Creation of Cybook 2416 (actually Gen4) repository

drivers/net/tokenring/3c359.h

@@ -0,0 +1,290 @@
+/*
+ *  3c359.h (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
+ *
+ *  Linux driver for 3Com 3C359 Token Link PCI XL cards.
+ *
+ *  This software may be used and distributed according to the terms
+ *  of the GNU General Public License Version 2 or (at your option) 
+ *  any later verion, incorporated herein by reference.
+ */
+
+/* Memory Access Commands */
+#define IO_BYTE_READ 0x28 << 24
+#define IO_BYTE_WRITE 0x18 << 24 
+#define IO_WORD_READ 0x20 << 24
+#define IO_WORD_WRITE 0x10 << 24
+#define MMIO_BYTE_READ 0x88 << 24
+#define MMIO_BYTE_WRITE 0x48 << 24
+#define MMIO_WORD_READ 0x80 << 24
+#define MMIO_WORD_WRITE 0x40 << 24
+#define MEM_BYTE_READ 0x8C << 24
+#define MEM_BYTE_WRITE 0x4C << 24
+#define MEM_WORD_READ 0x84 << 24
+#define MEM_WORD_WRITE 0x44 << 24
+
+#define PMBAR 0x1C80
+#define PMB_CPHOLD (1<<10)
+
+#define CPATTENTION 0x180D
+#define CPA_PMBARVIS (1<<7)
+#define CPA_MEMWREN (1<<6)
+
+#define SWITCHSETTINGS 0x1C88
+#define EECONTROL 0x1C8A
+#define EEDATA 0x1C8C
+#define EEREAD 0x0080 
+#define EEWRITE 0x0040
+#define EEERASE 0x0060
+#define EE_ENABLE_WRITE 0x0030
+#define EEBUSY (1<<15)
+
+#define WRBR 0xCDE02
+#define WWOR 0xCDE04
+#define WWCR 0xCDE06
+#define MACSTATUS 0xCDE08 
+#define MISR_RW 0xCDE0B
+#define MISR_AND 0xCDE2B
+#define MISR_SET 0xCDE4B
+#define RXBUFAREA 0xCDE10
+#define RXEARLYTHRESH 0xCDE12
+#define TXSTARTTHRESH 0x58
+#define DNPRIREQTHRESH 0x2C
+
+#define MISR_CSRB (1<<5)
+#define MISR_RASB (1<<4)
+#define MISR_SRBFR (1<<3)
+#define MISR_ASBFR (1<<2)
+#define MISR_ARBF (1<<1) 
+
+/* MISR Flags memory locations */
+#define MF_SSBF 0xDFFE0 
+#define MF_ARBF 0xDFFE1
+#define MF_ASBFR 0xDFFE2
+#define MF_SRBFR 0xDFFE3
+#define MF_RASB 0xDFFE4
+#define MF_CSRB 0xDFFE5
+
+#define MMIO_MACDATA 0x10 
+#define MMIO_MAC_ACCESS_CMD 0x14
+#define MMIO_TIMER 0x1A
+#define MMIO_DMA_CTRL 0x20
+#define MMIO_DNLISTPTR 0x24
+#define MMIO_HASHFILTER 0x28
+#define MMIO_CONFIG 0x29
+#define MMIO_DNPRIREQTHRESH 0x2C
+#define MMIO_DNPOLL 0x2D
+#define MMIO_UPPKTSTATUS 0x30
+#define MMIO_FREETIMER 0x34
+#define MMIO_COUNTDOWN 0x36
+#define MMIO_UPLISTPTR 0x38
+#define MMIO_UPPOLL 0x3C
+#define MMIO_UPBURSTTHRESH 0x40
+#define MMIO_DNBURSTTHRESH 0x41
+#define MMIO_INTSTATUS_AUTO 0x56
+#define MMIO_TXSTARTTHRESH 0x58
+#define MMIO_INTERRUPTENABLE 0x5A
+#define MMIO_INDICATIONENABLE 0x5C
+#define MMIO_COMMAND 0x5E  /* These two are meant to be the same */
+#define MMIO_INTSTATUS 0x5E /* Makes the code more readable this way */
+#define INTSTAT_CMD_IN_PROGRESS (1<<12) 
+#define INTSTAT_SRB (1<<14)
+#define INTSTAT_INTLATCH (1<<0)
+
+/* Indication / Interrupt Mask 
+ * Annoyingly the bits to be set in the indication and interrupt enable
+ * do not match with the actual bits received in the interrupt, although
+ * they are in the same order. 
+ * The mapping for the indication / interrupt are:
+ * Bit	Indication / Interrupt
+ *   0	HostError
+ *   1	txcomplete
+ *   2	updneeded
+ *   3	rxcomplete
+ *   4	intrequested
+ *   5	macerror
+ *   6  dncomplete
+ *   7	upcomplete
+ *   8	txunderrun
+ *   9	asbf
+ *  10	srbr
+ *  11	arbc
+ *
+ *  The only ones we don't want to receive are txcomplete and rxcomplete
+ *  we use dncomplete and upcomplete instead.
+ */
+
+#define INT_MASK 0xFF5
+
+/* Note the subtle difference here, IND and INT */
+
+#define SETINDENABLE (8<<12)
+#define SETINTENABLE (7<<12)
+#define SRBBIT (1<<10)
+#define ASBBIT (1<<9)
+#define ARBBIT (1<<11)
+
+#define SRB 0xDFE90
+#define ASB 0xDFED0
+#define ARB 0xD0000
+#define SCRATCH 0xDFEF0
+
+#define INT_REQUEST 0x6000 /* (6 << 12) */
+#define ACK_INTERRUPT 0x6800 /* (13 <<11) */
+#define GLOBAL_RESET 0x00 
+#define DNDISABLE 0x5000 
+#define DNENABLE 0x4800 
+#define DNSTALL 0x3002
+#define DNRESET 0x5800
+#define DNUNSTALL 0x3003
+#define UPRESET 0x2800
+#define UPSTALL 0x3000
+#define UPUNSTALL 0x3001
+#define SETCONFIG 0x4000
+#define SETTXSTARTTHRESH 0x9800 
+
+/* Received Interrupts */
+#define ASBFINT (1<<13)
+#define SRBRINT (1<<14)
+#define ARBCINT (1<<15)
+#define TXUNDERRUN (1<<11)
+
+#define UPCOMPINT (1<<10)
+#define DNCOMPINT (1<<9)
+#define HARDERRINT (1<<7)
+#define RXCOMPLETE (1<<4)
+#define TXCOMPINT (1<<2)
+#define HOSTERRINT (1<<1)
+
+/* Receive descriptor bits */
+#define RXOVERRUN (1<<19)
+#define RXFC (1<<21)
+#define RXAR (1<<22)
+#define RXUPDCOMPLETE (1<<23)
+#define RXUPDFULL (1<<24)
+#define RXUPLASTFRAG (1<<31)
+
+/* Transmit descriptor bits */
+#define TXDNCOMPLETE (1<<16)
+#define TXTXINDICATE (1<<27)
+#define TXDPDEMPTY (1<<29)
+#define TXDNINDICATE (1<<31)
+#define TXDNFRAGLAST (1<<31)
+
+/* Interrupts to Acknowledge */
+#define LATCH_ACK 1 
+#define TXCOMPACK (1<<1)
+#define INTREQACK (1<<2)
+#define DNCOMPACK (1<<3)
+#define UPCOMPACK (1<<4)
+#define ASBFACK (1<<5)
+#define SRBRACK (1<<6)
+#define ARBCACK (1<<7)
+
+#define XL_IO_SPACE 128
+#define SRB_COMMAND_SIZE 50
+
+/* Adapter Commands */
+#define REQUEST_INT 0x00
+#define MODIFY_OPEN_PARMS 0x01
+#define RESTORE_OPEN_PARMS 0x02
+#define OPEN_NIC 0x03
+#define CLOSE_NIC 0x04
+#define SET_SLEEP_MODE 0x05
+#define SET_GROUP_ADDRESS 0x06
+#define SET_FUNC_ADDRESS 0x07
+#define READ_LOG 0x08
+#define SET_MULTICAST_MODE 0x0C
+#define CHANGE_WAKEUP_PATTERN 0x0D
+#define GET_STATISTICS 0x13
+#define SET_RECEIVE_MODE 0x1F
+
+/* ARB Commands */
+#define RECEIVE_DATA 0x81
+#define RING_STATUS_CHANGE 0x84
+
+/* ASB Commands */
+#define ASB_RECEIVE_DATE 0x81 
+
+/* Defines for LAN STATUS CHANGE reports */
+#define LSC_SIG_LOSS 0x8000
+#define LSC_HARD_ERR 0x4000
+#define LSC_SOFT_ERR 0x2000
+#define LSC_TRAN_BCN 0x1000
+#define LSC_LWF      0x0800
+#define LSC_ARW      0x0400
+#define LSC_FPE      0x0200
+#define LSC_RR       0x0100
+#define LSC_CO       0x0080
+#define LSC_SS       0x0040
+#define LSC_RING_REC 0x0020
+#define LSC_SR_CO    0x0010
+#define LSC_FDX_MODE 0x0004
+
+#define XL_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
+
+/* 3c359 defaults for buffers */
+ 
+#define XL_RX_RING_SIZE 16 /* must be a power of 2 */
+#define XL_TX_RING_SIZE 16 /* must be a power of 2 */
+
+#define PKT_BUF_SZ 4096 /* Default packet size */
+
+/* 3c359 data structures */
+
+struct xl_tx_desc {
+	u32 dnnextptr ; 
+	u32 framestartheader ; 
+	u32 buffer ;
+	u32 buffer_length ;
+};
+
+struct xl_rx_desc {
+	u32 upnextptr ; 
+	u32 framestatus ; 
+	u32 upfragaddr ; 
+	u32 upfraglen ; 
+};
+
+struct xl_private {
+	
+
+	/* These two structures must be aligned on 8 byte boundaries */
+
+	/* struct xl_rx_desc xl_rx_ring[XL_RX_RING_SIZE]; */
+	/* struct xl_tx_desc xl_tx_ring[XL_TX_RING_SIZE]; */
+	struct xl_rx_desc *xl_rx_ring ; 
+	struct xl_tx_desc *xl_tx_ring ; 
+	struct sk_buff *tx_ring_skb[XL_TX_RING_SIZE], *rx_ring_skb[XL_RX_RING_SIZE];	
+	int tx_ring_head, tx_ring_tail ;  
+	int rx_ring_tail, rx_ring_no ; 
+	int free_ring_entries ; 
+
+	u16 srb;
+	u16 arb;
+	u16 asb;
+
+	u8 __iomem *xl_mmio;
+	char *xl_card_name;
+	struct pci_dev *pdev ; 
+	
+	spinlock_t xl_lock ; 
+
+	volatile int srb_queued;    
+	struct wait_queue *srb_wait;
+	volatile int asb_queued;   
+
+	struct net_device_stats xl_stats ;
+
+	u16 mac_buffer ; 	
+	u16 xl_lan_status ;
+	u8 xl_ring_speed ;
+	u16 pkt_buf_sz ; 
+	u8 xl_message_level; 
+	u16 xl_copy_all_options ;  
+	unsigned char xl_functional_addr[4] ; 
+	u16 xl_addr_table_addr, xl_parms_addr ; 
+	u8 xl_laa[6] ; 
+	u32 rx_ring_dma_addr ; 
+	u32 tx_ring_dma_addr ; 
+};
+

drivers/net/tokenring/Kconfig

@@ -0,0 +1,186 @@
+#
+# Token Ring driver configuration
+#
+
+menu "Token Ring devices"
+	depends on NETDEVICES && !UML
+
+# So far, we only have PCI, ISA, and MCA token ring devices
+config TR
+	bool "Token Ring driver support"
+	depends on (PCI || ISA || MCA || CCW)
+	select LLC
+	help
+	  Token Ring is IBM's way of communication on a local network; the
+	  rest of the world uses Ethernet. To participate on a Token Ring
+	  network, you need a special Token ring network card. If you are
+	  connected to such a Token Ring network and want to use your Token
+	  Ring card under Linux, say Y here and to the driver for your
+	  particular card below and read the Token-Ring mini-HOWTO, available
+	  from <http://www.tldp.org/docs.html#howto>. Most people can
+	  say N here.
+
+config IBMTR
+	tristate "IBM Tropic chipset based adapter support"
+	depends on TR && (ISA || MCA)
+	---help---
+	  This is support for all IBM Token Ring cards that don't use DMA. If
+	  you have such a beast, say Y and read the Token-Ring mini-HOWTO,
+	  available from <http://www.tldp.org/docs.html#howto>.
+
+	  Warning: this driver will almost definitely fail if more than one
+	  active Token Ring card is present.
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called ibmtr.
+
+config IBMOL
+	tristate "IBM Olympic chipset PCI adapter support"
+	depends on TR && PCI
+	---help---
+	  This is support for all non-Lanstreamer IBM PCI Token Ring Cards.
+	  Specifically this is all IBM PCI, PCI Wake On Lan, PCI II, PCI II
+	  Wake On Lan, and PCI 100/16/4 adapters.
+
+	  If you have such an adapter, say Y and read the Token-Ring
+	  mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called olympic.
+
+	  Also read <file:Documentation/networking/olympic.txt> or check the
+	  Linux Token Ring Project site for the latest information at
+	  <http://www.linuxtr.net/>.
+
+config IBMLS
+	tristate "IBM Lanstreamer chipset PCI adapter support"
+	depends on TR && PCI && !64BIT
+	help
+	  This is support for IBM Lanstreamer PCI Token Ring Cards.
+
+	  If you have such an adapter, say Y and read the Token-Ring
+	  mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called lanstreamer.
+
+config 3C359
+	tristate "3Com 3C359 Token Link Velocity XL adapter support"
+	depends on TR && PCI
+	---help---
+	  This is support for the 3Com PCI Velocity XL cards, specifically
+	  the 3Com 3C359, please note this is not for the 3C339 cards, you
+	  should use the tms380 driver instead.
+
+	  If you have such an adapter, say Y and read the Token-Ring
+	  mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called 3c359.
+
+	  Also read the file <file:Documentation/networking/3c359.txt> or check the 
+	  Linux Token Ring Project site for the latest information at
+	  <http://www.linuxtr.net>
+
+config TMS380TR
+	tristate "Generic TMS380 Token Ring ISA/PCI adapter support"
+	depends on TR && (PCI || ISA && ISA_DMA_API || MCA)
+	select FW_LOADER
+	---help---
+	  This driver provides generic support for token ring adapters
+	  based on the Texas Instruments TMS380 series chipsets.  This
+	  includes the SysKonnect TR4/16(+) ISA (SK-4190), SysKonnect
+	  TR4/16(+) PCI (SK-4590), SysKonnect TR4/16 PCI (SK-4591),
+	  Compaq 4/16 PCI, Thomas-Conrad TC4048 4/16 PCI, and several
+	  Madge adapters.  If you say Y here, you will be asked to select
+	  which cards to support below.  If you're using modules, each
+	  class of card will be supported by a separate module.
+
+	  If you have such an adapter and would like to use it, say Y and
+	  read the Token-Ring mini-HOWTO, available from
+	  <http://www.tldp.org/docs.html#howto>.
+
+	  Also read the file <file:Documentation/networking/tms380tr.txt> or
+	  check <http://www.auk.cx/tms380tr/>.
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called tms380tr.
+
+config TMSPCI
+	tristate "Generic TMS380 PCI support"
+	depends on TR && TMS380TR && PCI
+	---help---
+	  This tms380 module supports generic TMS380-based PCI cards.
+
+	  These cards are known to work:
+	  - Compaq 4/16 TR PCI
+	  - SysKonnect TR4/16 PCI (SK-4590/SK-4591)
+	  - Thomas-Conrad TC4048 PCI 4/16
+	  - 3Com Token Link Velocity
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called tmspci.
+
+config SKISA
+	tristate "SysKonnect TR4/16 ISA support"
+	depends on TR && TMS380TR && ISA
+	help
+	  This tms380 module supports SysKonnect TR4/16 ISA cards.
+
+	  These cards are known to work:
+	  - SysKonnect TR4/16 ISA (SK-4190)
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called skisa.
+
+config PROTEON
+	tristate "Proteon ISA support"
+	depends on TR && TMS380TR && ISA
+	help
+	  This tms380 module supports Proteon ISA cards.
+
+	  These cards are known to work:
+	  - Proteon 1392
+	  - Proteon 1392 plus
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called proteon.
+
+config ABYSS
+	tristate "Madge Smart 16/4 PCI Mk2 support"
+	depends on TR && TMS380TR && PCI
+	help
+	  This tms380 module supports the Madge Smart 16/4 PCI Mk2
+	  cards (51-02).
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called abyss.
+
+config MADGEMC
+	tristate "Madge Smart 16/4 Ringnode MicroChannel"
+	depends on TR && TMS380TR && MCA
+	help
+	  This tms380 module supports the Madge Smart 16/4 MC16 and MC32
+	  MicroChannel adapters.
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called madgemc.
+
+config SMCTR
+	tristate "SMC ISA/MCA adapter support"
+	depends on TR && (ISA || MCA_LEGACY) && (BROKEN || !64BIT)
+	---help---
+	  This is support for the ISA and MCA SMC Token Ring cards,
+	  specifically SMC TokenCard Elite (8115T) and SMC TokenCard Elite/A
+	  (8115T/A) adapters.
+
+	  If you have such an adapter and would like to use it, say Y or M and
+	  read the Token-Ring mini-HOWTO, available from
+	  <http://www.tldp.org/docs.html#howto> and the file
+	  <file:Documentation/networking/smctr.txt>.
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called smctr.
+
+endmenu
+

drivers/net/tokenring/Makefile

@@ -0,0 +1,15 @@
+#
+# Makefile for drivers/net/tokenring
+#
+
+obj-$(CONFIG_IBMTR) 	+= ibmtr.o
+obj-$(CONFIG_IBMOL) 	+= olympic.o
+obj-$(CONFIG_IBMLS) 	+= lanstreamer.o
+obj-$(CONFIG_TMS380TR) 	+= tms380tr.o
+obj-$(CONFIG_ABYSS) 	+= abyss.o
+obj-$(CONFIG_MADGEMC) 	+= madgemc.o
+obj-$(CONFIG_PROTEON) 	+= proteon.o
+obj-$(CONFIG_TMSPCI) 	+= tmspci.o
+obj-$(CONFIG_SKISA) 	+= skisa.o
+obj-$(CONFIG_SMCTR) 	+= smctr.o
+obj-$(CONFIG_3C359)	+= 3c359.o

drivers/net/tokenring/abyss.c

@@ -0,0 +1,469 @@
+/*
+ *  abyss.c: Network driver for the Madge Smart 16/4 PCI Mk2 token ring card.
+ *
+ *  Written 1999-2000 by Adam Fritzler
+ *
+ *  This software may be used and distributed according to the terms
+ *  of the GNU General Public License, incorporated herein by reference.
+ *
+ *  This driver module supports the following cards:
+ *      - Madge Smart 16/4 PCI Mk2
+ *
+ *  Maintainer(s):
+ *    AF	Adam Fritzler		mid@auk.cx
+ *
+ *  Modification History:
+ *	30-Dec-99	AF	Split off from the tms380tr driver.
+ *	22-Jan-00	AF	Updated to use indirect read/writes 
+ *	23-Nov-00	JG	New PCI API, cleanups
+ *
+ *
+ *  TODO:
+ *	1. See if we can use MMIO instead of inb/outb/inw/outw
+ *	2. Add support for Mk1 (has AT24 attached to the PCI
+ *		config registers)
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/trdevice.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "tms380tr.h"
+#include "abyss.h"            /* Madge-specific constants */
+
+static char version[] __devinitdata =
+"abyss.c: v1.02 23/11/2000 by Adam Fritzler\n";
+
+#define ABYSS_IO_EXTENT 64
+
+static struct pci_device_id abyss_pci_tbl[] = {
+	{ PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_MK2,
+	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_TOKEN_RING << 8, 0x00ffffff, },
+	{ }			/* Terminating entry */
+};
+MODULE_DEVICE_TABLE(pci, abyss_pci_tbl);
+
+MODULE_LICENSE("GPL");
+
+static int abyss_open(struct net_device *dev);
+static int abyss_close(struct net_device *dev);
+static void abyss_enable(struct net_device *dev);
+static int abyss_chipset_init(struct net_device *dev);
+static void abyss_read_eeprom(struct net_device *dev);
+static unsigned short abyss_setnselout_pins(struct net_device *dev);
+
+static void at24_writedatabyte(unsigned long regaddr, unsigned char byte);
+static int at24_sendfullcmd(unsigned long regaddr, unsigned char cmd, unsigned char addr);
+static int at24_sendcmd(unsigned long regaddr, unsigned char cmd);
+static unsigned char at24_readdatabit(unsigned long regaddr);
+static unsigned char at24_readdatabyte(unsigned long regaddr);
+static int at24_waitforack(unsigned long regaddr);
+static int at24_waitfornack(unsigned long regaddr);
+static void at24_setlines(unsigned long regaddr, unsigned char clock, unsigned char data);
+static void at24_start(unsigned long regaddr);
+static unsigned char at24_readb(unsigned long regaddr, unsigned char addr);
+
+static unsigned short abyss_sifreadb(struct net_device *dev, unsigned short reg)
+{
+	return inb(dev->base_addr + reg);
+}
+
+static unsigned short abyss_sifreadw(struct net_device *dev, unsigned short reg)
+{
+	return inw(dev->base_addr + reg);
+}
+
+static void abyss_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
+{
+	outb(val, dev->base_addr + reg);
+}
+
+static void abyss_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
+{
+	outw(val, dev->base_addr + reg);
+}
+
+static int __devinit abyss_attach(struct pci_dev *pdev, const struct pci_device_id *ent)
+{	
+	static int versionprinted;
+	struct net_device *dev;
+	struct net_local *tp;
+	int i, ret, pci_irq_line;
+	unsigned long pci_ioaddr;
+	
+	if (versionprinted++ == 0)
+		printk("%s", version);
+
+	if (pci_enable_device(pdev))
+		return -EIO;
+
+	/* Remove I/O space marker in bit 0. */
+	pci_irq_line = pdev->irq;
+	pci_ioaddr = pci_resource_start (pdev, 0);
+		
+	/* At this point we have found a valid card. */
+		
+	dev = alloc_trdev(sizeof(struct net_local));
+	if (!dev)
+		return -ENOMEM;
+
+	SET_MODULE_OWNER(dev);
+
+	if (!request_region(pci_ioaddr, ABYSS_IO_EXTENT, dev->name)) {
+		ret = -EBUSY;
+		goto err_out_trdev;
+	}
+		
+	ret = request_irq(pdev->irq, tms380tr_interrupt, IRQF_SHARED,
+			  dev->name, dev);
+	if (ret)
+		goto err_out_region;
+		
+	dev->base_addr	= pci_ioaddr;
+	dev->irq	= pci_irq_line;
+		
+	printk("%s: Madge Smart 16/4 PCI Mk2 (Abyss)\n", dev->name);
+	printk("%s:    IO: %#4lx  IRQ: %d\n",
+	       dev->name, pci_ioaddr, dev->irq);
+	/*
+	 * The TMS SIF registers lay 0x10 above the card base address.
+	 */
+	dev->base_addr += 0x10;
+		
+	ret = tmsdev_init(dev, &pdev->dev);
+	if (ret) {
+		printk("%s: unable to get memory for dev->priv.\n", 
+		       dev->name);
+		goto err_out_irq;
+	}
+
+	abyss_read_eeprom(dev);
+		
+	printk("%s:    Ring Station Address: ", dev->name);
+	printk("%2.2x", dev->dev_addr[0]);
+	for (i = 1; i < 6; i++)
+		printk(":%2.2x", dev->dev_addr[i]);
+	printk("\n");
+
+	tp = netdev_priv(dev);
+	tp->setnselout = abyss_setnselout_pins;
+	tp->sifreadb = abyss_sifreadb;
+	tp->sifreadw = abyss_sifreadw;
+	tp->sifwriteb = abyss_sifwriteb;
+	tp->sifwritew = abyss_sifwritew;
+
+	memcpy(tp->ProductID, "Madge PCI 16/4 Mk2", PROD_ID_SIZE + 1);
+		
+	dev->open = abyss_open;
+	dev->stop = abyss_close;
+
+	pci_set_drvdata(pdev, dev);
+	SET_NETDEV_DEV(dev, &pdev->dev);
+
+	ret = register_netdev(dev);
+	if (ret)
+		goto err_out_tmsdev;
+	return 0;
+
+err_out_tmsdev:
+	pci_set_drvdata(pdev, NULL);
+	tmsdev_term(dev);
+err_out_irq:
+	free_irq(pdev->irq, dev);
+err_out_region:
+	release_region(pci_ioaddr, ABYSS_IO_EXTENT);
+err_out_trdev:
+	free_netdev(dev);
+	return ret;
+}
+
+static unsigned short abyss_setnselout_pins(struct net_device *dev)
+{
+	unsigned short val = 0;
+	struct net_local *tp = netdev_priv(dev);
+	
+	if(tp->DataRate == SPEED_4)
+		val |= 0x01;  /* Set 4Mbps */
+	else
+		val |= 0x00;  /* Set 16Mbps */
+	
+	return val;
+}
+
+/*
+ * The following Madge boards should use this code:
+ *   - Smart 16/4 PCI Mk2 (Abyss)
+ *   - Smart 16/4 PCI Mk1 (PCI T)
+ *   - Smart 16/4 Client Plus PnP (Big Apple)
+ *   - Smart 16/4 Cardbus Mk2
+ *
+ * These access an Atmel AT24 SEEPROM using their glue chip registers. 
+ *
+ */
+static void at24_writedatabyte(unsigned long regaddr, unsigned char byte)
+{
+	int i;
+	
+	for (i = 0; i < 8; i++) {
+		at24_setlines(regaddr, 0, (byte >> (7-i))&0x01);
+		at24_setlines(regaddr, 1, (byte >> (7-i))&0x01);
+		at24_setlines(regaddr, 0, (byte >> (7-i))&0x01);
+	}
+}
+
+static int at24_sendfullcmd(unsigned long regaddr, unsigned char cmd, unsigned char addr)
+{
+	if (at24_sendcmd(regaddr, cmd)) {
+		at24_writedatabyte(regaddr, addr);
+		return at24_waitforack(regaddr);
+	}
+	return 0;
+}
+
+static int at24_sendcmd(unsigned long regaddr, unsigned char cmd)
+{
+	int i;
+	
+	for (i = 0; i < 10; i++) {
+		at24_start(regaddr);
+		at24_writedatabyte(regaddr, cmd);
+		if (at24_waitforack(regaddr))
+			return 1;
+	}
+	return 0;
+}
+
+static unsigned char at24_readdatabit(unsigned long regaddr)
+{
+	unsigned char val;
+
+	at24_setlines(regaddr, 0, 1);
+	at24_setlines(regaddr, 1, 1);
+	val = (inb(regaddr) & AT24_DATA)?1:0;
+	at24_setlines(regaddr, 1, 1);
+	at24_setlines(regaddr, 0, 1);
+	return val;
+}
+
+static unsigned char at24_readdatabyte(unsigned long regaddr)
+{
+	unsigned char data = 0;
+	int i;
+	
+	for (i = 0; i < 8; i++) {
+		data <<= 1;
+		data |= at24_readdatabit(regaddr);
+	}
+
+	return data;
+}
+
+static int at24_waitforack(unsigned long regaddr)
+{
+	int i;
+	
+	for (i = 0; i < 10; i++) {
+		if ((at24_readdatabit(regaddr) & 0x01) == 0x00)
+			return 1;
+	}
+	return 0;
+}
+
+static int at24_waitfornack(unsigned long regaddr)
+{
+	int i;
+	for (i = 0; i < 10; i++) {
+		if ((at24_readdatabit(regaddr) & 0x01) == 0x01)
+			return 1;
+	}
+	return 0;
+}
+
+static void at24_setlines(unsigned long regaddr, unsigned char clock, unsigned char data)
+{
+	unsigned char val = AT24_ENABLE;
+	if (clock)
+		val |= AT24_CLOCK;
+	if (data)
+		val |= AT24_DATA;
+
+	outb(val, regaddr); 
+	tms380tr_wait(20); /* Very necessary. */
+}
+
+static void at24_start(unsigned long regaddr)
+{
+	at24_setlines(regaddr, 0, 1);
+	at24_setlines(regaddr, 1, 1);
+	at24_setlines(regaddr, 1, 0);
+	at24_setlines(regaddr, 0, 1);
+}
+
+static unsigned char at24_readb(unsigned long regaddr, unsigned char addr)
+{
+	unsigned char data = 0xff;
+	
+	if (at24_sendfullcmd(regaddr, AT24_WRITE, addr)) {
+		if (at24_sendcmd(regaddr, AT24_READ)) {
+			data = at24_readdatabyte(regaddr);
+			if (!at24_waitfornack(regaddr))
+				data = 0xff;
+		}
+	}
+	return data;
+}
+
+
+/*
+ * Enable basic functions of the Madge chipset needed
+ * for initialization.
+ */
+static void abyss_enable(struct net_device *dev)
+{
+	unsigned char reset_reg;
+	unsigned long ioaddr;
+	
+	ioaddr = dev->base_addr;
+	reset_reg = inb(ioaddr + PCIBM2_RESET_REG);
+	reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
+	outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
+	tms380tr_wait(100);
+}
+
+/*
+ * Enable the functions of the Madge chipset needed for
+ * full working order. 
+ */
+static int abyss_chipset_init(struct net_device *dev)
+{
+	unsigned char reset_reg;
+	unsigned long ioaddr;
+	
+	ioaddr = dev->base_addr;
+	
+	reset_reg = inb(ioaddr + PCIBM2_RESET_REG);
+	
+	reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
+	outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
+	
+	reset_reg &= ~(PCIBM2_RESET_REG_CHIP_NRES |
+		       PCIBM2_RESET_REG_FIFO_NRES | 
+		       PCIBM2_RESET_REG_SIF_NRES);
+	outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
+	
+	tms380tr_wait(100);
+	
+	reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
+	outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
+	
+	reset_reg |= PCIBM2_RESET_REG_SIF_NRES;
+	outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
+
+	reset_reg |= PCIBM2_RESET_REG_FIFO_NRES;
+	outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
+
+	outb(PCIBM2_INT_CONTROL_REG_SINTEN | 
+	     PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE, 
+	     ioaddr + PCIBM2_INT_CONTROL_REG);
+  
+	outb(30, ioaddr + PCIBM2_FIFO_THRESHOLD);
+	
+	return 0;
+}
+
+static inline void abyss_chipset_close(struct net_device *dev)
+{
+	unsigned long ioaddr;
+	
+	ioaddr = dev->base_addr;
+	outb(0, ioaddr + PCIBM2_RESET_REG);
+}
+
+/*
+ * Read configuration data from the AT24 SEEPROM on Madge cards.
+ *
+ */
+static void abyss_read_eeprom(struct net_device *dev)
+{
+	struct net_local *tp;
+	unsigned long ioaddr;
+	unsigned short val;
+	int i;
+	
+	tp = netdev_priv(dev);
+	ioaddr = dev->base_addr;
+	
+	/* Must enable glue chip first */
+	abyss_enable(dev);
+	
+	val = at24_readb(ioaddr + PCIBM2_SEEPROM_REG, 
+			 PCIBM2_SEEPROM_RING_SPEED);
+	tp->DataRate = val?SPEED_4:SPEED_16; /* set open speed */
+	printk("%s:    SEEPROM: ring speed: %dMb/sec\n", dev->name, tp->DataRate);
+	
+	val = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
+			 PCIBM2_SEEPROM_RAM_SIZE) * 128;
+	printk("%s:    SEEPROM: adapter RAM: %dkb\n", dev->name, val);
+	
+	dev->addr_len = 6;
+	for (i = 0; i < 6; i++) 
+		dev->dev_addr[i] = at24_readb(ioaddr + PCIBM2_SEEPROM_REG, 
+					      PCIBM2_SEEPROM_BIA+i);
+}
+
+static int abyss_open(struct net_device *dev)
+{  
+	abyss_chipset_init(dev);
+	tms380tr_open(dev);
+	return 0;
+}
+
+static int abyss_close(struct net_device *dev)
+{
+	tms380tr_close(dev);
+	abyss_chipset_close(dev);
+	return 0;
+}
+
+static void __devexit abyss_detach (struct pci_dev *pdev)
+{
+	struct net_device *dev = pci_get_drvdata(pdev);
+	
+	BUG_ON(!dev);
+	unregister_netdev(dev);
+	release_region(dev->base_addr-0x10, ABYSS_IO_EXTENT);
+	free_irq(dev->irq, dev);
+	tmsdev_term(dev);
+	free_netdev(dev);
+	pci_set_drvdata(pdev, NULL);
+}
+
+static struct pci_driver abyss_driver = {
+	.name		= "abyss",
+	.id_table	= abyss_pci_tbl,
+	.probe		= abyss_attach,
+	.remove		= __devexit_p(abyss_detach),
+};
+
+static int __init abyss_init (void)
+{
+	return pci_register_driver(&abyss_driver);
+}
+
+static void __exit abyss_rmmod (void)
+{
+	pci_unregister_driver (&abyss_driver);
+}
+
+module_init(abyss_init);
+module_exit(abyss_rmmod);
+

drivers/net/tokenring/abyss.h

@@ -0,0 +1,58 @@
+/* 
+ * abyss.h: Header for the abyss tms380tr module
+ *
+ * Authors:
+ * - Adam Fritzler <mid@auk.cx>
+ */
+
+#ifndef __LINUX_MADGETR_H
+#define __LINUX_MADGETR_H
+
+#ifdef __KERNEL__
+
+/*
+ * For Madge Smart 16/4 PCI Mk2.  Since we increment the base address
+ * to get everything correct for the TMS SIF, we do these as negatives
+ * as they fall below the SIF in addressing.
+ */
+#define PCIBM2_INT_STATUS_REG          ((short)-15)/* 0x01 */
+#define PCIBM2_INT_CONTROL_REG         ((short)-14)/* 0x02 */
+#define PCIBM2_RESET_REG               ((short)-12)/* 0x04 */
+#define PCIBM2_SEEPROM_REG             ((short)-9) /* 0x07 */
+
+#define PCIBM2_INT_CONTROL_REG_SINTEN           0x02
+#define PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE   0x80
+#define PCIBM2_INT_STATUS_REG_PCI_ERR           0x80
+
+#define PCIBM2_RESET_REG_CHIP_NRES              0x01
+#define PCIBM2_RESET_REG_FIFO_NRES              0x02
+#define PCIBM2_RESET_REG_SIF_NRES               0x04
+
+#define PCIBM2_FIFO_THRESHOLD   0x21
+#define PCIBM2_BURST_LENGTH     0x22
+
+/*
+ * Bits in PCIBM2_SEEPROM_REG.
+ */
+#define AT24_ENABLE             0x04
+#define AT24_DATA               0x02
+#define AT24_CLOCK              0x01
+
+/*
+ * AT24 Commands.
+ */
+#define AT24_WRITE              0xA0
+#define AT24_READ               0xA1
+
+/*
+ * Addresses in AT24 SEEPROM.
+ */
+#define PCIBM2_SEEPROM_BIA          0x12
+#define PCIBM2_SEEPROM_RING_SPEED   0x18
+#define PCIBM2_SEEPROM_RAM_SIZE     0x1A
+#define PCIBM2_SEEPROM_HWF1         0x1C
+#define PCIBM2_SEEPROM_HWF2         0x1E
+
+
+#endif /* __KERNEL__ */
+#endif /* __LINUX_MADGETR_H */

drivers/net/tokenring/lanstreamer.h

@@ -0,0 +1,346 @@
+/*
+ *   lanstreamer.h -- driver for the IBM Auto LANStreamer PCI Adapter
+ *
+ *  Written By: Mike Sullivan, IBM Corporation
+ *
+ *  Copyright (C) 1999 IBM Corporation
+ *
+ *  Linux driver for IBM PCI tokenring cards based on the LanStreamer MPC
+ *  chipset. 
+ *
+ *  This driver is based on the olympic driver for IBM PCI TokenRing cards (Pit/Pit-Phy/Olympic
+ *  chipsets) written  by:
+ *      1999 Peter De Schrijver All Rights Reserved
+ *	1999 Mike Phillips (phillim@amtrak.com)
+ *
+ *  Base Driver Skeleton:
+ *      Written 1993-94 by Donald Becker.
+ *
+ *      Copyright 1993 United States Government as represented by the
+ *      Director, National Security Agency.
+ *
+ * This program is free software; you can redistribute it and/or modify      
+ * it under the terms of the GNU General Public License as published by      
+ * the Free Software Foundation; either version 2 of the License, or         
+ * (at your option) any later version.                                       
+ *                                                                           
+ * This program is distributed in the hope that it will be useful,           
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of            
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             
+ * GNU General Public License for more details.                              
+ *                                                                           
+ * NO WARRANTY                                                               
+ * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR        
+ * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT      
+ * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,      
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is    
+ * solely responsible for determining the appropriateness of using and       
+ * distributing the Program and assumes all risks associated with its        
+ * exercise of rights under this Agreement, including but not limited to     
+ * the risks and costs of program errors, damage to or loss of data,         
+ * programs or equipment, and unavailability or interruption of operations.  
+ *                                                                           
+ * DISCLAIMER OF LIABILITY                                                   
+ * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY   
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL        
+ * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND   
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR     
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE    
+ * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED  
+ * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES             
+ *                                                                           
+ * You should have received a copy of the GNU General Public License         
+ * along with this program; if not, write to the Free Software               
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+ *                                                                           
+ * 
+ *  12/10/99 - Alpha Release 0.1.0
+ *            First release to the public
+ *  08/15/01 - Added ioctl() definitions and others - Kent Yoder <yoder1@us.ibm.com>
+ *
+ */
+
+#include <linux/version.h>
+
+/* MAX_INTR - the maximum number of times we can loop
+ * inside the interrupt function before returning
+ * control to the OS (maximum value is 256)
+ */
+#define MAX_INTR 5
+
+#define CLS 0x0C
+#define MLR 0x86
+#define LTR 0x0D
+
+#define BCTL 0x60
+#define BCTL_SOFTRESET (1<<15)
+#define BCTL_RX_FIFO_8 (1<<1)
+#define BCTL_TX_FIFO_8 (1<<3)
+
+#define GPR 0x4a
+#define GPR_AUTOSENSE (1<<2)
+#define GPR_16MBPS (1<<3)
+
+#define LISR 0x10
+#define LISR_SUM 0x12
+#define LISR_RUM 0x14
+
+#define LISR_LIE (1<<15)
+#define LISR_SLIM (1<<13)
+#define LISR_SLI (1<<12)
+#define LISR_BPEI (1<<9)
+#define LISR_BPE (1<<8)
+#define LISR_SRB_CMD (1<<5)
+#define LISR_ASB_REPLY (1<<4)
+#define LISR_ASB_FREE_REQ (1<<2)
+#define LISR_ARB_FREE (1<<1)
+#define LISR_TRB_FRAME (1<<0)
+
+#define SISR 0x16
+#define SISR_SUM 0x18
+#define SISR_RUM 0x1A
+#define SISR_MASK 0x54
+#define SISR_MASK_SUM 0x56
+#define SISR_MASK_RUM 0x58
+
+#define SISR_MI (1<<15)
+#define SISR_SERR_ERR (1<<14)
+#define SISR_TIMER (1<<11)
+#define SISR_LAP_PAR_ERR (1<<10)
+#define SISR_LAP_ACC_ERR (1<<9)
+#define SISR_PAR_ERR (1<<8)
+#define SISR_ADAPTER_CHECK (1<<6)
+#define SISR_SRB_REPLY (1<<5)
+#define SISR_ASB_FREE (1<<4)
+#define SISR_ARB_CMD (1<<3)
+#define SISR_TRB_REPLY (1<<2)
+
+#define MISR_RUM 0x5A
+#define MISR_MASK 0x5C
+#define MISR_MASK_RUM 0x5E
+
+#define MISR_TX2_IDLE (1<<15)
+#define MISR_TX2_NO_STATUS (1<<14)
+#define MISR_TX2_HALT (1<<13)
+#define MISR_TX2_EOF (1<<12)
+#define MISR_TX1_IDLE (1<<11)
+#define MISR_TX1_NO_STATUS (1<<10)
+#define MISR_TX1_HALT (1<<9)
+#define MISR_TX1_EOF (1<<8)
+#define MISR_RX_NOBUF (1<<5)
+#define MISR_RX_EOB (1<<4)
+#define MISR_RX_NO_STATUS (1<<2)
+#define MISR_RX_HALT (1<<1)
+#define MISR_RX_EOF (1<<0)
+
+#define LAPA 0x62
+#define LAPE 0x64
+#define LAPD 0x66
+#define LAPDINC 0x68
+#define LAPWWO 0x6A
+#define LAPWWC 0x6C
+#define LAPCTL 0x6E
+
+#define TIMER 0x4E4
+
+#define BMCTL_SUM 0x50
+#define BMCTL_RUM 0x52
+#define BMCTL_TX1_DIS (1<<14)
+#define BMCTL_TX2_DIS (1<<10)
+#define BMCTL_RX_DIS (1<<6)
+#define BMCTL_RX_ENABLED  (1<<5)
+
+#define RXLBDA  0x90
+#define RXBDA   0x94
+#define RXSTAT  0x98
+#define RXDBA   0x9C
+
+#define TX1LFDA 0xA0
+#define TX1FDA  0xA4
+#define TX1STAT 0xA8
+#define TX1DBA  0xAC
+#define TX2LFDA 0xB0
+#define TX2FDA  0xB4
+#define TX2STAT 0xB8
+#define TX2DBA  0xBC
+
+#define STREAMER_IO_SPACE 256
+
+#define SRB_COMMAND_SIZE 50
+
+#define STREAMER_MAX_ADAPTERS 8	/* 0x08 __MODULE_STRING can't hand 0xnn */
+
+/* Defines for LAN STATUS CHANGE reports */
+#define LSC_SIG_LOSS 0x8000
+#define LSC_HARD_ERR 0x4000
+#define LSC_SOFT_ERR 0x2000
+#define LSC_TRAN_BCN 0x1000
+#define LSC_LWF      0x0800
+#define LSC_ARW      0x0400
+#define LSC_FPE      0x0200
+#define LSC_RR       0x0100
+#define LSC_CO       0x0080
+#define LSC_SS       0x0040
+#define LSC_RING_REC 0x0020
+#define LSC_SR_CO    0x0010
+#define LSC_FDX_MODE 0x0004
+
+/* Defines for OPEN ADAPTER command */
+
+#define OPEN_ADAPTER_EXT_WRAP (1<<15)
+#define OPEN_ADAPTER_DIS_HARDEE (1<<14)
+#define OPEN_ADAPTER_DIS_SOFTERR (1<<13)
+#define OPEN_ADAPTER_PASS_ADC_MAC (1<<12)
+#define OPEN_ADAPTER_PASS_ATT_MAC (1<<11)
+#define OPEN_ADAPTER_ENABLE_EC (1<<10)
+#define OPEN_ADAPTER_CONTENDER (1<<8)
+#define OPEN_ADAPTER_PASS_BEACON (1<<7)
+#define OPEN_ADAPTER_ENABLE_FDX (1<<6)
+#define OPEN_ADAPTER_ENABLE_RPL (1<<5)
+#define OPEN_ADAPTER_INHIBIT_ETR (1<<4)
+#define OPEN_ADAPTER_INTERNAL_WRAP (1<<3)
+
+
+/* Defines for SRB Commands */
+#define SRB_CLOSE_ADAPTER 0x04
+#define SRB_CONFIGURE_BRIDGE 0x0c
+#define SRB_CONFIGURE_HP_CHANNEL 0x13
+#define SRB_MODIFY_BRIDGE_PARMS 0x15
+#define SRB_MODIFY_OPEN_OPTIONS 0x01
+#define SRB_MODIFY_RECEIVE_OPTIONS 0x17
+#define SRB_NO_OPERATION 0x00
+#define SRB_OPEN_ADAPTER 0x03
+#define SRB_READ_LOG 0x08
+#define SRB_READ_SR_COUNTERS 0x16
+#define SRB_RESET_GROUP_ADDRESS 0x02
+#define SRB_RESET_TARGET_SEGMETN 0x14
+#define SRB_SAVE_CONFIGURATION 0x1b
+#define SRB_SET_BRIDGE_PARMS 0x09
+#define SRB_SET_FUNC_ADDRESS 0x07
+#define SRB_SET_GROUP_ADDRESS 0x06
+#define SRB_SET_TARGET_SEGMENT 0x05
+
+/* Clear return code */
+#define STREAMER_CLEAR_RET_CODE 0xfe
+
+/* ARB Commands */
+#define ARB_RECEIVE_DATA 0x81
+#define ARB_LAN_CHANGE_STATUS 0x84
+
+/* ASB Response commands */
+#define ASB_RECEIVE_DATA 0x81
+
+
+/* Streamer defaults for buffers */
+
+#define STREAMER_RX_RING_SIZE 16	/* should be a power of 2 */
+/* Setting the number of TX descriptors to 1 is a workaround for an
+ * undocumented hardware problem with the lanstreamer board. Setting
+ * this to something higher may slightly increase the throughput you
+ * can get from the card, but at the risk of locking up the box. - 
+ * <yoder1@us.ibm.com>
+ */
+#define STREAMER_TX_RING_SIZE 1	/* should be a power of 2 */
+
+#define PKT_BUF_SZ 4096		/* Default packet size */
+
+/* Streamer data structures */
+
+struct streamer_tx_desc {
+	__u32 forward;
+	__u32 status;
+	__u32 bufcnt_framelen;
+	__u32 buffer;
+	__u32 buflen;
+	__u32 rsvd1;
+	__u32 rsvd2;
+	__u32 rsvd3;
+};
+
+struct streamer_rx_desc {
+	__u32 forward;
+	__u32 status;
+	__u32 buffer;
+	__u32 framelen_buflen;
+};
+
+struct mac_receive_buffer {
+	__u16 next;
+	__u8 padding;
+	__u8 frame_status;
+	__u16 buffer_length;
+	__u8 frame_data;
+};
+
+struct streamer_private {
+
+	__u16 srb;
+	__u16 trb;
+	__u16 arb;
+	__u16 asb;
+
+        struct streamer_private *next;
+        struct pci_dev *pci_dev;
+	__u8 __iomem *streamer_mmio;
+        char *streamer_card_name;
+ 
+        spinlock_t streamer_lock;
+
+	volatile int srb_queued;	/* True if an SRB is still posted */
+	wait_queue_head_t srb_wait;
+
+	volatile int asb_queued;	/* True if an ASB is posted */
+
+	volatile int trb_queued;	/* True if a TRB is posted */
+	wait_queue_head_t trb_wait;
+
+	struct streamer_rx_desc *streamer_rx_ring;
+	struct streamer_tx_desc *streamer_tx_ring;
+	struct sk_buff *tx_ring_skb[STREAMER_TX_RING_SIZE],
+	    *rx_ring_skb[STREAMER_RX_RING_SIZE];
+	int tx_ring_free, tx_ring_last_status, rx_ring_last_received,
+	    free_tx_ring_entries;
+
+	struct net_device_stats streamer_stats;
+	__u16 streamer_lan_status;
+	__u8 streamer_ring_speed;
+	__u16 pkt_buf_sz;
+	__u8 streamer_receive_options, streamer_copy_all_options,
+	    streamer_message_level;
+	__u16 streamer_addr_table_addr, streamer_parms_addr;
+	__u16 mac_rx_buffer;
+	__u8 streamer_laa[6];
+};
+
+struct streamer_adapter_addr_table {
+
+	__u8 node_addr[6];
+	__u8 reserved[4];
+	__u8 func_addr[4];
+};
+
+struct streamer_parameters_table {
+
+	__u8 phys_addr[4];
+	__u8 up_node_addr[6];
+	__u8 up_phys_addr[4];
+	__u8 poll_addr[6];
+	__u16 reserved;
+	__u16 acc_priority;
+	__u16 auth_source_class;
+	__u16 att_code;
+	__u8 source_addr[6];
+	__u16 beacon_type;
+	__u16 major_vector;
+	__u16 lan_status;
+	__u16 soft_error_time;
+	__u16 reserved1;
+	__u16 local_ring;
+	__u16 mon_error;
+	__u16 beacon_transmit;
+	__u16 beacon_receive;
+	__u16 frame_correl;
+	__u8 beacon_naun[6];
+	__u32 reserved2;
+	__u8 beacon_phys[4];
+};

drivers/net/tokenring/madgemc.c

@@ -0,0 +1,784 @@
+/*
+ *  madgemc.c: Driver for the Madge Smart 16/4 MC16 MCA token ring card.
+ *
+ *  Written 2000 by Adam Fritzler
+ *
+ *  This software may be used and distributed according to the terms
+ *  of the GNU General Public License, incorporated herein by reference.
+ *
+ *  This driver module supports the following cards:
+ *      - Madge Smart 16/4 Ringnode MC16
+ *	- Madge Smart 16/4 Ringnode MC32 (??)
+ *
+ *  Maintainer(s):
+ *    AF	Adam Fritzler		mid@auk.cx
+ *
+ *  Modification History:
+ *	16-Jan-00	AF	Created
+ *
+ */
+static const char version[] = "madgemc.c: v0.91 23/01/2000 by Adam Fritzler\n";
+
+#include <linux/module.h>
+#include <linux/mca.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/trdevice.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "tms380tr.h"
+#include "madgemc.h"            /* Madge-specific constants */
+
+#define MADGEMC_IO_EXTENT 32
+#define MADGEMC_SIF_OFFSET 0x08
+
+struct card_info {
+	/*
+	 * These are read from the BIA ROM.
+	 */
+	unsigned int manid;
+	unsigned int cardtype;
+	unsigned int cardrev;
+	unsigned int ramsize;
+	
+	/*
+	 * These are read from the MCA POS registers.  
+	 */
+	unsigned int burstmode:2;
+	unsigned int fairness:1; /* 0 = Fair, 1 = Unfair */
+	unsigned int arblevel:4;
+	unsigned int ringspeed:2; /* 0 = 4mb, 1 = 16, 2 = Auto/none */
+	unsigned int cabletype:1; /* 0 = RJ45, 1 = DB9 */
+};
+
+static int madgemc_open(struct net_device *dev);
+static int madgemc_close(struct net_device *dev);
+static int madgemc_chipset_init(struct net_device *dev);
+static void madgemc_read_rom(struct net_device *dev, struct card_info *card);
+static unsigned short madgemc_setnselout_pins(struct net_device *dev);
+static void madgemc_setcabletype(struct net_device *dev, int type);
+
+static int madgemc_mcaproc(char *buf, int slot, void *d);
+
+static void madgemc_setregpage(struct net_device *dev, int page);
+static void madgemc_setsifsel(struct net_device *dev, int val);
+static void madgemc_setint(struct net_device *dev, int val);
+
+static irqreturn_t madgemc_interrupt(int irq, void *dev_id);
+
+/*
+ * These work around paging, however they don't guarentee you're on the
+ * right page.
+ */
+#define SIFREADB(reg) (inb(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
+#define SIFWRITEB(val, reg) (outb(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
+#define SIFREADW(reg) (inw(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
+#define SIFWRITEW(val, reg) (outw(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
+
+/*
+ * Read a byte-length value from the register.
+ */
+static unsigned short madgemc_sifreadb(struct net_device *dev, unsigned short reg)
+{
+	unsigned short ret;
+	if (reg<0x8)	
+		ret = SIFREADB(reg);
+	else {
+		madgemc_setregpage(dev, 1);	
+		ret = SIFREADB(reg);
+		madgemc_setregpage(dev, 0);
+	}
+	return ret;
+}
+
+/*
+ * Write a byte-length value to a register.
+ */
+static void madgemc_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
+{
+	if (reg<0x8)
+		SIFWRITEB(val, reg);
+	else {
+		madgemc_setregpage(dev, 1);
+		SIFWRITEB(val, reg);
+		madgemc_setregpage(dev, 0);
+	}
+	return;
+}
+
+/*
+ * Read a word-length value from a register
+ */
+static unsigned short madgemc_sifreadw(struct net_device *dev, unsigned short reg)
+{
+	unsigned short ret;
+	if (reg<0x8)	
+		ret = SIFREADW(reg);
+	else {
+		madgemc_setregpage(dev, 1);	
+		ret = SIFREADW(reg);
+		madgemc_setregpage(dev, 0);
+	}
+	return ret;
+}
+
+/*
+ * Write a word-length value to a register.
+ */
+static void madgemc_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
+{
+	if (reg<0x8)
+		SIFWRITEW(val, reg);
+	else {
+		madgemc_setregpage(dev, 1);
+		SIFWRITEW(val, reg);
+		madgemc_setregpage(dev, 0);
+	}
+	return;
+}
+
+
+
+static int __devinit madgemc_probe(struct device *device)
+{	
+	static int versionprinted;
+	struct net_device *dev;
+	struct net_local *tp;
+	struct card_info *card;
+	struct mca_device *mdev = to_mca_device(device);
+	int ret = 0, i = 0;
+
+	if (versionprinted++ == 0)
+		printk("%s", version);
+
+	if(mca_device_claimed(mdev))
+		return -EBUSY;
+	mca_device_set_claim(mdev, 1);
+
+	dev = alloc_trdev(sizeof(struct net_local));
+	if (!dev) {
+		printk("madgemc: unable to allocate dev space\n");
+		mca_device_set_claim(mdev, 0);
+		ret = -ENOMEM;
+		goto getout;
+	}
+
+	SET_MODULE_OWNER(dev);
+	dev->dma = 0;
+
+	card = kmalloc(sizeof(struct card_info), GFP_KERNEL);
+	if (card==NULL) {
+		printk("madgemc: unable to allocate card struct\n");
+		ret = -ENOMEM;
+		goto getout1;
+	}
+
+	/*
+	 * Parse configuration information.  This all comes
+	 * directly from the publicly available @002d.ADF.
+	 * Get it from Madge or your local ADF library.
+	 */
+
+	/*
+	 * Base address 
+	 */
+	dev->base_addr = 0x0a20 + 
+		((mdev->pos[2] & MC16_POS2_ADDR2)?0x0400:0) +
+		((mdev->pos[0] & MC16_POS0_ADDR1)?0x1000:0) +
+		((mdev->pos[3] & MC16_POS3_ADDR3)?0x2000:0);
+
+	/*
+	 * Interrupt line
+	 */
+	switch(mdev->pos[0] >> 6) { /* upper two bits */
+		case 0x1: dev->irq = 3; break;
+		case 0x2: dev->irq = 9; break; /* IRQ 2 = IRQ 9 */
+		case 0x3: dev->irq = 10; break;
+		default: dev->irq = 0; break;
+	}
+
+	if (dev->irq == 0) {
+		printk("%s: invalid IRQ\n", dev->name);
+		ret = -EBUSY;
+		goto getout2;
+	}
+
+	if (!request_region(dev->base_addr, MADGEMC_IO_EXTENT, 
+			   "madgemc")) {
+		printk(KERN_INFO "madgemc: unable to setup Smart MC in slot %d because of I/O base conflict at 0x%04lx\n", mdev->slot, dev->base_addr);
+		dev->base_addr += MADGEMC_SIF_OFFSET;
+		ret = -EBUSY;
+		goto getout2;
+	}
+	dev->base_addr += MADGEMC_SIF_OFFSET;
+	
+	/*
+	 * Arbitration Level
+	 */
+	card->arblevel = ((mdev->pos[0] >> 1) & 0x7) + 8;
+
+	/*
+	 * Burst mode and Fairness
+	 */
+	card->burstmode = ((mdev->pos[2] >> 6) & 0x3);
+	card->fairness = ((mdev->pos[2] >> 4) & 0x1);
+
+	/*
+	 * Ring Speed
+	 */
+	if ((mdev->pos[1] >> 2)&0x1)
+		card->ringspeed = 2; /* not selected */
+	else if ((mdev->pos[2] >> 5) & 0x1)
+		card->ringspeed = 1; /* 16Mb */
+	else
+		card->ringspeed = 0; /* 4Mb */
+
+	/* 
+	 * Cable type
+	 */
+	if ((mdev->pos[1] >> 6)&0x1)
+		card->cabletype = 1; /* STP/DB9 */
+	else
+		card->cabletype = 0; /* UTP/RJ-45 */
+
+
+	/* 
+	 * ROM Info. This requires us to actually twiddle
+	 * bits on the card, so we must ensure above that 
+	 * the base address is free of conflict (request_region above).
+	 */
+	madgemc_read_rom(dev, card);
+		
+	if (card->manid != 0x4d) { /* something went wrong */
+		printk(KERN_INFO "%s: Madge MC ROM read failed (unknown manufacturer ID %02x)\n", dev->name, card->manid);
+		goto getout3;
+	}
+		
+	if ((card->cardtype != 0x08) && (card->cardtype != 0x0d)) {
+		printk(KERN_INFO "%s: Madge MC ROM read failed (unknown card ID %02x)\n", dev->name, card->cardtype);
+		ret = -EIO;
+		goto getout3;
+	}
+	       
+	/* All cards except Rev 0 and 1 MC16's have 256kb of RAM */
+	if ((card->cardtype == 0x08) && (card->cardrev <= 0x01))
+		card->ramsize = 128;
+	else
+		card->ramsize = 256;
+
+	printk("%s: %s Rev %d at 0x%04lx IRQ %d\n", 
+	       dev->name, 
+	       (card->cardtype == 0x08)?MADGEMC16_CARDNAME:
+	       MADGEMC32_CARDNAME, card->cardrev, 
+	       dev->base_addr, dev->irq);
+
+	if (card->cardtype == 0x0d)
+		printk("%s:     Warning: MC32 support is experimental and highly untested\n", dev->name);
+	
+	if (card->ringspeed==2) { /* Unknown */
+		printk("%s:     Warning: Ring speed not set in POS -- Please run the reference disk and set it!\n", dev->name);
+		card->ringspeed = 1; /* default to 16mb */
+	}
+		
+	printk("%s:     RAM Size: %dKB\n", dev->name, card->ramsize);
+
+	printk("%s:     Ring Speed: %dMb/sec on %s\n", dev->name, 
+	       (card->ringspeed)?16:4, 
+	       card->cabletype?"STP/DB9":"UTP/RJ-45");
+	printk("%s:     Arbitration Level: %d\n", dev->name, 
+	       card->arblevel);
+
+	printk("%s:     Burst Mode: ", dev->name);
+	switch(card->burstmode) {
+		case 0: printk("Cycle steal"); break;
+		case 1: printk("Limited burst"); break;
+		case 2: printk("Delayed release"); break;
+		case 3: printk("Immediate release"); break;
+	}
+	printk(" (%s)\n", (card->fairness)?"Unfair":"Fair");
+
+
+	/* 
+	 * Enable SIF before we assign the interrupt handler,
+	 * just in case we get spurious interrupts that need
+	 * handling.
+	 */ 
+	outb(0, dev->base_addr + MC_CONTROL_REG0); /* sanity */
+	madgemc_setsifsel(dev, 1);
+	if (request_irq(dev->irq, madgemc_interrupt, IRQF_SHARED,
+		       "madgemc", dev)) {
+		ret = -EBUSY;
+		goto getout3;
+	}
+
+	madgemc_chipset_init(dev); /* enables interrupts! */
+	madgemc_setcabletype(dev, card->cabletype);
+
+	/* Setup MCA structures */
+	mca_device_set_name(mdev, (card->cardtype == 0x08)?MADGEMC16_CARDNAME:MADGEMC32_CARDNAME);
+	mca_set_adapter_procfn(mdev->slot, madgemc_mcaproc, dev);
+
+	printk("%s:     Ring Station Address: ", dev->name);
+	printk("%2.2x", dev->dev_addr[0]);
+	for (i = 1; i < 6; i++)
+		printk(":%2.2x", dev->dev_addr[i]);
+	printk("\n");
+
+	if (tmsdev_init(dev, device)) {
+		printk("%s: unable to get memory for dev->priv.\n", 
+		       dev->name);
+		ret = -ENOMEM;
+		goto getout4;
+	}
+	tp = netdev_priv(dev);
+
+	/* 
+	 * The MC16 is physically a 32bit card.  However, Madge
+	 * insists on calling it 16bit, so I'll assume here that
+	 * they know what they're talking about.  Cut off DMA
+	 * at 16mb.
+	 */
+	tp->setnselout = madgemc_setnselout_pins;
+	tp->sifwriteb = madgemc_sifwriteb;
+	tp->sifreadb = madgemc_sifreadb;
+	tp->sifwritew = madgemc_sifwritew;
+	tp->sifreadw = madgemc_sifreadw;
+	tp->DataRate = (card->ringspeed)?SPEED_16:SPEED_4;
+
+	memcpy(tp->ProductID, "Madge MCA 16/4    ", PROD_ID_SIZE + 1);
+
+	dev->open = madgemc_open;
+	dev->stop = madgemc_close;
+
+	tp->tmspriv = card;
+	dev_set_drvdata(device, dev);
+
+	if (register_netdev(dev) == 0)
+		return 0;
+
+	dev_set_drvdata(device, NULL);
+	ret = -ENOMEM;
+getout4:
+	free_irq(dev->irq, dev);
+getout3:
+	release_region(dev->base_addr-MADGEMC_SIF_OFFSET, 
+		       MADGEMC_IO_EXTENT); 
+getout2:
+	kfree(card);
+getout1:
+	free_netdev(dev);
+getout:
+	mca_device_set_claim(mdev, 0);
+	return ret;
+}
+
+/*
+ * Handle interrupts generated by the card
+ *
+ * The MicroChannel Madge cards need slightly more handling
+ * after an interrupt than other TMS380 cards do.
+ *
+ * First we must make sure it was this card that generated the
+ * interrupt (since interrupt sharing is allowed).  Then,
+ * because we're using level-triggered interrupts (as is
+ * standard on MCA), we must toggle the interrupt line
+ * on the card in order to claim and acknowledge the interrupt.
+ * Once that is done, the interrupt should be handlable in
+ * the normal tms380tr_interrupt() routine.
+ *
+ * There's two ways we can check to see if the interrupt is ours,
+ * both with their own disadvantages...
+ *
+ * 1)  	Read in the SIFSTS register from the TMS controller.  This
+ *	is guarenteed to be accurate, however, there's a fairly
+ *	large performance penalty for doing so: the Madge chips
+ *	must request the register from the Eagle, the Eagle must
+ *	read them from its internal bus, and then take the route
+ *	back out again, for a 16bit read.  
+ *
+ * 2)	Use the MC_CONTROL_REG0_SINTR bit from the Madge ASICs.
+ *	The major disadvantage here is that the accuracy of the
+ *	bit is in question.  However, it cuts out the extra read
+ *	cycles it takes to read the Eagle's SIF, as its only an
+ *	8bit read, and theoretically the Madge bit is directly
+ *	connected to the interrupt latch coming out of the Eagle
+ *	hardware (that statement is not verified).  
+ *
+ * I can't determine which of these methods has the best win.  For now,
+ * we make a compromise.  Use the Madge way for the first interrupt,
+ * which should be the fast-path, and then once we hit the first 
+ * interrupt, keep on trying using the SIF method until we've
+ * exhausted all contiguous interrupts.
+ *
+ */
+static irqreturn_t madgemc_interrupt(int irq, void *dev_id)
+{
+	int pending,reg1;
+	struct net_device *dev;
+
+	if (!dev_id) {
+		printk("madgemc_interrupt: was not passed a dev_id!\n");
+		return IRQ_NONE;
+	}
+
+	dev = (struct net_device *)dev_id;
+
+	/* Make sure its really us. -- the Madge way */
+	pending = inb(dev->base_addr + MC_CONTROL_REG0);
+	if (!(pending & MC_CONTROL_REG0_SINTR))
+		return IRQ_NONE; /* not our interrupt */
+
+	/*
+	 * Since we're level-triggered, we may miss the rising edge
+	 * of the next interrupt while we're off handling this one,
+	 * so keep checking until the SIF verifies that it has nothing
+	 * left for us to do.
+	 */
+	pending = STS_SYSTEM_IRQ;
+	do {
+		if (pending & STS_SYSTEM_IRQ) {
+
+			/* Toggle the interrupt to reset the latch on card */
+			reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
+			outb(reg1 ^ MC_CONTROL_REG1_SINTEN, 
+			     dev->base_addr + MC_CONTROL_REG1);
+			outb(reg1, dev->base_addr + MC_CONTROL_REG1);
+
+			/* Continue handling as normal */
+			tms380tr_interrupt(irq, dev_id);
+
+			pending = SIFREADW(SIFSTS); /* restart - the SIF way */
+
+		} else
+			return IRQ_HANDLED; 
+	} while (1);
+
+	return IRQ_HANDLED; /* not reachable */
+}
+
+/*
+ * Set the card to the prefered ring speed.
+ *
+ * Unlike newer cards, the MC16/32 have their speed selection
+ * circuit connected to the Madge ASICs and not to the TMS380
+ * NSELOUT pins. Set the ASIC bits correctly here, and return 
+ * zero to leave the TMS NSELOUT bits unaffected.
+ *
+ */
+unsigned short madgemc_setnselout_pins(struct net_device *dev)
+{
+	unsigned char reg1;
+	struct net_local *tp = netdev_priv(dev);
+	
+	reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
+
+	if(tp->DataRate == SPEED_16)
+		reg1 |= MC_CONTROL_REG1_SPEED_SEL; /* add for 16mb */
+	else if (reg1 & MC_CONTROL_REG1_SPEED_SEL)
+		reg1 ^= MC_CONTROL_REG1_SPEED_SEL; /* remove for 4mb */
+	outb(reg1, dev->base_addr + MC_CONTROL_REG1);
+
+	return 0; /* no change */
+}
+
+/*
+ * Set the register page.  This equates to the SRSX line
+ * on the TMS380Cx6.
+ *
+ * Register selection is normally done via three contiguous
+ * bits.  However, some boards (such as the MC16/32) use only
+ * two bits, plus a separate bit in the glue chip.  This
+ * sets the SRSX bit (the top bit).  See page 4-17 in the
+ * Yellow Book for which registers are affected.
+ *
+ */
+static void madgemc_setregpage(struct net_device *dev, int page)
+{	
+	static int reg1;
+
+	reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
+	if ((page == 0) && (reg1 & MC_CONTROL_REG1_SRSX)) {
+		outb(reg1 ^ MC_CONTROL_REG1_SRSX, 
+		     dev->base_addr + MC_CONTROL_REG1);
+	}
+	else if (page == 1) {
+		outb(reg1 | MC_CONTROL_REG1_SRSX, 
+		     dev->base_addr + MC_CONTROL_REG1);
+	}
+	reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
+
+	return;
+}
+
+/*
+ * The SIF registers are not mapped into register space by default
+ * Set this to 1 to map them, 0 to map the BIA ROM.
+ *
+ */
+static void madgemc_setsifsel(struct net_device *dev, int val)
+{
+	unsigned int reg0;
+
+	reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
+	if ((val == 0) && (reg0 & MC_CONTROL_REG0_SIFSEL)) {
+		outb(reg0 ^ MC_CONTROL_REG0_SIFSEL, 
+		     dev->base_addr + MC_CONTROL_REG0);
+	} else if (val == 1) {
+		outb(reg0 | MC_CONTROL_REG0_SIFSEL, 
+		     dev->base_addr + MC_CONTROL_REG0);
+	}	
+	reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
+
+	return;
+}
+
+/*
+ * Enable SIF interrupts
+ *
+ * This does not enable interrupts in the SIF, but rather
+ * enables SIF interrupts to be passed onto the host.
+ *
+ */
+static void madgemc_setint(struct net_device *dev, int val)
+{
+	unsigned int reg1;
+
+	reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
+	if ((val == 0) && (reg1 & MC_CONTROL_REG1_SINTEN)) {
+		outb(reg1 ^ MC_CONTROL_REG1_SINTEN, 
+		     dev->base_addr + MC_CONTROL_REG1);
+	} else if (val == 1) {
+		outb(reg1 | MC_CONTROL_REG1_SINTEN, 
+		     dev->base_addr + MC_CONTROL_REG1);
+	}
+
+	return;
+}
+
+/*
+ * Cable type is set via control register 7. Bit zero high
+ * for UTP, low for STP.
+ */
+static void madgemc_setcabletype(struct net_device *dev, int type)
+{
+	outb((type==0)?MC_CONTROL_REG7_CABLEUTP:MC_CONTROL_REG7_CABLESTP,
+	     dev->base_addr + MC_CONTROL_REG7);
+}
+
+/*
+ * Enable the functions of the Madge chipset needed for
+ * full working order. 
+ */
+static int madgemc_chipset_init(struct net_device *dev)
+{
+	outb(0, dev->base_addr + MC_CONTROL_REG1); /* pull SRESET low */
+	tms380tr_wait(100); /* wait for card to reset */
+
+	/* bring back into normal operating mode */
+	outb(MC_CONTROL_REG1_NSRESET, dev->base_addr + MC_CONTROL_REG1);
+
+	/* map SIF registers */
+	madgemc_setsifsel(dev, 1);
+
+	/* enable SIF interrupts */
+	madgemc_setint(dev, 1); 
+
+	return 0;
+}
+
+/*
+ * Disable the board, and put back into power-up state.
+ */
+static void madgemc_chipset_close(struct net_device *dev)
+{
+	/* disable interrupts */
+	madgemc_setint(dev, 0);
+	/* unmap SIF registers */
+	madgemc_setsifsel(dev, 0);
+
+	return;
+}
+
+/*
+ * Read the card type (MC16 or MC32) from the card.
+ *
+ * The configuration registers are stored in two separate
+ * pages.  Pages are flipped by clearing bit 3 of CONTROL_REG0 (PAGE)
+ * for page zero, or setting bit 3 for page one.
+ *
+ * Page zero contains the following data:
+ *	Byte 0: Manufacturer ID (0x4D -- ASCII "M")
+ *	Byte 1: Card type:
+ *			0x08 for MC16
+ *			0x0D for MC32
+ *	Byte 2: Card revision
+ *	Byte 3: Mirror of POS config register 0
+ *	Byte 4: Mirror of POS 1
+ *	Byte 5: Mirror of POS 2
+ *
+ * Page one contains the following data:
+ *	Byte 0: Unused
+ *	Byte 1-6: BIA, MSB to LSB.
+ *
+ * Note that to read the BIA, we must unmap the SIF registers
+ * by clearing bit 2 of CONTROL_REG0 (SIFSEL), as the data
+ * will reside in the same logical location.  For this reason,
+ * _never_ read the BIA while the Eagle processor is running!
+ * The SIF will be completely inaccessible until the BIA operation
+ * is complete.
+ *
+ */
+static void madgemc_read_rom(struct net_device *dev, struct card_info *card)
+{
+	unsigned long ioaddr;
+	unsigned char reg0, reg1, tmpreg0, i;
+
+	ioaddr = dev->base_addr;
+
+	reg0 = inb(ioaddr + MC_CONTROL_REG0);
+	reg1 = inb(ioaddr + MC_CONTROL_REG1);
+
+	/* Switch to page zero and unmap SIF */
+	tmpreg0 = reg0 & ~(MC_CONTROL_REG0_PAGE + MC_CONTROL_REG0_SIFSEL);
+	outb(tmpreg0, ioaddr + MC_CONTROL_REG0);
+	
+	card->manid = inb(ioaddr + MC_ROM_MANUFACTURERID);
+	card->cardtype = inb(ioaddr + MC_ROM_ADAPTERID);
+	card->cardrev = inb(ioaddr + MC_ROM_REVISION);
+
+	/* Switch to rom page one */
+	outb(tmpreg0 | MC_CONTROL_REG0_PAGE, ioaddr + MC_CONTROL_REG0);
+
+	/* Read BIA */
+	dev->addr_len = 6;
+	for (i = 0; i < 6; i++)
+		dev->dev_addr[i] = inb(ioaddr + MC_ROM_BIA_START + i);
+	
+	/* Restore original register values */
+	outb(reg0, ioaddr + MC_CONTROL_REG0);
+	outb(reg1, ioaddr + MC_CONTROL_REG1);
+	
+	return;
+}
+
+static int madgemc_open(struct net_device *dev)
+{  
+	/*
+	 * Go ahead and reinitialize the chipset again, just to 
+	 * make sure we didn't get left in a bad state.
+	 */
+	madgemc_chipset_init(dev);
+	tms380tr_open(dev);
+	return 0;
+}
+
+static int madgemc_close(struct net_device *dev)
+{
+	tms380tr_close(dev);
+	madgemc_chipset_close(dev);
+	return 0;
+}
+
+/*
+ * Give some details available from /proc/mca/slotX
+ */
+static int madgemc_mcaproc(char *buf, int slot, void *d) 
+{	
+	struct net_device *dev = (struct net_device *)d;
+	struct net_local *tp = dev->priv;
+	struct card_info *curcard = tp->tmspriv;
+	int len = 0;
+	
+	len += sprintf(buf+len, "-------\n");
+	if (curcard) {
+		struct net_local *tp = netdev_priv(dev);
+		int i;
+		
+		len += sprintf(buf+len, "Card Revision: %d\n", curcard->cardrev);
+		len += sprintf(buf+len, "RAM Size: %dkb\n", curcard->ramsize);
+		len += sprintf(buf+len, "Cable type: %s\n", (curcard->cabletype)?"STP/DB9":"UTP/RJ-45");
+		len += sprintf(buf+len, "Configured ring speed: %dMb/sec\n", (curcard->ringspeed)?16:4);
+		len += sprintf(buf+len, "Running ring speed: %dMb/sec\n", (tp->DataRate==SPEED_16)?16:4);
+		len += sprintf(buf+len, "Device: %s\n", dev->name);
+		len += sprintf(buf+len, "IO Port: 0x%04lx\n", dev->base_addr);
+		len += sprintf(buf+len, "IRQ: %d\n", dev->irq);
+		len += sprintf(buf+len, "Arbitration Level: %d\n", curcard->arblevel);
+		len += sprintf(buf+len, "Burst Mode: ");
+		switch(curcard->burstmode) {
+		case 0: len += sprintf(buf+len, "Cycle steal"); break;
+		case 1: len += sprintf(buf+len, "Limited burst"); break;
+		case 2: len += sprintf(buf+len, "Delayed release"); break;
+		case 3: len += sprintf(buf+len, "Immediate release"); break;
+		}
+		len += sprintf(buf+len, " (%s)\n", (curcard->fairness)?"Unfair":"Fair");
+		
+		len += sprintf(buf+len, "Ring Station Address: ");
+		len += sprintf(buf+len, "%2.2x", dev->dev_addr[0]);
+		for (i = 1; i < 6; i++)
+			len += sprintf(buf+len, " %2.2x", dev->dev_addr[i]);
+		len += sprintf(buf+len, "\n");
+	} else 
+		len += sprintf(buf+len, "Card not configured\n");
+
+	return len;
+}
+
+static int __devexit madgemc_remove(struct device *device)
+{
+	struct net_device *dev = dev_get_drvdata(device);
+	struct net_local *tp;
+        struct card_info *card;
+
+	BUG_ON(!dev);
+
+	tp = dev->priv;
+	card = tp->tmspriv;
+	kfree(card);
+	tp->tmspriv = NULL;
+
+	unregister_netdev(dev);
+	release_region(dev->base_addr-MADGEMC_SIF_OFFSET, MADGEMC_IO_EXTENT);
+	free_irq(dev->irq, dev);
+	tmsdev_term(dev);
+	free_netdev(dev);
+	dev_set_drvdata(device, NULL);
+
+	return 0;
+}
+
+static short madgemc_adapter_ids[] __initdata = {
+	0x002d,
+	0x0000
+};
+
+static struct mca_driver madgemc_driver = {
+	.id_table = madgemc_adapter_ids,
+	.driver = {
+		.name = "madgemc",
+		.bus = &mca_bus_type,
+		.probe = madgemc_probe,
+		.remove = __devexit_p(madgemc_remove),
+	},
+};
+
+static int __init madgemc_init (void)
+{
+	return mca_register_driver (&madgemc_driver);
+}
+
+static void __exit madgemc_exit (void)
+{
+	mca_unregister_driver (&madgemc_driver);
+}
+
+module_init(madgemc_init);
+module_exit(madgemc_exit);
+
+MODULE_LICENSE("GPL");
+

drivers/net/tokenring/madgemc.h

@@ -0,0 +1,70 @@
+/* 
+ * madgemc.h: Header for the madgemc tms380tr module
+ *
+ * Authors:
+ * - Adam Fritzler <mid@auk.cx>
+ */
+
+#ifndef __LINUX_MADGEMC_H
+#define __LINUX_MADGEMC_H
+
+#ifdef __KERNEL__
+
+#define MADGEMC16_CARDNAME "Madge Smart 16/4 MC16 Ringnode"
+#define MADGEMC32_CARDNAME "Madge Smart 16/4 MC32 Ringnode"
+
+/* 
+ * Bit definitions for the POS config registers
+ */
+#define MC16_POS0_ADDR1 0x20
+#define MC16_POS2_ADDR2 0x04
+#define MC16_POS3_ADDR3 0x20
+
+#define MC_CONTROL_REG0		((long)-8) /* 0x00 */
+#define MC_CONTROL_REG1		((long)-7) /* 0x01 */
+#define MC_ADAPTER_POS_REG0	((long)-6) /* 0x02 */
+#define MC_ADAPTER_POS_REG1	((long)-5) /* 0x03 */
+#define MC_ADAPTER_POS_REG2	((long)-4) /* 0x04 */
+#define MC_ADAPTER_REG5_UNUSED	((long)-3) /* 0x05 */
+#define MC_ADAPTER_REG6_UNUSED	((long)-2) /* 0x06 */
+#define MC_CONTROL_REG7		((long)-1) /* 0x07 */
+
+#define MC_CONTROL_REG0_UNKNOWN1	0x01
+#define MC_CONTROL_REG0_UNKNOWN2	0x02
+#define MC_CONTROL_REG0_SIFSEL		0x04
+#define MC_CONTROL_REG0_PAGE		0x08
+#define MC_CONTROL_REG0_TESTINTERRUPT	0x10
+#define MC_CONTROL_REG0_UNKNOWN20	0x20
+#define MC_CONTROL_REG0_SINTR		0x40
+#define MC_CONTROL_REG0_UNKNOWN80	0x80
+
+#define MC_CONTROL_REG1_SINTEN		0x01
+#define MC_CONTROL_REG1_BITOFDEATH	0x02
+#define MC_CONTROL_REG1_NSRESET		0x04
+#define MC_CONTROL_REG1_UNKNOWN8	0x08
+#define MC_CONTROL_REG1_UNKNOWN10	0x10
+#define MC_CONTROL_REG1_UNKNOWN20	0x20
+#define MC_CONTROL_REG1_SRSX		0x40
+#define MC_CONTROL_REG1_SPEED_SEL	0x80
+
+#define MC_CONTROL_REG7_CABLESTP	0x00
+#define MC_CONTROL_REG7_CABLEUTP	0x01
+
+/*
+ * ROM Page Zero
+ */
+#define MC_ROM_MANUFACTURERID		0x00
+#define MC_ROM_ADAPTERID		0x01
+#define MC_ROM_REVISION			0x02
+#define MC_ROM_CONFIG0			0x03
+#define MC_ROM_CONFIG1			0x04
+#define MC_ROM_CONFIG2			0x05
+
+/*
+ * ROM Page One
+ */
+#define MC_ROM_UNUSED_BYTE		0x00
+#define MC_ROM_BIA_START		0x01
+
+#endif /* __KERNEL__ */
+#endif /* __LINUX_MADGEMC_H */

drivers/net/tokenring/olympic.h

@@ -0,0 +1,322 @@
+/*
+ *  olympic.h (c) 1999 Peter De Schrijver All Rights Reserved
+ *                1999,2000 Mike Phillips (mikep@linuxtr.net)
+ *
+ *  Linux driver for IBM PCI tokenring cards based on the olympic and the PIT/PHY chipset.
+ *
+ *  Base Driver Skeleton:
+ *      Written 1993-94 by Donald Becker.
+ *
+ *      Copyright 1993 United States Government as represented by the
+ *      Director, National Security Agency.
+ *
+ *  This software may be used and distributed according to the terms
+ *  of the GNU General Public License, incorporated herein by reference.
+ */
+
+#define CID 0x4e
+
+#define BCTL 0x70
+#define BCTL_SOFTRESET (1<<15)
+#define BCTL_MIMREB (1<<6)
+#define BCTL_MODE_INDICATOR (1<<5)
+
+#define GPR 0x4a
+#define GPR_OPTI_BF (1<<6)
+#define GPR_NEPTUNE_BF (1<<4) 
+#define GPR_AUTOSENSE (1<<2)
+#define GPR_16MBPS (1<<3) 
+
+#define PAG 0x85
+#define LBC 0x8e
+
+#define LISR 0x10
+#define LISR_SUM 0x14
+#define LISR_RWM 0x18
+
+#define LISR_LIE (1<<15)
+#define LISR_SLIM (1<<13)
+#define LISR_SLI (1<<12)
+#define LISR_PCMSRMASK (1<<11)
+#define LISR_PCMSRINT (1<<10)
+#define LISR_WOLMASK (1<<9)
+#define LISR_WOL (1<<8)
+#define LISR_SRB_CMD (1<<5)
+#define LISR_ASB_REPLY (1<<4)
+#define LISR_ASB_FREE_REQ (1<<2)
+#define LISR_ARB_FREE (1<<1)
+#define LISR_TRB_FRAME (1<<0)
+
+#define SISR 0x20
+#define SISR_SUM 0x24
+#define SISR_RWM 0x28
+#define SISR_RR 0x2C
+#define SISR_RESMASK 0x30
+#define SISR_MASK 0x54
+#define SISR_MASK_SUM 0x58
+#define SISR_MASK_RWM 0x5C
+
+#define SISR_TX2_IDLE (1<<31)
+#define SISR_TX2_HALT (1<<29)
+#define SISR_TX2_EOF (1<<28)
+#define SISR_TX1_IDLE (1<<27)
+#define SISR_TX1_HALT (1<<25)
+#define SISR_TX1_EOF (1<<24)
+#define SISR_TIMEOUT (1<<23)
+#define SISR_RX_NOBUF (1<<22)
+#define SISR_RX_STATUS (1<<21)
+#define SISR_RX_HALT (1<<18)
+#define SISR_RX_EOF_EARLY (1<<16)
+#define SISR_MI (1<<15)
+#define SISR_PI (1<<13)
+#define SISR_ERR (1<<9)
+#define SISR_ADAPTER_CHECK (1<<6)
+#define SISR_SRB_REPLY (1<<5)
+#define SISR_ASB_FREE (1<<4)
+#define SISR_ARB_CMD (1<<3)
+#define SISR_TRB_REPLY (1<<2)
+
+#define EISR 0x34
+#define EISR_RWM 0x38
+#define EISR_MASK 0x3c
+#define EISR_MASK_OPTIONS 0x001FFF7F
+
+#define LAPA 0x60
+#define LAPWWO 0x64
+#define LAPWWC 0x68
+#define LAPCTL 0x6C
+#define LAIPD 0x78
+#define LAIPDDINC 0x7C
+
+#define TIMER 0x50
+
+#define CLKCTL 0x74
+#define CLKCTL_PAUSE (1<<15) 
+
+#define PM_CON 0x4
+
+#define BMCTL_SUM 0x40
+#define BMCTL_RWM 0x44
+#define BMCTL_TX2_DIS (1<<30) 
+#define BMCTL_TX1_DIS (1<<26) 
+#define BMCTL_RX_DIS (1<<22) 
+
+#define BMASR 0xcc
+
+#define RXDESCQ 0x90
+#define RXDESCQCNT 0x94
+#define RXCDA 0x98
+#define RXENQ 0x9C
+#define RXSTATQ 0xA0
+#define RXSTATQCNT 0xA4
+#define RXCSA 0xA8
+#define RXCLEN 0xAC
+#define RXHLEN 0xAE
+
+#define TXDESCQ_1 0xb0
+#define TXDESCQ_2 0xd0
+#define TXDESCQCNT_1 0xb4
+#define TXDESCQCNT_2 0xd4
+#define TXCDA_1 0xb8
+#define TXCDA_2 0xd8
+#define TXENQ_1 0xbc
+#define TXENQ_2 0xdc
+#define TXSTATQ_1 0xc0
+#define TXSTATQ_2 0xe0
+#define TXSTATQCNT_1 0xc4
+#define TXSTATQCNT_2 0xe4
+#define TXCSA_1 0xc8
+#define TXCSA_2 0xe8
+/* Cardbus */
+#define FERMASK 0xf4
+#define FERMASK_INT_BIT (1<<15)
+
+#define OLYMPIC_IO_SPACE 256
+
+#define SRB_COMMAND_SIZE 50
+
+#define OLYMPIC_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
+
+/* Defines for LAN STATUS CHANGE reports */
+#define LSC_SIG_LOSS 0x8000
+#define LSC_HARD_ERR 0x4000
+#define LSC_SOFT_ERR 0x2000
+#define LSC_TRAN_BCN 0x1000
+#define LSC_LWF      0x0800
+#define LSC_ARW      0x0400
+#define LSC_FPE      0x0200
+#define LSC_RR       0x0100
+#define LSC_CO       0x0080
+#define LSC_SS       0x0040
+#define LSC_RING_REC 0x0020
+#define LSC_SR_CO    0x0010
+#define LSC_FDX_MODE 0x0004
+
+/* Defines for OPEN ADAPTER command */
+
+#define OPEN_ADAPTER_EXT_WRAP (1<<15)
+#define OPEN_ADAPTER_DIS_HARDEE (1<<14)
+#define OPEN_ADAPTER_DIS_SOFTERR (1<<13)
+#define OPEN_ADAPTER_PASS_ADC_MAC (1<<12)
+#define OPEN_ADAPTER_PASS_ATT_MAC (1<<11)
+#define OPEN_ADAPTER_ENABLE_EC (1<<10)
+#define OPEN_ADAPTER_CONTENDER (1<<8)
+#define OPEN_ADAPTER_PASS_BEACON (1<<7)
+#define OPEN_ADAPTER_ENABLE_FDX (1<<6)
+#define OPEN_ADAPTER_ENABLE_RPL (1<<5)
+#define OPEN_ADAPTER_INHIBIT_ETR (1<<4)
+#define OPEN_ADAPTER_INTERNAL_WRAP (1<<3)
+#define OPEN_ADAPTER_USE_OPTS2 (1<<0)
+
+#define OPEN_ADAPTER_2_ENABLE_ONNOW (1<<15)
+
+/* Defines for SRB Commands */
+
+#define SRB_ACCESS_REGISTER 0x1f
+#define SRB_CLOSE_ADAPTER 0x04
+#define SRB_CONFIGURE_BRIDGE 0x0c
+#define SRB_CONFIGURE_WAKEUP_EVENT 0x1a
+#define SRB_MODIFY_BRIDGE_PARMS 0x15
+#define SRB_MODIFY_OPEN_OPTIONS 0x01
+#define SRB_MODIFY_RECEIVE_OPTIONS 0x17
+#define SRB_NO_OPERATION 0x00
+#define SRB_OPEN_ADAPTER 0x03
+#define SRB_READ_LOG 0x08
+#define SRB_READ_SR_COUNTERS 0x16
+#define SRB_RESET_GROUP_ADDRESS 0x02
+#define SRB_SAVE_CONFIGURATION 0x1b
+#define SRB_SET_BRIDGE_PARMS 0x09
+#define SRB_SET_BRIDGE_TARGETS 0x10
+#define SRB_SET_FUNC_ADDRESS 0x07
+#define SRB_SET_GROUP_ADDRESS 0x06
+#define SRB_SET_GROUP_ADDR_OPTIONS 0x11
+#define SRB_UPDATE_WAKEUP_PATTERN 0x19
+
+/* Clear return code */
+
+#define OLYMPIC_CLEAR_RET_CODE 0xfe 
+
+/* ARB Commands */
+#define ARB_RECEIVE_DATA 0x81
+#define ARB_LAN_CHANGE_STATUS 0x84
+/* ASB Response commands */
+
+#define ASB_RECEIVE_DATA 0x81
+
+
+/* Olympic defaults for buffers */
+ 
+#define OLYMPIC_RX_RING_SIZE 16 /* should be a power of 2 */
+#define OLYMPIC_TX_RING_SIZE 8 /* should be a power of 2 */
+
+#define PKT_BUF_SZ 4096 /* Default packet size */
+
+/* Olympic data structures */
+
+/* xxxx These structures are all little endian in hardware. */
+
+struct olympic_tx_desc {
+	u32 buffer;
+	u32 status_length;
+};
+
+struct olympic_tx_status {
+	u32 status;
+};
+
+struct olympic_rx_desc {
+	u32 buffer;
+	u32 res_length; 
+};
+
+struct olympic_rx_status {
+	u32 fragmentcnt_framelen;
+	u32 status_buffercnt;
+};
+/* xxxx END These structures are all little endian in hardware. */
+/* xxxx There may be more, but I'm pretty sure about these */
+
+struct mac_receive_buffer {
+	u16 next ; 
+	u8 padding ; 
+	u8 frame_status ;
+	u16 buffer_length ; 
+	u8 frame_data ; 
+};
+
+struct olympic_private {
+	
+	u16 srb;      /* be16 */
+	u16 trb;      /* be16 */
+	u16 arb;      /* be16 */
+	u16 asb;      /* be16 */
+
+	u8 __iomem *olympic_mmio;
+	u8 __iomem *olympic_lap;
+	struct pci_dev *pdev ; 
+	char *olympic_card_name ; 
+
+	spinlock_t olympic_lock ; 
+
+	volatile int srb_queued;    /* True if an SRB is still posted */	
+	wait_queue_head_t srb_wait;
+
+	volatile int asb_queued;    /* True if an ASB is posted */
+
+	volatile int trb_queued;   /* True if a TRB is posted */
+	wait_queue_head_t trb_wait ; 
+
+	/* These must be on a 4 byte boundary. */
+	struct olympic_rx_desc olympic_rx_ring[OLYMPIC_RX_RING_SIZE];
+	struct olympic_tx_desc olympic_tx_ring[OLYMPIC_TX_RING_SIZE];
+	struct olympic_rx_status olympic_rx_status_ring[OLYMPIC_RX_RING_SIZE];	
+	struct olympic_tx_status olympic_tx_status_ring[OLYMPIC_TX_RING_SIZE];	
+
+	struct sk_buff *tx_ring_skb[OLYMPIC_TX_RING_SIZE], *rx_ring_skb[OLYMPIC_RX_RING_SIZE];	
+	int tx_ring_free, tx_ring_last_status, rx_ring_last_received,rx_status_last_received, free_tx_ring_entries;
+
+	struct net_device_stats olympic_stats ;
+	u16 olympic_lan_status ;
+	u8 olympic_ring_speed ;
+	u16 pkt_buf_sz ; 
+	u8 olympic_receive_options, olympic_copy_all_options,olympic_message_level, olympic_network_monitor;  
+	u16 olympic_addr_table_addr, olympic_parms_addr ; 
+	u8 olympic_laa[6] ; 
+	u32 rx_ring_dma_addr;
+	u32 rx_status_ring_dma_addr;
+	u32 tx_ring_dma_addr;
+	u32 tx_status_ring_dma_addr;
+};
+
+struct olympic_adapter_addr_table {
+
+	u8 node_addr[6] ; 
+	u8 reserved[4] ; 
+	u8 func_addr[4] ; 
+} ; 
+
+struct olympic_parameters_table { 
+	
+	u8  phys_addr[4] ; 
+	u8  up_node_addr[6] ; 
+	u8  up_phys_addr[4] ; 
+	u8  poll_addr[6] ; 
+	u16 reserved ; 
+	u16 acc_priority ; 
+	u16 auth_source_class ; 
+	u16 att_code ; 
+	u8  source_addr[6] ; 
+	u16 beacon_type ; 
+	u16 major_vector ; 
+	u16 lan_status ; 
+	u16 soft_error_time ; 
+ 	u16 reserved1 ; 
+	u16 local_ring ; 
+	u16 mon_error ; 
+	u16 beacon_transmit ; 
+	u16 beacon_receive ; 
+	u16 frame_correl ; 
+	u8  beacon_naun[6] ; 
+	u32 reserved2 ; 
+	u8  beacon_phys[4] ; 	
+}; 

drivers/net/tokenring/proteon.c

@@ -0,0 +1,422 @@
+/*
+ *  proteon.c: A network driver for Proteon ISA token ring cards.
+ *
+ *  Based on tmspci written 1999 by Adam Fritzler
+ *  
+ *  Written 2003 by Jochen Friedrich
+ *
+ *  This software may be used and distributed according to the terms
+ *  of the GNU General Public License, incorporated herein by reference.
+ *
+ *  This driver module supports the following cards:
+ *	- Proteon 1392, 1392+
+ *
+ *  Maintainer(s):
+ *    AF        Adam Fritzler           mid@auk.cx
+ *    JF	Jochen Friedrich	jochen@scram.de
+ *
+ *  Modification History:
+ *	02-Jan-03	JF	Created
+ *
+ */
+static const char version[] = "proteon.c: v1.00 02/01/2003 by Jochen Friedrich\n";
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/trdevice.h>
+#include <linux/platform_device.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pci.h>
+#include <asm/dma.h>
+
+#include "tms380tr.h"
+
+#define PROTEON_IO_EXTENT 32
+
+/* A zero-terminated list of I/O addresses to be probed. */
+static unsigned int portlist[] __initdata = {
+	0x0A20, 0x0E20, 0x1A20, 0x1E20, 0x2A20, 0x2E20, 0x3A20, 0x3E20,// Prot.
+	0x4A20, 0x4E20, 0x5A20, 0x5E20, 0x6A20, 0x6E20, 0x7A20, 0x7E20,// Prot.
+	0x8A20, 0x8E20, 0x9A20, 0x9E20, 0xAA20, 0xAE20, 0xBA20, 0xBE20,// Prot.
+	0xCA20, 0xCE20, 0xDA20, 0xDE20, 0xEA20, 0xEE20, 0xFA20, 0xFE20,// Prot.
+	0
+};
+
+/* A zero-terminated list of IRQs to be probed. */
+static unsigned short irqlist[] = {
+	7, 6, 5, 4, 3, 12, 11, 10, 9,
+	0
+};
+
+/* A zero-terminated list of DMAs to be probed. */
+static int dmalist[] __initdata = {
+	5, 6, 7,
+	0
+};
+
+static char cardname[] = "Proteon 1392\0";
+static u64 dma_mask = ISA_MAX_ADDRESS;
+static int proteon_open(struct net_device *dev);
+static void proteon_read_eeprom(struct net_device *dev);
+static unsigned short proteon_setnselout_pins(struct net_device *dev);
+
+static unsigned short proteon_sifreadb(struct net_device *dev, unsigned short reg)
+{
+	return inb(dev->base_addr + reg);
+}
+
+static unsigned short proteon_sifreadw(struct net_device *dev, unsigned short reg)
+{
+	return inw(dev->base_addr + reg);
+}
+
+static void proteon_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
+{
+	outb(val, dev->base_addr + reg);
+}
+
+static void proteon_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
+{
+	outw(val, dev->base_addr + reg);
+}
+
+static int __init proteon_probe1(struct net_device *dev, int ioaddr)
+{
+	unsigned char chk1, chk2;
+	int i;
+
+	if (!request_region(ioaddr, PROTEON_IO_EXTENT, cardname))
+		return -ENODEV;
+		
+
+	chk1 = inb(ioaddr + 0x1f);      /* Get Proteon ID reg 1 */
+	if (chk1 != 0x1f) 
+		goto nodev;
+
+	chk1 = inb(ioaddr + 0x1e) & 0x07;       /* Get Proteon ID reg 0 */
+	for (i=0; i<16; i++) {
+		chk2 = inb(ioaddr + 0x1e) & 0x07;
+		if (((chk1 + 1) & 0x07) != chk2)
+			goto nodev;
+		chk1 = chk2;
+	}
+
+	dev->base_addr = ioaddr;
+	return (0);
+nodev:
+	release_region(ioaddr, PROTEON_IO_EXTENT); 
+	return -ENODEV;
+}
+
+static int __init setup_card(struct net_device *dev, struct device *pdev)
+{
+	struct net_local *tp;
+        static int versionprinted;
+	const unsigned *port;
+	int j,err = 0;
+
+	if (!dev)
+		return -ENOMEM;
+
+	SET_MODULE_OWNER(dev);
+	if (dev->base_addr)	/* probe specific location */
+		err = proteon_probe1(dev, dev->base_addr);
+	else {
+		for (port = portlist; *port; port++) {
+			err = proteon_probe1(dev, *port);
+			if (!err)
+				break;
+		}
+	}
+	if (err)
+		goto out5;
+
+	/* At this point we have found a valid card. */
+
+	if (versionprinted++ == 0)
+		printk(KERN_DEBUG "%s", version);
+
+	err = -EIO;
+	pdev->dma_mask = &dma_mask;
+	if (tmsdev_init(dev, pdev))
+		goto out4;
+
+	dev->base_addr &= ~3; 
+		
+	proteon_read_eeprom(dev);
+
+	printk(KERN_DEBUG "proteon.c:    Ring Station Address: ");
+	printk("%2.2x", dev->dev_addr[0]);
+	for (j = 1; j < 6; j++)
+		printk(":%2.2x", dev->dev_addr[j]);
+	printk("\n");
+		
+	tp = netdev_priv(dev);
+	tp->setnselout = proteon_setnselout_pins;
+		
+	tp->sifreadb = proteon_sifreadb;
+	tp->sifreadw = proteon_sifreadw;
+	tp->sifwriteb = proteon_sifwriteb;
+	tp->sifwritew = proteon_sifwritew;
+	
+	memcpy(tp->ProductID, cardname, PROD_ID_SIZE + 1);
+
+	tp->tmspriv = NULL;
+
+	dev->open = proteon_open;
+	dev->stop = tms380tr_close;
+
+	if (dev->irq == 0)
+	{
+		for(j = 0; irqlist[j] != 0; j++)
+		{
+			dev->irq = irqlist[j];
+			if (!request_irq(dev->irq, tms380tr_interrupt, 0, 
+				cardname, dev))
+				break;
+                }
+		
+                if(irqlist[j] == 0)
+                {
+                        printk(KERN_INFO "proteon.c: AutoSelect no IRQ available\n");
+			goto out3;
+		}
+	}
+	else
+	{
+		for(j = 0; irqlist[j] != 0; j++)
+			if (irqlist[j] == dev->irq)
+				break;
+		if (irqlist[j] == 0)
+		{
+			printk(KERN_INFO "proteon.c: Illegal IRQ %d specified\n",
+				dev->irq);
+			goto out3;
+		}
+		if (request_irq(dev->irq, tms380tr_interrupt, 0, 
+			cardname, dev))
+		{
+                        printk(KERN_INFO "proteon.c: Selected IRQ %d not available\n",
+				dev->irq);
+			goto out3;
+		}
+	}
+
+	if (dev->dma == 0)
+	{
+		for(j = 0; dmalist[j] != 0; j++)
+		{
+			dev->dma = dmalist[j];
+                        if (!request_dma(dev->dma, cardname))
+				break;
+		}
+
+		if(dmalist[j] == 0)
+		{
+			printk(KERN_INFO "proteon.c: AutoSelect no DMA available\n");
+			goto out2;
+		}
+	}
+	else
+	{
+		for(j = 0; dmalist[j] != 0; j++)
+			if (dmalist[j] == dev->dma)
+				break;
+		if (dmalist[j] == 0)
+		{
+                        printk(KERN_INFO "proteon.c: Illegal DMA %d specified\n",
+				dev->dma);
+			goto out2;
+		}
+		if (request_dma(dev->dma, cardname))
+		{
+                        printk(KERN_INFO "proteon.c: Selected DMA %d not available\n",
+				dev->dma);
+			goto out2;
+		}
+	}
+
+	err = register_netdev(dev);
+	if (err)
+		goto out;
+
+	printk(KERN_DEBUG "%s:    IO: %#4lx  IRQ: %d  DMA: %d\n",
+	       dev->name, dev->base_addr, dev->irq, dev->dma);
+
+	return 0;
+out:
+	free_dma(dev->dma);
+out2:
+	free_irq(dev->irq, dev);
+out3:
+	tmsdev_term(dev);
+out4:
+	release_region(dev->base_addr, PROTEON_IO_EXTENT);
+out5:
+	return err;
+}
+
+/*
+ * Reads MAC address from adapter RAM, which should've read it from
+ * the onboard ROM.  
+ *
+ * Calling this on a board that does not support it can be a very
+ * dangerous thing.  The Madge board, for instance, will lock your
+ * machine hard when this is called.  Luckily, its supported in a
+ * separate driver.  --ASF
+ */
+static void proteon_read_eeprom(struct net_device *dev)
+{
+	int i;
+	
+	/* Address: 0000:0000 */
+	proteon_sifwritew(dev, 0, SIFADX);
+	proteon_sifwritew(dev, 0, SIFADR);	
+	
+	/* Read six byte MAC address data */
+	dev->addr_len = 6;
+	for(i = 0; i < 6; i++)
+		dev->dev_addr[i] = proteon_sifreadw(dev, SIFINC) >> 8;
+}
+
+unsigned short proteon_setnselout_pins(struct net_device *dev)
+{
+	return 0;
+}
+
+static int proteon_open(struct net_device *dev)
+{  
+	struct net_local *tp = netdev_priv(dev);
+	unsigned short val = 0;
+	int i;
+
+	/* Proteon reset sequence */
+	outb(0, dev->base_addr + 0x11);
+	mdelay(20);
+	outb(0x04, dev->base_addr + 0x11);
+	mdelay(20);
+	outb(0, dev->base_addr + 0x11);
+	mdelay(100);
+
+	/* set control/status reg */
+	val = inb(dev->base_addr + 0x11);
+	val |= 0x78;
+	val &= 0xf9;
+	if(tp->DataRate == SPEED_4)
+		val |= 0x20;
+	else
+		val &= ~0x20;
+
+	outb(val, dev->base_addr + 0x11);
+	outb(0xff, dev->base_addr + 0x12);
+	for(i = 0; irqlist[i] != 0; i++)
+	{
+		if(irqlist[i] == dev->irq)
+			break;
+	}
+	val = i;
+	i = (7 - dev->dma) << 4;
+	val |= i;
+	outb(val, dev->base_addr + 0x13);
+
+	return tms380tr_open(dev);
+}
+
+#define ISATR_MAX_ADAPTERS 3
+
+static int io[ISATR_MAX_ADAPTERS];
+static int irq[ISATR_MAX_ADAPTERS];
+static int dma[ISATR_MAX_ADAPTERS];
+
+MODULE_LICENSE("GPL");
+
+module_param_array(io, int, NULL, 0);
+module_param_array(irq, int, NULL, 0);
+module_param_array(dma, int, NULL, 0);
+
+static struct platform_device *proteon_dev[ISATR_MAX_ADAPTERS];
+
+static struct platform_driver proteon_driver = {
+	.driver		= {
+		.name	= "proteon",
+	},
+};
+
+static int __init proteon_init(void)
+{
+	struct net_device *dev;
+	struct platform_device *pdev;
+	int i, num = 0, err = 0;
+
+	err = platform_driver_register(&proteon_driver);
+	if (err)
+		return err;
+
+	for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
+		dev = alloc_trdev(sizeof(struct net_local));
+		if (!dev)
+			continue;
+
+		dev->base_addr = io[i];
+		dev->irq = irq[i];
+		dev->dma = dma[i];
+		pdev = platform_device_register_simple("proteon",
+			i, NULL, 0);
+		if (IS_ERR(pdev)) {
+			free_netdev(dev);
+			continue;
+		}
+		err = setup_card(dev, &pdev->dev);
+		if (!err) {
+			proteon_dev[i] = pdev;
+			platform_set_drvdata(pdev, dev);
+			++num;
+		} else {
+			platform_device_unregister(pdev);
+			free_netdev(dev);
+		}
+	}
+
+	printk(KERN_NOTICE "proteon.c: %d cards found.\n", num);
+	/* Probe for cards. */
+	if (num == 0) {
+		printk(KERN_NOTICE "proteon.c: No cards found.\n");
+		platform_driver_unregister(&proteon_driver);
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static void __exit proteon_cleanup(void)
+{
+	struct net_device *dev;
+	int i;
+
+	for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
+		struct platform_device *pdev = proteon_dev[i];
+		
+		if (!pdev)
+			continue;
+		dev = platform_get_drvdata(pdev);
+		unregister_netdev(dev);
+		release_region(dev->base_addr, PROTEON_IO_EXTENT);
+		free_irq(dev->irq, dev);
+		free_dma(dev->dma);
+		tmsdev_term(dev);
+		free_netdev(dev);
+		platform_set_drvdata(pdev, NULL);
+		platform_device_unregister(pdev);
+	}
+	platform_driver_unregister(&proteon_driver);
+}
+
+module_init(proteon_init);
+module_exit(proteon_cleanup);

drivers/net/tokenring/skisa.c

@@ -0,0 +1,432 @@
+/*
+ *  skisa.c: A network driver for SK-NET TMS380-based ISA token ring cards.
+ *
+ *  Based on tmspci written 1999 by Adam Fritzler
+ *  
+ *  Written 2000 by Jochen Friedrich
+ *  Dedicated to my girlfriend Steffi Bopp
+ *
+ *  This software may be used and distributed according to the terms
+ *  of the GNU General Public License, incorporated herein by reference.
+ *
+ *  This driver module supports the following cards:
+ *	- SysKonnect TR4/16(+) ISA	(SK-4190)
+ *
+ *  Maintainer(s):
+ *    AF        Adam Fritzler           mid@auk.cx
+ *    JF	Jochen Friedrich	jochen@scram.de
+ *
+ *  Modification History:
+ *	14-Jan-01	JF	Created
+ *	28-Oct-02	JF	Fixed probe of card for static compilation.
+ *				Fixed module init to not make hotplug go wild.
+ *	09-Nov-02	JF	Fixed early bail out on out of memory
+ *				situations if multiple cards are found.
+ *				Cleaned up some unnecessary console SPAM.
+ *	09-Dec-02	JF	Fixed module reference counting.
+ *	02-Jan-03	JF	Renamed to skisa.c
+ *
+ */
+static const char version[] = "skisa.c: v1.03 09/12/2002 by Jochen Friedrich\n";
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/trdevice.h>
+#include <linux/platform_device.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pci.h>
+#include <asm/dma.h>
+
+#include "tms380tr.h"
+
+#define SK_ISA_IO_EXTENT 32
+
+/* A zero-terminated list of I/O addresses to be probed. */
+static unsigned int portlist[] __initdata = {
+	0x0A20, 0x1A20, 0x0B20, 0x1B20, 0x0980, 0x1980, 0x0900, 0x1900,// SK
+	0
+};
+
+/* A zero-terminated list of IRQs to be probed. 
+ * Used again after initial probe for sktr_chipset_init, called from sktr_open.
+ */
+static const unsigned short irqlist[] = {
+	3, 5, 9, 10, 11, 12, 15,
+	0
+};
+
+/* A zero-terminated list of DMAs to be probed. */
+static int dmalist[] __initdata = {
+	5, 6, 7,
+	0
+};
+
+static char isa_cardname[] = "SK NET TR 4/16 ISA\0";
+static u64 dma_mask = ISA_MAX_ADDRESS;
+static int sk_isa_open(struct net_device *dev);
+static void sk_isa_read_eeprom(struct net_device *dev);
+static unsigned short sk_isa_setnselout_pins(struct net_device *dev);
+
+static unsigned short sk_isa_sifreadb(struct net_device *dev, unsigned short reg)
+{
+	return inb(dev->base_addr + reg);
+}
+
+static unsigned short sk_isa_sifreadw(struct net_device *dev, unsigned short reg)
+{
+	return inw(dev->base_addr + reg);
+}
+
+static void sk_isa_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
+{
+	outb(val, dev->base_addr + reg);
+}
+
+static void sk_isa_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
+{
+	outw(val, dev->base_addr + reg);
+}
+
+
+static int __init sk_isa_probe1(struct net_device *dev, int ioaddr)
+{
+	unsigned char old, chk1, chk2;
+
+	if (!request_region(ioaddr, SK_ISA_IO_EXTENT, isa_cardname))
+		return -ENODEV;
+
+	old = inb(ioaddr + SIFADR);	/* Get the old SIFADR value */
+
+	chk1 = 0;	/* Begin with check value 0 */
+	do {
+		/* Write new SIFADR value */
+		outb(chk1, ioaddr + SIFADR);
+
+		/* Read, invert and write */
+		chk2 = inb(ioaddr + SIFADD);
+		chk2 ^= 0x0FE;
+		outb(chk2, ioaddr + SIFADR);
+
+		/* Read, invert and compare */
+		chk2 = inb(ioaddr + SIFADD);
+		chk2 ^= 0x0FE;
+
+		if(chk1 != chk2) {
+			release_region(ioaddr, SK_ISA_IO_EXTENT);
+			return -ENODEV;
+		}
+
+		chk1 -= 2;
+	} while(chk1 != 0);	/* Repeat 128 times (all byte values) */
+
+    	/* Restore the SIFADR value */
+	outb(old, ioaddr + SIFADR);
+
+	dev->base_addr = ioaddr;
+	return 0;
+}
+
+static int __init setup_card(struct net_device *dev, struct device *pdev)
+{
+	struct net_local *tp;
+        static int versionprinted;
+	const unsigned *port;
+	int j, err = 0;
+
+	if (!dev)
+		return -ENOMEM;
+
+	SET_MODULE_OWNER(dev);
+	if (dev->base_addr)	/* probe specific location */
+		err = sk_isa_probe1(dev, dev->base_addr);
+	else {
+		for (port = portlist; *port; port++) {
+			err = sk_isa_probe1(dev, *port);
+			if (!err)
+				break;
+		}
+	}
+	if (err)
+		goto out5;
+
+	/* At this point we have found a valid card. */
+
+	if (versionprinted++ == 0)
+		printk(KERN_DEBUG "%s", version);
+
+	err = -EIO;
+	pdev->dma_mask = &dma_mask;
+	if (tmsdev_init(dev, pdev))
+		goto out4;
+
+	dev->base_addr &= ~3; 
+		
+	sk_isa_read_eeprom(dev);
+
+	printk(KERN_DEBUG "skisa.c:    Ring Station Address: ");
+	printk("%2.2x", dev->dev_addr[0]);
+	for (j = 1; j < 6; j++)
+		printk(":%2.2x", dev->dev_addr[j]);
+	printk("\n");
+		
+	tp = netdev_priv(dev);
+	tp->setnselout = sk_isa_setnselout_pins;
+		
+	tp->sifreadb = sk_isa_sifreadb;
+	tp->sifreadw = sk_isa_sifreadw;
+	tp->sifwriteb = sk_isa_sifwriteb;
+	tp->sifwritew = sk_isa_sifwritew;
+	
+	memcpy(tp->ProductID, isa_cardname, PROD_ID_SIZE + 1);
+
+	tp->tmspriv = NULL;
+
+	dev->open = sk_isa_open;
+	dev->stop = tms380tr_close;
+
+	if (dev->irq == 0)
+	{
+		for(j = 0; irqlist[j] != 0; j++)
+		{
+			dev->irq = irqlist[j];
+			if (!request_irq(dev->irq, tms380tr_interrupt, 0, 
+				isa_cardname, dev))
+				break;
+                }
+		
+                if(irqlist[j] == 0)
+                {
+                        printk(KERN_INFO "skisa.c: AutoSelect no IRQ available\n");
+			goto out3;
+		}
+	}
+	else
+	{
+		for(j = 0; irqlist[j] != 0; j++)
+			if (irqlist[j] == dev->irq)
+				break;
+		if (irqlist[j] == 0)
+		{
+			printk(KERN_INFO "skisa.c: Illegal IRQ %d specified\n",
+				dev->irq);
+			goto out3;
+		}
+		if (request_irq(dev->irq, tms380tr_interrupt, 0, 
+			isa_cardname, dev))
+		{
+                        printk(KERN_INFO "skisa.c: Selected IRQ %d not available\n",
+				dev->irq);
+			goto out3;
+		}
+	}
+
+	if (dev->dma == 0)
+	{
+		for(j = 0; dmalist[j] != 0; j++)
+		{
+			dev->dma = dmalist[j];
+                        if (!request_dma(dev->dma, isa_cardname))
+				break;
+		}
+
+		if(dmalist[j] == 0)
+		{
+			printk(KERN_INFO "skisa.c: AutoSelect no DMA available\n");
+			goto out2;
+		}
+	}
+	else
+	{
+		for(j = 0; dmalist[j] != 0; j++)
+			if (dmalist[j] == dev->dma)
+				break;
+		if (dmalist[j] == 0)
+		{
+                        printk(KERN_INFO "skisa.c: Illegal DMA %d specified\n",
+				dev->dma);
+			goto out2;
+		}
+		if (request_dma(dev->dma, isa_cardname))
+		{
+                        printk(KERN_INFO "skisa.c: Selected DMA %d not available\n",
+				dev->dma);
+			goto out2;
+		}
+	}
+
+	err = register_netdev(dev);
+	if (err)
+		goto out;
+
+	printk(KERN_DEBUG "%s:    IO: %#4lx  IRQ: %d  DMA: %d\n",
+	       dev->name, dev->base_addr, dev->irq, dev->dma);
+
+	return 0;
+out:
+	free_dma(dev->dma);
+out2:
+	free_irq(dev->irq, dev);
+out3:
+	tmsdev_term(dev);
+out4:
+	release_region(dev->base_addr, SK_ISA_IO_EXTENT);
+out5:
+	return err;
+}
+
+/*
+ * Reads MAC address from adapter RAM, which should've read it from
+ * the onboard ROM.  
+ *
+ * Calling this on a board that does not support it can be a very
+ * dangerous thing.  The Madge board, for instance, will lock your
+ * machine hard when this is called.  Luckily, its supported in a
+ * separate driver.  --ASF
+ */
+static void sk_isa_read_eeprom(struct net_device *dev)
+{
+	int i;
+	
+	/* Address: 0000:0000 */
+	sk_isa_sifwritew(dev, 0, SIFADX);
+	sk_isa_sifwritew(dev, 0, SIFADR);	
+	
+	/* Read six byte MAC address data */
+	dev->addr_len = 6;
+	for(i = 0; i < 6; i++)
+		dev->dev_addr[i] = sk_isa_sifreadw(dev, SIFINC) >> 8;
+}
+
+unsigned short sk_isa_setnselout_pins(struct net_device *dev)
+{
+	return 0;
+}
+
+static int sk_isa_open(struct net_device *dev)
+{  
+	struct net_local *tp = netdev_priv(dev);
+	unsigned short val = 0;
+	unsigned short oldval;
+	int i;
+
+	val = 0;
+	for(i = 0; irqlist[i] != 0; i++)
+	{
+		if(irqlist[i] == dev->irq)
+			break;
+	}
+
+	val |= CYCLE_TIME << 2;
+	val |= i << 4;
+	i = dev->dma - 5;
+	val |= i;
+	if(tp->DataRate == SPEED_4)
+		val |= LINE_SPEED_BIT;
+	else
+		val &= ~LINE_SPEED_BIT;
+	oldval = sk_isa_sifreadb(dev, POSREG);
+	/* Leave cycle bits alone */
+	oldval |= 0xf3;
+	val &= oldval;
+	sk_isa_sifwriteb(dev, val, POSREG);
+
+	return tms380tr_open(dev);
+}
+
+#define ISATR_MAX_ADAPTERS 3
+
+static int io[ISATR_MAX_ADAPTERS];
+static int irq[ISATR_MAX_ADAPTERS];
+static int dma[ISATR_MAX_ADAPTERS];
+
+MODULE_LICENSE("GPL");
+
+module_param_array(io, int, NULL, 0);
+module_param_array(irq, int, NULL, 0);
+module_param_array(dma, int, NULL, 0);
+
+static struct platform_device *sk_isa_dev[ISATR_MAX_ADAPTERS];
+
+static struct platform_driver sk_isa_driver = {
+	.driver		= {
+		.name	= "skisa",
+	},
+};
+
+static int __init sk_isa_init(void)
+{
+	struct net_device *dev;
+	struct platform_device *pdev;
+	int i, num = 0, err = 0;
+
+	err = platform_driver_register(&sk_isa_driver);
+	if (err)
+		return err;
+
+	for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
+		dev = alloc_trdev(sizeof(struct net_local));
+		if (!dev)
+			continue;
+
+		dev->base_addr = io[i];
+		dev->irq = irq[i];
+		dev->dma = dma[i];
+		pdev = platform_device_register_simple("skisa",
+			i, NULL, 0);
+		if (IS_ERR(pdev)) {
+			free_netdev(dev);
+			continue;
+		}
+		err = setup_card(dev, &pdev->dev);
+		if (!err) {
+			sk_isa_dev[i] = pdev;
+			platform_set_drvdata(sk_isa_dev[i], dev);
+			++num;
+		} else {
+			platform_device_unregister(pdev);
+			free_netdev(dev);
+		}
+	}
+
+	printk(KERN_NOTICE "skisa.c: %d cards found.\n", num);
+	/* Probe for cards. */
+	if (num == 0) {
+		printk(KERN_NOTICE "skisa.c: No cards found.\n");
+		platform_driver_unregister(&sk_isa_driver);
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static void __exit sk_isa_cleanup(void)
+{
+	struct net_device *dev;
+	int i;
+
+	for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
+		struct platform_device *pdev = sk_isa_dev[i];
+
+		if (!pdev)
+			continue;
+		dev = platform_get_drvdata(pdev);
+		unregister_netdev(dev);
+		release_region(dev->base_addr, SK_ISA_IO_EXTENT);
+		free_irq(dev->irq, dev);
+		free_dma(dev->dma);
+		tmsdev_term(dev);
+		free_netdev(dev);
+		platform_set_drvdata(pdev, NULL);
+		platform_device_unregister(pdev);
+	}
+	platform_driver_unregister(&sk_isa_driver);
+}
+
+module_init(sk_isa_init);
+module_exit(sk_isa_cleanup);

drivers/net/tokenring/smctr_firmware.h

@@ -0,0 +1,978 @@
+/*
+ * The firmware this driver downloads into the tokenring card is a
+ * separate program and is not GPL'd source code, even though the Linux
+ * side driver and the routine that loads this data into the card are.
+ *
+ * This firmware is licensed to you strictly for use in conjunction
+ * with the use of SMC TokenRing adapters. There is no waranty
+ * expressed or implied about its fitness for any purpose.
+ */
+
+/* smctr_firmware.h: SMC TokenRing driver firmware dump for Linux.
+ *
+ * Notes:
+ *  - This is an 8K binary image. (MCT.BIN v6.3C1 03/01/95)
+ *
+ * Authors:
+ *  - Jay Schulist <jschlst@samba.org>
+ */
+
+
+#if defined(CONFIG_SMCTR) || defined(CONFIG_SMCTR_MODULE)
+
+static const unsigned char smctr_code[] = {
+	0x0BC, 0x01D, 0x012, 0x03B, 0x063, 0x0B4, 0x0E9, 0x000,
+	0x000, 0x01F, 0x000, 0x001, 0x001, 0x000, 0x002, 0x005,
+	0x001, 0x000, 0x006, 0x003, 0x001, 0x000, 0x004, 0x009,
+	0x001, 0x000, 0x00A, 0x007, 0x001, 0x000, 0x008, 0x00B,
+	0x001, 0x000, 0x00C, 0x000, 0x000, 0x000, 0x000, 0x00F,
+	0x001, 0x000, 0x010, 0x00D, 0x001, 0x000, 0x00E, 0x013,
+	0x001, 0x000, 0x014, 0x011, 0x001, 0x000, 0x012, 0x000,
+	0x000, 0x005, 0x000, 0x015, 0x001, 0x000, 0x016, 0x019,
+	0x001, 0x000, 0x01A, 0x017, 0x001, 0x000, 0x018, 0x000,
+	0x000, 0x00E, 0x000, 0x000, 0x000, 0x001, 0x000, 0x000,
+	0x000, 0x004, 0x000, 0x01B, 0x001, 0x000, 0x01C, 0x000,
+	0x000, 0x007, 0x000, 0x000, 0x000, 0x00F, 0x000, 0x000,
+	0x000, 0x00B, 0x000, 0x01D, 0x001, 0x000, 0x01E, 0x000,
+	0x000, 0x008, 0x000, 0x000, 0x000, 0x002, 0x000, 0x000,
+	0x000, 0x00C, 0x000, 0x000, 0x000, 0x006, 0x000, 0x000,
+	0x000, 0x00D, 0x000, 0x000, 0x000, 0x003, 0x000, 0x000,
+	0x000, 0x00A, 0x000, 0x000, 0x000, 0x009, 0x000, 0x004,
+	0x078, 0x0C6, 0x0BC, 0x001, 0x094, 0x004, 0x093, 0x080,
+	0x0C8, 0x040, 0x062, 0x0E9, 0x0DA, 0x01C, 0x02C, 0x015,
+	0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x058,
+	0x00B, 0x0E9, 0x0E5, 0x0D5, 0x095, 0x0C1, 0x09D, 0x077,
+	0x0CE, 0x0BB, 0x0A0, 0x06E, 0x01C, 0x005, 0x0F6, 0x077,
+	0x0C6, 0x002, 0x0FA, 0x096, 0x070, 0x0E8, 0x01D, 0x0C0,
+	0x017, 0x00E, 0x002, 0x0FA, 0x058, 0x07D, 0x0C0, 0x05F,
+	0x072, 0x0CE, 0x0EC, 0x0A4, 0x0C3, 0x084, 0x090, 0x07A,
+	0x030, 0x0CD, 0x08D, 0x079, 0x019, 0x0E7, 0x06C, 0x024,
+	0x027, 0x09C, 0x008, 0x039, 0x007, 0x038, 0x0A8, 0x04A,
+	0x04C, 0x0EA, 0x04D, 0x098, 0x09B, 0x024, 0x04C, 0x0C0,
+	0x026, 0x0D3, 0x0E7, 0x054, 0x05A, 0x04D, 0x0F2, 0x04C,
+	0x00C, 0x013, 0x023, 0x049, 0x090, 0x032, 0x06E, 0x0A4,
+	0x0DF, 0x093, 0x071, 0x013, 0x077, 0x026, 0x0E1, 0x026,
+	0x0F8, 0x026, 0x00C, 0x04C, 0x012, 0x026, 0x008, 0x009,
+	0x082, 0x082, 0x060, 0x0A9, 0x030, 0x079, 0x036, 0x0B0,
+	0x0B2, 0x0A8, 0x0A7, 0x072, 0x064, 0x08F, 0x09B, 0x033,
+	0x033, 0x0F9, 0x0B8, 0x039, 0x0D5, 0x011, 0x073, 0x0AA,
+	0x075, 0x026, 0x05D, 0x026, 0x051, 0x093, 0x02A, 0x049,
+	0x094, 0x0C9, 0x095, 0x089, 0x0BC, 0x04D, 0x0C8, 0x09B,
+	0x080, 0x09B, 0x0A0, 0x099, 0x006, 0x04C, 0x086, 0x026,
+	0x058, 0x09B, 0x0A4, 0x09B, 0x099, 0x037, 0x062, 0x06C,
+	0x067, 0x09B, 0x033, 0x030, 0x0BF, 0x036, 0x066, 0x061,
+	0x0BF, 0x036, 0x0EC, 0x0C5, 0x0BD, 0x066, 0x082, 0x05A,
+	0x050, 0x031, 0x0D5, 0x09D, 0x098, 0x018, 0x029, 0x03C,
+	0x098, 0x086, 0x04C, 0x017, 0x026, 0x03E, 0x02C, 0x0B8,
+	0x069, 0x03B, 0x049, 0x02E, 0x0B4, 0x008, 0x043, 0x01A,
+	0x0A4, 0x0F9, 0x0B3, 0x051, 0x0F1, 0x010, 0x0F3, 0x043,
+	0x0CD, 0x008, 0x06F, 0x063, 0x079, 0x0B3, 0x033, 0x00E,
+	0x013, 0x098, 0x049, 0x098, 0x004, 0x0DA, 0x07C, 0x0E0,
+	0x052, 0x079, 0x031, 0x00C, 0x098, 0x02E, 0x04D, 0x0AC,
+	0x02C, 0x084, 0x014, 0x0EE, 0x04C, 0x0FE, 0x067, 0x05E,
+	0x0E4, 0x09A, 0x075, 0x029, 0x0D7, 0x0A9, 0x035, 0x03A,
+	0x094, 0x05B, 0x0D5, 0x09B, 0x058, 0x0B4, 0x0AF, 0x075,
+	0x066, 0x0AF, 0x014, 0x0A9, 0x0EF, 0x040, 0x095, 0x025,
+	0x008, 0x0B9, 0x0AD, 0x042, 0x0FC, 0x0D8, 0x0D9, 0x08C,
+	0x033, 0x00E, 0x013, 0x098, 0x066, 0x01E, 0x045, 0x0AC,
+	0x0B0, 0x00C, 0x042, 0x0D3, 0x0CC, 0x0A6, 0x012, 0x062,
+	0x0DE, 0x0B4, 0x0B1, 0x080, 0x049, 0x07D, 0x0A2, 0x0DE,
+	0x0B4, 0x018, 0x0C0, 0x024, 0x084, 0x0E6, 0x054, 0x0F5,
+	0x083, 0x046, 0x001, 0x068, 0x01A, 0x063, 0x00C, 0x0C6,
+	0x012, 0x064, 0x0FA, 0x04C, 0x035, 0x01C, 0x02C, 0x00E,
+	0x0AA, 0x0AA, 0x0AA, 0x0AA, 0x0AA, 0x0AA, 0x0AA, 0x0AA,
+	0x0AA, 0x0AA, 0x0AA, 0x0AA, 0x0AA, 0x0AD, 0x0D7, 0x002,
+	0x070, 0x0E0, 0x04C, 0x0F3, 0x0A1, 0x0C1, 0x0D5, 0x0C0,
+	0x03C, 0x0B9, 0x069, 0x039, 0x060, 0x04E, 0x058, 0x077,
+	0x002, 0x067, 0x093, 0x03C, 0x099, 0x0E4, 0x0CF, 0x038,
+	0x01C, 0x097, 0x02E, 0x040, 0x01B, 0x090, 0x031, 0x046,
+	0x0A3, 0x05E, 0x00E, 0x088, 0x034, 0x06A, 0x035, 0x0E0,
+	0x0E8, 0x0AA, 0x035, 0x01A, 0x0A9, 0x0F5, 0x015, 0x046,
+	0x0A3, 0x0EA, 0x07D, 0x04A, 0x0A3, 0x051, 0x0AA, 0x09F,
+	0x070, 0x054, 0x0A6, 0x057, 0x02E, 0x0B4, 0x0CD, 0x0C8,
+	0x0A3, 0x00C, 0x0C1, 0x0DA, 0x0C6, 0x0E1, 0x0CB, 0x07A,
+	0x0D4, 0x01C, 0x068, 0x0FF, 0x0CF, 0x055, 0x0A8, 0x0C0,
+	0x02D, 0x085, 0x011, 0x017, 0x044, 0x02A, 0x030, 0x00B,
+	0x04A, 0x088, 0x0C2, 0x04D, 0x0B5, 0x020, 0x0D5, 0x026,
+	0x001, 0x069, 0x051, 0x069, 0x052, 0x019, 0x052, 0x060,
+	0x016, 0x095, 0x016, 0x082, 0x096, 0x054, 0x098, 0x005,
+	0x0A5, 0x045, 0x0F3, 0x0DD, 0x06A, 0x0F9, 0x028, 0x018,
+	0x0EF, 0x000, 0x030, 0x030, 0x051, 0x04E, 0x044, 0x05D,
+	0x012, 0x0D1, 0x043, 0x0E6, 0x012, 0x06F, 0x09E, 0x0BA,
+	0x0CC, 0x0DF, 0x025, 0x003, 0x01D, 0x0E0, 0x006, 0x006,
+	0x00A, 0x030, 0x0CC, 0x0A9, 0x0EB, 0x02D, 0x000, 0x086,
+	0x0A6, 0x012, 0x065, 0x04F, 0x056, 0x0D6, 0x065, 0x049,
+	0x05F, 0x03D, 0x0E8, 0x037, 0x0C9, 0x040, 0x0C7, 0x078,
+	0x001, 0x081, 0x082, 0x08C, 0x033, 0x018, 0x049, 0x080,
+	0x0AE, 0x040, 0x0C5, 0x018, 0x005, 0x09C, 0x06D, 0x018,
+	0x066, 0x00E, 0x0F3, 0x0A0, 0x0C6, 0x012, 0x062, 0x0DE,
+	0x0F5, 0x004, 0x0B4, 0x0AC, 0x06B, 0x0C6, 0x019, 0x091,
+	0x073, 0x005, 0x048, 0x02E, 0x072, 0x094, 0x080, 0x073,
+	0x0A1, 0x0C8, 0x047, 0x036, 0x066, 0x064, 0x02F, 0x036,
+	0x066, 0x064, 0x007, 0x099, 0x002, 0x091, 0x08E, 0x072,
+	0x0D1, 0x00F, 0x09D, 0x006, 0x031, 0x073, 0x0A0, 0x0C3,
+	0x051, 0x06A, 0x01A, 0x020, 0x0BF, 0x03A, 0x00C, 0x02C,
+	0x073, 0x087, 0x043, 0x05E, 0x060, 0x002, 0x023, 0x0FC,
+	0x0E0, 0x0D6, 0x035, 0x0EF, 0x09E, 0x0F5, 0x0EF, 0x092,
+	0x081, 0x08E, 0x0F0, 0x003, 0x003, 0x005, 0x018, 0x066,
+	0x045, 0x0CC, 0x00B, 0x048, 0x02E, 0x070, 0x00A, 0x040,
+	0x039, 0x0D0, 0x0E4, 0x023, 0x09B, 0x033, 0x032, 0x017,
+	0x09B, 0x033, 0x032, 0x003, 0x0CC, 0x085, 0x048, 0x0C7,
+	0x038, 0x014, 0x0A5, 0x0CE, 0x029, 0x07E, 0x0D2, 0x080,
+	0x0A1, 0x0A8, 0x0B4, 0x048, 0x088, 0x02F, 0x0CE, 0x083,
+	0x00B, 0x01C, 0x0E1, 0x0D0, 0x0D7, 0x098, 0x004, 0x088,
+	0x087, 0x0CE, 0x096, 0x031, 0x073, 0x0A5, 0x08F, 0x0F3,
+	0x083, 0x058, 0x0D7, 0x0BE, 0x07B, 0x082, 0x0AF, 0x092,
+	0x081, 0x08E, 0x0F0, 0x003, 0x003, 0x005, 0x018, 0x066,
+	0x045, 0x0CC, 0x015, 0x020, 0x0B9, 0x0C8, 0x029, 0x000,
+	0x0E7, 0x043, 0x090, 0x08E, 0x06C, 0x0CC, 0x0C8, 0x05E,
+	0x06C, 0x0CC, 0x0C8, 0x00F, 0x032, 0x005, 0x023, 0x01C,
+	0x0E4, 0x050, 0x0D4, 0x05A, 0x017, 0x088, 0x02F, 0x0CE,
+	0x083, 0x010, 0x0F9, 0x0D0, 0x023, 0x017, 0x03A, 0x004,
+	0x035, 0x0E6, 0x000, 0x022, 0x016, 0x039, 0x0C3, 0x0A3,
+	0x0FC, 0x0E0, 0x0D6, 0x035, 0x0E0, 0x0BF, 0x0F4, 0x018,
+	0x0F2, 0x02D, 0x04D, 0x043, 0x051, 0x06E, 0x05A, 0x022,
+	0x01F, 0x030, 0x0D4, 0x017, 0x0E7, 0x041, 0x091, 0x073,
+	0x005, 0x048, 0x02E, 0x077, 0x069, 0x000, 0x0E7, 0x043,
+	0x090, 0x08E, 0x06C, 0x0CC, 0x0C8, 0x05E, 0x06C, 0x0CC,
+	0x0C8, 0x00F, 0x032, 0x005, 0x023, 0x01C, 0x0EF, 0x04C,
+	0x04E, 0x006, 0x004, 0x0C9, 0x09E, 0x00B, 0x0FF, 0x041,
+	0x08F, 0x022, 0x0D4, 0x0D4, 0x035, 0x016, 0x0E5, 0x0A2,
+	0x021, 0x0F3, 0x05A, 0x082, 0x0FC, 0x0E8, 0x032, 0x02E,
+	0x060, 0x0A9, 0x005, 0x0CE, 0x013, 0x048, 0x007, 0x03A,
+	0x01C, 0x084, 0x073, 0x066, 0x066, 0x042, 0x0F3, 0x066,
+	0x066, 0x040, 0x079, 0x090, 0x029, 0x018, 0x0E7, 0x00A,
+	0x098, 0x09C, 0x00A, 0x09E, 0x0B5, 0x012, 0x05C, 0x07C,
+	0x0C3, 0x031, 0x08B, 0x098, 0x02A, 0x07C, 0x0D3, 0x0ED,
+	0x038, 0x0E9, 0x0D3, 0x04E, 0x074, 0x0ED, 0x049, 0x09E,
+	0x00B, 0x0FF, 0x041, 0x08F, 0x022, 0x0D4, 0x0D4, 0x035,
+	0x016, 0x0E5, 0x0A2, 0x02D, 0x0EB, 0x045, 0x033, 0x08F,
+	0x0FC, 0x0F7, 0x0A0, 0x05F, 0x025, 0x003, 0x01D, 0x0E4,
+	0x00E, 0x006, 0x00A, 0x030, 0x0CC, 0x00C, 0x0F3, 0x0EB,
+	0x040, 0x0DE, 0x061, 0x0A8, 0x070, 0x092, 0x00A, 0x000,
+	0x0E1, 0x024, 0x01E, 0x000, 0x0E1, 0x024, 0x01E, 0x000,
+	0x0E1, 0x024, 0x01E, 0x000, 0x0E1, 0x024, 0x01E, 0x000,
+	0x0E1, 0x024, 0x01E, 0x001, 0x00F, 0x098, 0x02A, 0x00B,
+	0x0F3, 0x0A0, 0x0C8, 0x0B9, 0x0A2, 0x0A4, 0x017, 0x03A,
+	0x069, 0x000, 0x0E7, 0x043, 0x090, 0x08E, 0x075, 0x048,
+	0x05E, 0x070, 0x069, 0x001, 0x0E6, 0x000, 0x052, 0x031,
+	0x0CC, 0x018, 0x014, 0x0A5, 0x0CC, 0x009, 0x082, 0x094,
+	0x073, 0x00C, 0x0A0, 0x091, 0x0F5, 0x025, 0x0CC, 0x007,
+	0x006, 0x084, 0x084, 0x09F, 0x030, 0x0A2, 0x0A4, 0x07D,
+	0x050, 0x075, 0x0A6, 0x065, 0x001, 0x04A, 0x08E, 0x0B4,
+	0x0CC, 0x0C4, 0x035, 0x054, 0x075, 0x066, 0x0A4, 0x097,
+	0x07A, 0x089, 0x050, 0x053, 0x013, 0x080, 0x019, 0x0E3,
+	0x049, 0x05C, 0x06D, 0x0CE, 0x0A9, 0x040, 0x035, 0x006,
+	0x078, 0x0D2, 0x057, 0x006, 0x0F1, 0x0B3, 0x02A, 0x08D,
+	0x097, 0x023, 0x062, 0x092, 0x05D, 0x069, 0x099, 0x01C,
+	0x06A, 0x036, 0x0E6, 0x0CD, 0x046, 0x012, 0x06F, 0x09E,
+	0x0E1, 0x0AB, 0x0E4, 0x0A3, 0x00C, 0x0C0, 0x0DE, 0x0AC,
+	0x0D4, 0x00D, 0x028, 0x01B, 0x0D0, 0x012, 0x0A5, 0x000,
+	0x0F8, 0x04B, 0x0AD, 0x033, 0x028, 0x006, 0x0A0, 0x0DE,
+	0x014, 0x097, 0x03A, 0x089, 0x05D, 0x0C0, 0x00D, 0x0E3,
+	0x006, 0x090, 0x092, 0x05D, 0x069, 0x098, 0x066, 0x0B9,
+	0x019, 0x095, 0x0E4, 0x0A8, 0x0CF, 0x09D, 0x033, 0x018,
+	0x049, 0x0BE, 0x07B, 0x086, 0x0AF, 0x092, 0x08C, 0x033,
+	0x024, 0x014, 0x00C, 0x0F4, 0x083, 0x024, 0x021, 0x0C2,
+	0x070, 0x0BF, 0x0F4, 0x018, 0x0F2, 0x02D, 0x04D, 0x043,
+	0x051, 0x06E, 0x05A, 0x022, 0x01F, 0x032, 0x0A8, 0x02F,
+	0x0CE, 0x083, 0x022, 0x0E6, 0x005, 0x0A4, 0x017, 0x03A,
+	0x069, 0x000, 0x0E7, 0x043, 0x090, 0x08E, 0x075, 0x048,
+	0x05E, 0x070, 0x069, 0x001, 0x0E6, 0x042, 0x0A4, 0x063,
+	0x098, 0x002, 0x029, 0x04B, 0x09A, 0x029, 0x078, 0x0E9,
+	0x040, 0x053, 0x013, 0x081, 0x081, 0x032, 0x067, 0x082,
+	0x0FF, 0x0D0, 0x063, 0x0C8, 0x0B5, 0x035, 0x00D, 0x045,
+	0x0AE, 0x050, 0x008, 0x07C, 0x0E0, 0x0D0, 0x05F, 0x09D,
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+	0x026, 0x0D3, 0x0E7, 0x015, 0x00C, 0x03C, 0x0E2, 0x0AC,
+	0x0FE, 0x07B, 0x04A, 0x022, 0x0E7, 0x08A, 0x085, 0x0F9,
+	0x09E, 0x059, 0x097, 0x07A, 0x08D, 0x00C, 0x0CB, 0x0A5,
+	0x027, 0x0F3, 0x0A0, 0x041, 0x072, 0x062, 0x019, 0x037,
+	0x0DE, 0x070, 0x028, 0x08B, 0x09C, 0x08A, 0x00E, 0x039,
+	0x0D4, 0x08D, 0x00F, 0x056, 0x036, 0x06D, 0x009, 0x04E,
+	0x0BD, 0x059, 0x02C, 0x0CE, 0x0A5, 0x06B, 0x00B, 0x022,
+	0x0D9, 0x09D, 0x0C9, 0x0B2, 0x097, 0x0BE, 0x0F3, 0x081,
+	0x04A, 0x07D, 0x065, 0x0A3, 0x000, 0x093, 0x08F, 0x067,
+	0x029, 0x078, 0x0C2, 0x04D, 0x0C1, 0x0D1, 0x006, 0x082,
+	0x031, 0x0AF, 0x007, 0x038, 0x034, 0x011, 0x0F3, 0x0A8,
+	0x02A, 0x09E, 0x0A8, 0x066, 0x01A, 0x0A4, 0x0A5, 0x04F,
+	0x05A, 0x00C, 0x011, 0x08F, 0x0AA, 0x07B, 0x0D0, 0x065,
+	0x049, 0x045, 0x0BD, 0x0E9, 0x062, 0x0D2, 0x0B1, 0x09E,
+	0x06C, 0x0CC, 0x0C6, 0x019, 0x087, 0x009, 0x0C3, 0x08E,
+	0x075, 0x041, 0x01F, 0x03A, 0x0A5, 0x013, 0x0D5, 0x055,
+	0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055,
+	0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055,
+	0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055,
+	0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055,
+	0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055,
+	0x055, 0x055, 0x055, 0x05A, 0x0CC, 0x090
+ };
+
+#endif	/* defined(CONFIG_SMCTR) || defined(CONFIG_SMCTR_MODULE) */

drivers/net/tokenring/tmspci.c

@@ -0,0 +1,255 @@
+/*
+ *  tmspci.c: A generic network driver for TMS380-based PCI token ring cards.
+ *
+ *  Written 1999 by Adam Fritzler
+ *
+ *  This software may be used and distributed according to the terms
+ *  of the GNU General Public License, incorporated herein by reference.
+ *
+ *  This driver module supports the following cards:
+ *	- SysKonnect TR4/16(+) PCI	(SK-4590)
+ *	- SysKonnect TR4/16 PCI		(SK-4591)
+ *      - Compaq TR 4/16 PCI
+ *      - Thomas-Conrad TC4048 4/16 PCI 
+ *      - 3Com 3C339 Token Link Velocity
+ *
+ *  Maintainer(s):
+ *    AF	Adam Fritzler		mid@auk.cx
+ *
+ *  Modification History:
+ *	30-Dec-99	AF	Split off from the tms380tr driver.
+ *	22-Jan-00	AF	Updated to use indirect read/writes
+ *	23-Nov-00	JG	New PCI API, cleanups
+ *
+ *  TODO:
+ *	1. See if we can use MMIO instead of port accesses
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/trdevice.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "tms380tr.h"
+
+static char version[] __devinitdata =
+"tmspci.c: v1.02 23/11/2000 by Adam Fritzler\n";
+
+#define TMS_PCI_IO_EXTENT 32
+
+struct card_info {
+	unsigned char nselout[2]; /* NSELOUT vals for 4mb([0]) and 16mb([1]) */
+	char *name;
+};
+
+static struct card_info card_info_table[] = {
+	{ {0x03, 0x01}, "Compaq 4/16 TR PCI"},
+	{ {0x03, 0x01}, "SK NET TR 4/16 PCI"},
+	{ {0x03, 0x01}, "Thomas-Conrad TC4048 PCI 4/16"},
+	{ {0x03, 0x01}, "3Com Token Link Velocity"},
+};
+
+static struct pci_device_id tmspci_pci_tbl[] = {
+	{ PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_TOKENRING, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+	{ PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_TR, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
+	{ PCI_VENDOR_ID_TCONRAD, PCI_DEVICE_ID_TCONRAD_TOKENRING, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
+	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C339, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
+	{ }			/* Terminating entry */
+};
+MODULE_DEVICE_TABLE(pci, tmspci_pci_tbl);
+
+MODULE_LICENSE("GPL");
+
+static void tms_pci_read_eeprom(struct net_device *dev);
+static unsigned short tms_pci_setnselout_pins(struct net_device *dev);
+
+static unsigned short tms_pci_sifreadb(struct net_device *dev, unsigned short reg)
+{
+	return inb(dev->base_addr + reg);
+}
+
+static unsigned short tms_pci_sifreadw(struct net_device *dev, unsigned short reg)
+{
+	return inw(dev->base_addr + reg);
+}
+
+static void tms_pci_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
+{
+	outb(val, dev->base_addr + reg);
+}
+
+static void tms_pci_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
+{
+	outw(val, dev->base_addr + reg);
+}
+
+static int __devinit tms_pci_attach(struct pci_dev *pdev, const struct pci_device_id *ent)
+{	
+	static int versionprinted;
+	struct net_device *dev;
+	struct net_local *tp;
+	int i, ret;
+	unsigned int pci_irq_line;
+	unsigned long pci_ioaddr;
+	struct card_info *cardinfo = &card_info_table[ent->driver_data];
+
+	if (versionprinted++ == 0)
+		printk("%s", version);
+
+	if (pci_enable_device(pdev))
+		return -EIO;
+
+	/* Remove I/O space marker in bit 0. */
+	pci_irq_line = pdev->irq;
+	pci_ioaddr = pci_resource_start (pdev, 0);
+
+	/* At this point we have found a valid card. */
+	dev = alloc_trdev(sizeof(struct net_local));
+	if (!dev)
+		return -ENOMEM;
+	SET_MODULE_OWNER(dev);
+
+	if (!request_region(pci_ioaddr, TMS_PCI_IO_EXTENT, dev->name)) {
+		ret = -EBUSY;
+		goto err_out_trdev;
+	}
+
+	ret = request_irq(pdev->irq, tms380tr_interrupt, IRQF_SHARED,
+			  dev->name, dev);
+	if (ret)
+		goto err_out_region;
+
+	dev->base_addr	= pci_ioaddr;
+	dev->irq 	= pci_irq_line;
+	dev->dma	= 0;
+
+	printk("%s: %s\n", dev->name, cardinfo->name);
+	printk("%s:    IO: %#4lx  IRQ: %d\n",
+	       dev->name, dev->base_addr, dev->irq);
+		
+	tms_pci_read_eeprom(dev);
+
+	printk("%s:    Ring Station Address: ", dev->name);
+	printk("%2.2x", dev->dev_addr[0]);
+	for (i = 1; i < 6; i++)
+		printk(":%2.2x", dev->dev_addr[i]);
+	printk("\n");
+		
+	ret = tmsdev_init(dev, &pdev->dev);
+	if (ret) {
+		printk("%s: unable to get memory for dev->priv.\n", dev->name);
+		goto err_out_irq;
+	}
+
+	tp = dev->priv;
+	tp->setnselout = tms_pci_setnselout_pins;
+		
+	tp->sifreadb = tms_pci_sifreadb;
+	tp->sifreadw = tms_pci_sifreadw;
+	tp->sifwriteb = tms_pci_sifwriteb;
+	tp->sifwritew = tms_pci_sifwritew;
+		
+	memcpy(tp->ProductID, cardinfo->name, PROD_ID_SIZE + 1);
+
+	tp->tmspriv = cardinfo;
+
+	dev->open = tms380tr_open;
+	dev->stop = tms380tr_close;
+	pci_set_drvdata(pdev, dev);
+	SET_NETDEV_DEV(dev, &pdev->dev);
+
+	ret = register_netdev(dev);
+	if (ret)
+		goto err_out_tmsdev;
+	
+	return 0;
+
+err_out_tmsdev:
+	pci_set_drvdata(pdev, NULL);
+	tmsdev_term(dev);
+err_out_irq:
+	free_irq(pdev->irq, dev);
+err_out_region:
+	release_region(pci_ioaddr, TMS_PCI_IO_EXTENT);
+err_out_trdev:
+	free_netdev(dev);
+	return ret;
+}
+
+/*
+ * Reads MAC address from adapter RAM, which should've read it from
+ * the onboard ROM.  
+ *
+ * Calling this on a board that does not support it can be a very
+ * dangerous thing.  The Madge board, for instance, will lock your
+ * machine hard when this is called.  Luckily, its supported in a
+ * separate driver.  --ASF
+ */
+static void tms_pci_read_eeprom(struct net_device *dev)
+{
+	int i;
+	
+	/* Address: 0000:0000 */
+	tms_pci_sifwritew(dev, 0, SIFADX);
+	tms_pci_sifwritew(dev, 0, SIFADR);	
+	
+	/* Read six byte MAC address data */
+	dev->addr_len = 6;
+	for(i = 0; i < 6; i++)
+		dev->dev_addr[i] = tms_pci_sifreadw(dev, SIFINC) >> 8;
+}
+
+static unsigned short tms_pci_setnselout_pins(struct net_device *dev)
+{
+	unsigned short val = 0;
+	struct net_local *tp = dev->priv;
+	struct card_info *cardinfo = tp->tmspriv;
+  
+	if(tp->DataRate == SPEED_4)
+		val |= cardinfo->nselout[0];	/* Set 4Mbps */
+	else
+		val |= cardinfo->nselout[1];	/* Set 16Mbps */
+	return val;
+}
+
+static void __devexit tms_pci_detach (struct pci_dev *pdev)
+{
+	struct net_device *dev = pci_get_drvdata(pdev);
+
+	BUG_ON(!dev);
+	unregister_netdev(dev);
+	release_region(dev->base_addr, TMS_PCI_IO_EXTENT);
+	free_irq(dev->irq, dev);
+	tmsdev_term(dev);
+	free_netdev(dev);
+	pci_set_drvdata(pdev, NULL);
+}
+
+static struct pci_driver tms_pci_driver = {
+	.name		= "tmspci",
+	.id_table	= tmspci_pci_tbl,
+	.probe		= tms_pci_attach,
+	.remove		= __devexit_p(tms_pci_detach),
+};
+
+static int __init tms_pci_init (void)
+{
+	return pci_register_driver(&tms_pci_driver);
+}
+
+static void __exit tms_pci_rmmod (void)
+{
+	pci_unregister_driver (&tms_pci_driver);
+}
+
+module_init(tms_pci_init);
+module_exit(tms_pci_rmmod);
+