Creation of Cybook 2416 (actually Gen4) repository
This commit is contained in:
mlt
11
drivers/serial/cpm_uart/Makefile
Normal file
11
drivers/serial/cpm_uart/Makefile
Normal file
@@ -0,0 +1,11 @@
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#
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# Makefile for the Motorola 8xx FEC ethernet controller
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#
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obj-$(CONFIG_SERIAL_CPM) += cpm_uart.o
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# Select the correct platform objects.
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cpm_uart-objs-$(CONFIG_CPM2) += cpm_uart_cpm2.o
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cpm_uart-objs-$(CONFIG_8xx) += cpm_uart_cpm1.o
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cpm_uart-objs := cpm_uart_core.o $(cpm_uart-objs-y)
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136
drivers/serial/cpm_uart/cpm_uart.h
Normal file
136
drivers/serial/cpm_uart/cpm_uart.h
Normal file
@@ -0,0 +1,136 @@
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/*
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* linux/drivers/serial/cpm_uart.h
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*
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* Driver for CPM (SCC/SMC) serial ports
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*
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* Copyright (C) 2004 Freescale Semiconductor, Inc.
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*
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* 2006 (c) MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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#ifndef CPM_UART_H
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#define CPM_UART_H
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#include <linux/platform_device.h>
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#include <linux/fs_uart_pd.h>
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#if defined(CONFIG_CPM2)
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#include "cpm_uart_cpm2.h"
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#elif defined(CONFIG_8xx)
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#include "cpm_uart_cpm1.h"
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#endif
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#define SERIAL_CPM_MAJOR 204
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#define SERIAL_CPM_MINOR 46
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#define IS_SMC(pinfo) (pinfo->flags & FLAG_SMC)
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#define IS_DISCARDING(pinfo) (pinfo->flags & FLAG_DISCARDING)
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#define FLAG_DISCARDING 0x00000004 /* when set, don't discard */
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#define FLAG_SMC 0x00000002
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#define FLAG_CONSOLE 0x00000001
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#define UART_SMC1 fsid_smc1_uart
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#define UART_SMC2 fsid_smc2_uart
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#define UART_SCC1 fsid_scc1_uart
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#define UART_SCC2 fsid_scc2_uart
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#define UART_SCC3 fsid_scc3_uart
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#define UART_SCC4 fsid_scc4_uart
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#define UART_NR fs_uart_nr
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#define RX_NUM_FIFO 4
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#define RX_BUF_SIZE 32
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#define TX_NUM_FIFO 4
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#define TX_BUF_SIZE 32
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#define SCC_WAIT_CLOSING 100
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struct uart_cpm_port {
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struct uart_port port;
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u16 rx_nrfifos;
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u16 rx_fifosize;
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u16 tx_nrfifos;
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u16 tx_fifosize;
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smc_t *smcp;
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smc_uart_t *smcup;
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scc_t *sccp;
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scc_uart_t *sccup;
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volatile cbd_t *rx_bd_base;
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volatile cbd_t *rx_cur;
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volatile cbd_t *tx_bd_base;
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volatile cbd_t *tx_cur;
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unsigned char *tx_buf;
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unsigned char *rx_buf;
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u32 flags;
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void (*set_lineif)(struct uart_cpm_port *);
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u8 brg;
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uint dp_addr;
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void *mem_addr;
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dma_addr_t dma_addr;
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u32 mem_size;
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/* helpers */
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int baud;
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int bits;
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/* Keep track of 'odd' SMC2 wirings */
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int is_portb;
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/* wait on close if needed */
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int wait_closing;
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};
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extern int cpm_uart_port_map[UART_NR];
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extern int cpm_uart_nr;
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extern struct uart_cpm_port cpm_uart_ports[UART_NR];
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/* these are located in their respective files */
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void cpm_line_cr_cmd(int line, int cmd);
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int __init cpm_uart_init_portdesc(void);
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int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
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void cpm_uart_freebuf(struct uart_cpm_port *pinfo);
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void smc1_lineif(struct uart_cpm_port *pinfo);
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void smc2_lineif(struct uart_cpm_port *pinfo);
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void scc1_lineif(struct uart_cpm_port *pinfo);
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void scc2_lineif(struct uart_cpm_port *pinfo);
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void scc3_lineif(struct uart_cpm_port *pinfo);
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void scc4_lineif(struct uart_cpm_port *pinfo);
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/*
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virtual to phys transtalion
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*/
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static inline unsigned long cpu2cpm_addr(void* addr, struct uart_cpm_port *pinfo)
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{
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int offset;
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u32 val = (u32)addr;
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/* sane check */
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if (likely((val >= (u32)pinfo->mem_addr)) &&
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(val<((u32)pinfo->mem_addr + pinfo->mem_size))) {
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offset = val - (u32)pinfo->mem_addr;
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return pinfo->dma_addr+offset;
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}
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/* something nasty happened */
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BUG();
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return 0;
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}
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static inline void *cpm2cpu_addr(unsigned long addr, struct uart_cpm_port *pinfo)
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{
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int offset;
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u32 val = addr;
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/* sane check */
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if (likely((val >= pinfo->dma_addr) &&
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(val<(pinfo->dma_addr + pinfo->mem_size)))) {
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offset = val - (u32)pinfo->dma_addr;
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return (void*)(pinfo->mem_addr+offset);
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}
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/* something nasty happened */
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BUG();
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return 0;
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}
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#endif /* CPM_UART_H */
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1389
drivers/serial/cpm_uart/cpm_uart_core.c
Normal file
1389
drivers/serial/cpm_uart/cpm_uart_core.c
Normal file
File diff suppressed because it is too large
Load Diff
281
drivers/serial/cpm_uart/cpm_uart_cpm1.c
Normal file
281
drivers/serial/cpm_uart/cpm_uart_cpm1.c
Normal file
@@ -0,0 +1,281 @@
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/*
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* linux/drivers/serial/cpm_uart.c
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*
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* Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
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*
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* Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
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* Pantelis Antoniou (panto@intracom.gr) (CPM1)
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*
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* Copyright (C) 2004 Freescale Semiconductor, Inc.
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* (C) 2004 Intracom, S.A.
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* (C) 2006 MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
|
||||
*
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||||
* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/tty.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/device.h>
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#include <linux/bootmem.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/fs_pd.h>
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#include <linux/serial_core.h>
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#include <linux/kernel.h>
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#include "cpm_uart.h"
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/**************************************************************/
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void cpm_line_cr_cmd(int line, int cmd)
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{
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ushort val;
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volatile cpm8xx_t *cp = cpmp;
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switch (line) {
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case UART_SMC1:
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val = mk_cr_cmd(CPM_CR_CH_SMC1, cmd) | CPM_CR_FLG;
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break;
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case UART_SMC2:
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val = mk_cr_cmd(CPM_CR_CH_SMC2, cmd) | CPM_CR_FLG;
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break;
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case UART_SCC1:
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val = mk_cr_cmd(CPM_CR_CH_SCC1, cmd) | CPM_CR_FLG;
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break;
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case UART_SCC2:
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val = mk_cr_cmd(CPM_CR_CH_SCC2, cmd) | CPM_CR_FLG;
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break;
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case UART_SCC3:
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val = mk_cr_cmd(CPM_CR_CH_SCC3, cmd) | CPM_CR_FLG;
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break;
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case UART_SCC4:
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val = mk_cr_cmd(CPM_CR_CH_SCC4, cmd) | CPM_CR_FLG;
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break;
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default:
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return;
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}
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cp->cp_cpcr = val;
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while (cp->cp_cpcr & CPM_CR_FLG) ;
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}
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void smc1_lineif(struct uart_cpm_port *pinfo)
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{
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pinfo->brg = 1;
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}
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void smc2_lineif(struct uart_cpm_port *pinfo)
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{
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pinfo->brg = 2;
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}
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void scc1_lineif(struct uart_cpm_port *pinfo)
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{
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/* XXX SCC1: insert port configuration here */
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pinfo->brg = 1;
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}
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void scc2_lineif(struct uart_cpm_port *pinfo)
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{
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/* XXX SCC2: insert port configuration here */
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pinfo->brg = 2;
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}
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void scc3_lineif(struct uart_cpm_port *pinfo)
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{
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/* XXX SCC3: insert port configuration here */
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pinfo->brg = 3;
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}
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void scc4_lineif(struct uart_cpm_port *pinfo)
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{
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/* XXX SCC4: insert port configuration here */
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pinfo->brg = 4;
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}
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/*
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* Allocate DP-Ram and memory buffers. We need to allocate a transmit and
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* receive buffer descriptors from dual port ram, and a character
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* buffer area from host mem. If we are allocating for the console we need
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* to do it from bootmem
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*/
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int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
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{
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int dpmemsz, memsz;
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u8 *dp_mem;
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uint dp_offset;
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u8 *mem_addr;
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dma_addr_t dma_addr = 0;
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pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
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dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
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dp_offset = cpm_dpalloc(dpmemsz, 8);
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if (IS_DPERR(dp_offset)) {
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printk(KERN_ERR
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"cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
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return -ENOMEM;
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}
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dp_mem = cpm_dpram_addr(dp_offset);
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memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
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L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
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if (is_con) {
|
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/* was hostalloc but changed cause it blows away the */
|
||||
/* large tlb mapping when pinning the kernel area */
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mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
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dma_addr = (u32)cpm_dpram_phys(mem_addr);
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} else
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mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
|
||||
GFP_KERNEL);
|
||||
|
||||
if (mem_addr == NULL) {
|
||||
cpm_dpfree(dp_offset);
|
||||
printk(KERN_ERR
|
||||
"cpm_uart_cpm1.c: could not allocate coherent memory\n");
|
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return -ENOMEM;
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}
|
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pinfo->dp_addr = dp_offset;
|
||||
pinfo->mem_addr = mem_addr; /* virtual address*/
|
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pinfo->dma_addr = dma_addr; /* physical address*/
|
||||
pinfo->mem_size = memsz;
|
||||
|
||||
pinfo->rx_buf = mem_addr;
|
||||
pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
|
||||
* pinfo->rx_fifosize);
|
||||
|
||||
pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
|
||||
pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
|
||||
{
|
||||
dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
|
||||
pinfo->rx_fifosize) +
|
||||
L1_CACHE_ALIGN(pinfo->tx_nrfifos *
|
||||
pinfo->tx_fifosize), pinfo->mem_addr,
|
||||
pinfo->dma_addr);
|
||||
|
||||
cpm_dpfree(pinfo->dp_addr);
|
||||
}
|
||||
|
||||
/* Setup any dynamic params in the uart desc */
|
||||
int __init cpm_uart_init_portdesc(void)
|
||||
{
|
||||
pr_debug("CPM uart[-]:init portdesc\n");
|
||||
|
||||
cpm_uart_nr = 0;
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC1
|
||||
cpm_uart_ports[UART_SMC1].smcp = &cpmp->cp_smc[0];
|
||||
/*
|
||||
* Is SMC1 being relocated?
|
||||
*/
|
||||
# ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
|
||||
cpm_uart_ports[UART_SMC1].smcup =
|
||||
(smc_uart_t *) & cpmp->cp_dparam[0x3C0];
|
||||
# else
|
||||
cpm_uart_ports[UART_SMC1].smcup =
|
||||
(smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC1];
|
||||
# endif
|
||||
cpm_uart_ports[UART_SMC1].port.mapbase =
|
||||
(unsigned long)&cpmp->cp_smc[0];
|
||||
cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
|
||||
cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
|
||||
cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC2
|
||||
cpm_uart_ports[UART_SMC2].smcp = &cpmp->cp_smc[1];
|
||||
cpm_uart_ports[UART_SMC2].smcup =
|
||||
(smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC2];
|
||||
cpm_uart_ports[UART_SMC2].port.mapbase =
|
||||
(unsigned long)&cpmp->cp_smc[1];
|
||||
cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
|
||||
cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
|
||||
cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC1
|
||||
cpm_uart_ports[UART_SCC1].sccp = &cpmp->cp_scc[0];
|
||||
cpm_uart_ports[UART_SCC1].sccup =
|
||||
(scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC1];
|
||||
cpm_uart_ports[UART_SCC1].port.mapbase =
|
||||
(unsigned long)&cpmp->cp_scc[0];
|
||||
cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
|
||||
~(UART_SCCM_TX | UART_SCCM_RX);
|
||||
cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC2
|
||||
cpm_uart_ports[UART_SCC2].sccp = &cpmp->cp_scc[1];
|
||||
cpm_uart_ports[UART_SCC2].sccup =
|
||||
(scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC2];
|
||||
cpm_uart_ports[UART_SCC2].port.mapbase =
|
||||
(unsigned long)&cpmp->cp_scc[1];
|
||||
cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
|
||||
~(UART_SCCM_TX | UART_SCCM_RX);
|
||||
cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC3
|
||||
cpm_uart_ports[UART_SCC3].sccp = &cpmp->cp_scc[2];
|
||||
cpm_uart_ports[UART_SCC3].sccup =
|
||||
(scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC3];
|
||||
cpm_uart_ports[UART_SCC3].port.mapbase =
|
||||
(unsigned long)&cpmp->cp_scc[2];
|
||||
cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
|
||||
~(UART_SCCM_TX | UART_SCCM_RX);
|
||||
cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC4
|
||||
cpm_uart_ports[UART_SCC4].sccp = &cpmp->cp_scc[3];
|
||||
cpm_uart_ports[UART_SCC4].sccup =
|
||||
(scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC4];
|
||||
cpm_uart_ports[UART_SCC4].port.mapbase =
|
||||
(unsigned long)&cpmp->cp_scc[3];
|
||||
cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
|
||||
~(UART_SCCM_TX | UART_SCCM_RX);
|
||||
cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
42
drivers/serial/cpm_uart/cpm_uart_cpm1.h
Normal file
42
drivers/serial/cpm_uart/cpm_uart_cpm1.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* linux/drivers/serial/cpm_uart/cpm_uart_cpm1.h
|
||||
*
|
||||
* Driver for CPM (SCC/SMC) serial ports
|
||||
*
|
||||
* definitions for cpm1
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef CPM_UART_CPM1_H
|
||||
#define CPM_UART_CPM1_H
|
||||
|
||||
#include <asm/commproc.h>
|
||||
|
||||
/* defines for IRQs */
|
||||
#define SMC1_IRQ (CPM_IRQ_OFFSET + CPMVEC_SMC1)
|
||||
#define SMC2_IRQ (CPM_IRQ_OFFSET + CPMVEC_SMC2)
|
||||
#define SCC1_IRQ (CPM_IRQ_OFFSET + CPMVEC_SCC1)
|
||||
#define SCC2_IRQ (CPM_IRQ_OFFSET + CPMVEC_SCC2)
|
||||
#define SCC3_IRQ (CPM_IRQ_OFFSET + CPMVEC_SCC3)
|
||||
#define SCC4_IRQ (CPM_IRQ_OFFSET + CPMVEC_SCC4)
|
||||
|
||||
static inline void cpm_set_brg(int brg, int baud)
|
||||
{
|
||||
cpm_setbrg(brg, baud);
|
||||
}
|
||||
|
||||
static inline void cpm_set_scc_fcr(volatile scc_uart_t * sup)
|
||||
{
|
||||
sup->scc_genscc.scc_rfcr = SMC_EB;
|
||||
sup->scc_genscc.scc_tfcr = SMC_EB;
|
||||
}
|
||||
|
||||
static inline void cpm_set_smc_fcr(volatile smc_uart_t * up)
|
||||
{
|
||||
up->smc_rfcr = SMC_EB;
|
||||
up->smc_tfcr = SMC_EB;
|
||||
}
|
||||
|
||||
#define DPRAM_BASE ((unsigned char *)&cpmp->cp_dpmem[0])
|
||||
|
||||
#endif
|
||||
388
drivers/serial/cpm_uart/cpm_uart_cpm2.c
Normal file
388
drivers/serial/cpm_uart/cpm_uart_cpm2.c
Normal file
@@ -0,0 +1,388 @@
|
||||
/*
|
||||
* linux/drivers/serial/cpm_uart_cpm2.c
|
||||
*
|
||||
* Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
|
||||
*
|
||||
* Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
|
||||
* Pantelis Antoniou (panto@intracom.gr) (CPM1)
|
||||
*
|
||||
* Copyright (C) 2004 Freescale Semiconductor, Inc.
|
||||
* (C) 2004 Intracom, S.A.
|
||||
* (C) 2006 MontaVista Software, Inc.
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/sysrq.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/fs_pd.h>
|
||||
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "cpm_uart.h"
|
||||
|
||||
/**************************************************************/
|
||||
|
||||
void cpm_line_cr_cmd(int line, int cmd)
|
||||
{
|
||||
ulong val;
|
||||
volatile cpm_cpm2_t *cp = cpm2_map(im_cpm);
|
||||
|
||||
|
||||
switch (line) {
|
||||
case UART_SMC1:
|
||||
val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
|
||||
cmd) | CPM_CR_FLG;
|
||||
break;
|
||||
case UART_SMC2:
|
||||
val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
|
||||
cmd) | CPM_CR_FLG;
|
||||
break;
|
||||
case UART_SCC1:
|
||||
val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
|
||||
cmd) | CPM_CR_FLG;
|
||||
break;
|
||||
case UART_SCC2:
|
||||
val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
|
||||
cmd) | CPM_CR_FLG;
|
||||
break;
|
||||
case UART_SCC3:
|
||||
val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
|
||||
cmd) | CPM_CR_FLG;
|
||||
break;
|
||||
case UART_SCC4:
|
||||
val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
|
||||
cmd) | CPM_CR_FLG;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
|
||||
}
|
||||
cp->cp_cpcr = val;
|
||||
while (cp->cp_cpcr & CPM_CR_FLG) ;
|
||||
|
||||
cpm2_unmap(cp);
|
||||
}
|
||||
|
||||
void smc1_lineif(struct uart_cpm_port *pinfo)
|
||||
{
|
||||
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
|
||||
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
|
||||
|
||||
/* SMC1 is only on port D */
|
||||
io->iop_ppard |= 0x00c00000;
|
||||
io->iop_pdird |= 0x00400000;
|
||||
io->iop_pdird &= ~0x00800000;
|
||||
io->iop_psord &= ~0x00c00000;
|
||||
|
||||
/* Wire BRG1 to SMC1 */
|
||||
cpmux->cmx_smr &= 0x0f;
|
||||
pinfo->brg = 1;
|
||||
|
||||
cpm2_unmap(cpmux);
|
||||
cpm2_unmap(io);
|
||||
}
|
||||
|
||||
void smc2_lineif(struct uart_cpm_port *pinfo)
|
||||
{
|
||||
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
|
||||
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
|
||||
|
||||
/* SMC2 is only on port A */
|
||||
io->iop_ppara |= 0x00c00000;
|
||||
io->iop_pdira |= 0x00400000;
|
||||
io->iop_pdira &= ~0x00800000;
|
||||
io->iop_psora &= ~0x00c00000;
|
||||
|
||||
/* Wire BRG2 to SMC2 */
|
||||
cpmux->cmx_smr &= 0xf0;
|
||||
pinfo->brg = 2;
|
||||
|
||||
cpm2_unmap(cpmux);
|
||||
cpm2_unmap(io);
|
||||
}
|
||||
|
||||
void scc1_lineif(struct uart_cpm_port *pinfo)
|
||||
{
|
||||
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
|
||||
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
|
||||
|
||||
/* Use Port D for SCC1 instead of other functions. */
|
||||
io->iop_ppard |= 0x00000003;
|
||||
io->iop_psord &= ~0x00000001; /* Rx */
|
||||
io->iop_psord |= 0x00000002; /* Tx */
|
||||
io->iop_pdird &= ~0x00000001; /* Rx */
|
||||
io->iop_pdird |= 0x00000002; /* Tx */
|
||||
|
||||
/* Wire BRG1 to SCC1 */
|
||||
cpmux->cmx_scr &= 0x00ffffff;
|
||||
cpmux->cmx_scr |= 0x00000000;
|
||||
pinfo->brg = 1;
|
||||
|
||||
cpm2_unmap(cpmux);
|
||||
cpm2_unmap(io);
|
||||
}
|
||||
|
||||
void scc2_lineif(struct uart_cpm_port *pinfo)
|
||||
{
|
||||
/*
|
||||
* STx GP3 uses the SCC2 secondary option pin assignment
|
||||
* which this driver doesn't account for in the static
|
||||
* pin assignments. This kind of board specific info
|
||||
* really has to get out of the driver so boards can
|
||||
* be supported in a sane fashion.
|
||||
*/
|
||||
#ifndef CONFIG_STX_GP3
|
||||
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
|
||||
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
|
||||
|
||||
io->iop_pparb |= 0x008b0000;
|
||||
io->iop_pdirb |= 0x00880000;
|
||||
io->iop_psorb |= 0x00880000;
|
||||
io->iop_pdirb &= ~0x00030000;
|
||||
io->iop_psorb &= ~0x00030000;
|
||||
#endif
|
||||
cpmux->cmx_scr &= 0xff00ffff;
|
||||
cpmux->cmx_scr |= 0x00090000;
|
||||
pinfo->brg = 2;
|
||||
|
||||
cpm2_unmap(cpmux);
|
||||
cpm2_unmap(io);
|
||||
}
|
||||
|
||||
void scc3_lineif(struct uart_cpm_port *pinfo)
|
||||
{
|
||||
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
|
||||
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
|
||||
|
||||
io->iop_pparb |= 0x008b0000;
|
||||
io->iop_pdirb |= 0x00880000;
|
||||
io->iop_psorb |= 0x00880000;
|
||||
io->iop_pdirb &= ~0x00030000;
|
||||
io->iop_psorb &= ~0x00030000;
|
||||
cpmux->cmx_scr &= 0xffff00ff;
|
||||
cpmux->cmx_scr |= 0x00001200;
|
||||
pinfo->brg = 3;
|
||||
|
||||
cpm2_unmap(cpmux);
|
||||
cpm2_unmap(io);
|
||||
}
|
||||
|
||||
void scc4_lineif(struct uart_cpm_port *pinfo)
|
||||
{
|
||||
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
|
||||
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
|
||||
|
||||
io->iop_ppard |= 0x00000600;
|
||||
io->iop_psord &= ~0x00000600; /* Tx/Rx */
|
||||
io->iop_pdird &= ~0x00000200; /* Rx */
|
||||
io->iop_pdird |= 0x00000400; /* Tx */
|
||||
|
||||
cpmux->cmx_scr &= 0xffffff00;
|
||||
cpmux->cmx_scr |= 0x0000001b;
|
||||
pinfo->brg = 4;
|
||||
|
||||
cpm2_unmap(cpmux);
|
||||
cpm2_unmap(io);
|
||||
}
|
||||
|
||||
/*
|
||||
* Allocate DP-Ram and memory buffers. We need to allocate a transmit and
|
||||
* receive buffer descriptors from dual port ram, and a character
|
||||
* buffer area from host mem. If we are allocating for the console we need
|
||||
* to do it from bootmem
|
||||
*/
|
||||
int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
|
||||
{
|
||||
int dpmemsz, memsz;
|
||||
u8 *dp_mem;
|
||||
uint dp_offset;
|
||||
u8 *mem_addr;
|
||||
dma_addr_t dma_addr = 0;
|
||||
|
||||
pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
|
||||
|
||||
dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
|
||||
dp_offset = cpm_dpalloc(dpmemsz, 8);
|
||||
if (IS_DPERR(dp_offset)) {
|
||||
printk(KERN_ERR
|
||||
"cpm_uart_cpm.c: could not allocate buffer descriptors\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dp_mem = cpm_dpram_addr(dp_offset);
|
||||
|
||||
memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
|
||||
L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
|
||||
if (is_con) {
|
||||
mem_addr = alloc_bootmem(memsz);
|
||||
dma_addr = virt_to_bus(mem_addr);
|
||||
}
|
||||
else
|
||||
mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
|
||||
GFP_KERNEL);
|
||||
|
||||
if (mem_addr == NULL) {
|
||||
cpm_dpfree(dp_offset);
|
||||
printk(KERN_ERR
|
||||
"cpm_uart_cpm.c: could not allocate coherent memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pinfo->dp_addr = dp_offset;
|
||||
pinfo->mem_addr = mem_addr;
|
||||
pinfo->dma_addr = dma_addr;
|
||||
pinfo->mem_size = memsz;
|
||||
|
||||
pinfo->rx_buf = mem_addr;
|
||||
pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
|
||||
* pinfo->rx_fifosize);
|
||||
|
||||
pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
|
||||
pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
|
||||
{
|
||||
dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
|
||||
pinfo->rx_fifosize) +
|
||||
L1_CACHE_ALIGN(pinfo->tx_nrfifos *
|
||||
pinfo->tx_fifosize), pinfo->mem_addr,
|
||||
pinfo->dma_addr);
|
||||
|
||||
cpm_dpfree(pinfo->dp_addr);
|
||||
}
|
||||
|
||||
/* Setup any dynamic params in the uart desc */
|
||||
int __init cpm_uart_init_portdesc(void)
|
||||
{
|
||||
#if defined(CONFIG_SERIAL_CPM_SMC1) || defined(CONFIG_SERIAL_CPM_SMC2)
|
||||
u16 *addr;
|
||||
#endif
|
||||
pr_debug("CPM uart[-]:init portdesc\n");
|
||||
|
||||
cpm_uart_nr = 0;
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC1
|
||||
cpm_uart_ports[UART_SMC1].smcp = (smc_t *) cpm2_map(im_smc[0]);
|
||||
cpm_uart_ports[UART_SMC1].port.mapbase =
|
||||
(unsigned long)cpm_uart_ports[UART_SMC1].smcp;
|
||||
|
||||
cpm_uart_ports[UART_SMC1].smcup =
|
||||
(smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC1], PROFF_SMC_SIZE);
|
||||
addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC1_BASE], 2);
|
||||
*addr = PROFF_SMC1;
|
||||
cpm2_unmap(addr);
|
||||
|
||||
cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
|
||||
cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
|
||||
cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC2
|
||||
cpm_uart_ports[UART_SMC2].smcp = (smc_t *) cpm2_map(im_smc[1]);
|
||||
cpm_uart_ports[UART_SMC2].port.mapbase =
|
||||
(unsigned long)cpm_uart_ports[UART_SMC2].smcp;
|
||||
|
||||
cpm_uart_ports[UART_SMC2].smcup =
|
||||
(smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC2], PROFF_SMC_SIZE);
|
||||
addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC2_BASE], 2);
|
||||
*addr = PROFF_SMC2;
|
||||
cpm2_unmap(addr);
|
||||
|
||||
cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
|
||||
cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
|
||||
cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC1
|
||||
cpm_uart_ports[UART_SCC1].sccp = (scc_t *) cpm2_map(im_scc[0]);
|
||||
cpm_uart_ports[UART_SCC1].port.mapbase =
|
||||
(unsigned long)cpm_uart_ports[UART_SCC1].sccp;
|
||||
cpm_uart_ports[UART_SCC1].sccup =
|
||||
(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC1], PROFF_SCC_SIZE);
|
||||
|
||||
cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
|
||||
~(UART_SCCM_TX | UART_SCCM_RX);
|
||||
cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC2
|
||||
cpm_uart_ports[UART_SCC2].sccp = (scc_t *) cpm2_map(im_scc[1]);
|
||||
cpm_uart_ports[UART_SCC2].port.mapbase =
|
||||
(unsigned long)cpm_uart_ports[UART_SCC2].sccp;
|
||||
cpm_uart_ports[UART_SCC2].sccup =
|
||||
(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC2], PROFF_SCC_SIZE);
|
||||
|
||||
cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
|
||||
~(UART_SCCM_TX | UART_SCCM_RX);
|
||||
cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC3
|
||||
cpm_uart_ports[UART_SCC3].sccp = (scc_t *) cpm2_map(im_scc[2]);
|
||||
cpm_uart_ports[UART_SCC3].port.mapbase =
|
||||
(unsigned long)cpm_uart_ports[UART_SCC3].sccp;
|
||||
cpm_uart_ports[UART_SCC3].sccup =
|
||||
(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC3], PROFF_SCC_SIZE);
|
||||
|
||||
cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
|
||||
~(UART_SCCM_TX | UART_SCCM_RX);
|
||||
cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC4
|
||||
cpm_uart_ports[UART_SCC4].sccp = (scc_t *) cpm2_map(im_scc[3]);
|
||||
cpm_uart_ports[UART_SCC4].port.mapbase =
|
||||
(unsigned long)cpm_uart_ports[UART_SCC4].sccp;
|
||||
cpm_uart_ports[UART_SCC4].sccup =
|
||||
(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC4], PROFF_SCC_SIZE);
|
||||
|
||||
cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
|
||||
~(UART_SCCM_TX | UART_SCCM_RX);
|
||||
cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
|
||||
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
42
drivers/serial/cpm_uart/cpm_uart_cpm2.h
Normal file
42
drivers/serial/cpm_uart/cpm_uart_cpm2.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* linux/drivers/serial/cpm_uart/cpm_uart_cpm2.h
|
||||
*
|
||||
* Driver for CPM (SCC/SMC) serial ports
|
||||
*
|
||||
* definitions for cpm2
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef CPM_UART_CPM2_H
|
||||
#define CPM_UART_CPM2_H
|
||||
|
||||
#include <asm/cpm2.h>
|
||||
|
||||
/* defines for IRQs */
|
||||
#define SMC1_IRQ SIU_INT_SMC1
|
||||
#define SMC2_IRQ SIU_INT_SMC2
|
||||
#define SCC1_IRQ SIU_INT_SCC1
|
||||
#define SCC2_IRQ SIU_INT_SCC2
|
||||
#define SCC3_IRQ SIU_INT_SCC3
|
||||
#define SCC4_IRQ SIU_INT_SCC4
|
||||
|
||||
static inline void cpm_set_brg(int brg, int baud)
|
||||
{
|
||||
cpm_setbrg(brg, baud);
|
||||
}
|
||||
|
||||
static inline void cpm_set_scc_fcr(volatile scc_uart_t * sup)
|
||||
{
|
||||
sup->scc_genscc.scc_rfcr = CPMFCR_GBL | CPMFCR_EB;
|
||||
sup->scc_genscc.scc_tfcr = CPMFCR_GBL | CPMFCR_EB;
|
||||
}
|
||||
|
||||
static inline void cpm_set_smc_fcr(volatile smc_uart_t * up)
|
||||
{
|
||||
up->smc_rfcr = CPMFCR_GBL | CPMFCR_EB;
|
||||
up->smc_tfcr = CPMFCR_GBL | CPMFCR_EB;
|
||||
}
|
||||
|
||||
#define DPRAM_BASE ((unsigned char *)cpm_dpram_addr(0))
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user