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Creation of Cybook 2416 (actually Gen4) repository

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This commit is contained in:
mlt
2009-12-18 17:10:00 +00:00
committed by godzil
commit 76f20f4d40
13791 changed files with 6812321 additions and 0 deletions
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59
drivers/video/geode/Kconfig Normal file
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#
# Geode family framebuffer configuration
#
config FB_GEODE
bool "AMD Geode family framebuffer support (EXPERIMENTAL)"
depends on FB && PCI && EXPERIMENTAL && X86
---help---
Say 'Y' here to allow you to select framebuffer drivers for
the AMD Geode family of processors.
config FB_GEODE_GX
tristate "AMD Geode GX framebuffer support (EXPERIMENTAL)"
depends on FB && FB_GEODE && EXPERIMENTAL
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Framebuffer driver for the display controller integrated into the
AMD Geode GX processors.
To compile this driver as a module, choose M here: the module will be
called gxfb.
If unsure, say N.
config FB_GEODE_GX_SET_FBSIZE
bool "Manually specify the Geode GX framebuffer size"
depends on FB_GEODE_GX
default n
---help---
If you want to manually specify the size of your GX framebuffer,
say Y here, otherwise say N to dynamically probe it.
Say N unless you know what you are doing.
config FB_GEODE_GX_FBSIZE
hex "Size of the GX framebuffer, in bytes"
depends on FB_GEODE_GX_SET_FBSIZE
default "0x1600000"
---help---
Specify the size of the GX framebuffer. Normally, you will
want this to be MB aligned. Common values are 0x80000 (8MB)
and 0x1600000 (16MB). Don't change this unless you know what
you are doing
config FB_GEODE_GX1
tristate "AMD Geode GX1 framebuffer support (EXPERIMENTAL)"
depends on FB && FB_GEODE && EXPERIMENTAL
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Framebuffer driver for the display controller integrated into the
AMD Geode GX1 processor.
To compile this driver as a module, choose M here: the module will be
called gx1fb.
If unsure, say N.

7
drivers/video/geode/Makefile Normal file
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# Makefile for the Geode family framebuffer drivers
obj-$(CONFIG_FB_GEODE_GX1) += gx1fb.o
obj-$(CONFIG_FB_GEODE_GX) += gxfb.o
gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o
gxfb-objs := gxfb_core.o display_gx.o video_gx.o

173
drivers/video/geode/display_gx.c Normal file
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/*
* Geode GX display controller.
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* Portions from AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by * the
* Free Software Foundation; either version 2 of the License, or * (at your
* option) any later version.
*/
#include <linux/spinlock.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/div64.h>
#include <asm/delay.h>
#include "geodefb.h"
#include "display_gx.h"
#ifdef CONFIG_FB_GEODE_GX_SET_FBSIZE
unsigned int gx_frame_buffer_size(void)
{
return CONFIG_FB_GEODE_GX_FBSIZE;
}
#else
unsigned int gx_frame_buffer_size(void)
{
unsigned int val;
/* FB size is reported by a virtual register */
/* Virtual register class = 0x02 */
/* VG_MEM_SIZE(512Kb units) = 0x00 */
outw(0xFC53, 0xAC1C);
outw(0x0200, 0xAC1C);
val = (unsigned int)(inw(0xAC1E)) & 0xFFl;
return (val << 19);
}
#endif
int gx_line_delta(int xres, int bpp)
{
/* Must be a multiple of 8 bytes. */
return (xres * (bpp >> 3) + 7) & ~0x7;
}
static void gx_set_mode(struct fb_info *info)
{
struct geodefb_par *par = info->par;
u32 gcfg, dcfg;
int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
/* Unlock the display controller registers. */
readl(par->dc_regs + DC_UNLOCK);
writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
dcfg = readl(par->dc_regs + DC_DISPLAY_CFG);
/* Disable the timing generator. */
dcfg &= ~(DC_DCFG_TGEN);
writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
/* Wait for pending memory requests before disabling the FIFO load. */
udelay(100);
/* Disable FIFO load and compression. */
gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
/* Setup DCLK and its divisor. */
par->vid_ops->set_dclk(info);
/*
* Setup new mode.
*/
/* Clear all unused feature bits. */
gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE;
dcfg = 0;
/* Set FIFO priority (default 6/5) and enable. */
/* FIXME: increase fifo priority for 1280x1024 and higher modes? */
gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
/* Framebuffer start offset. */
writel(0, par->dc_regs + DC_FB_ST_OFFSET);
/* Line delta and line buffer length. */
writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH);
writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
par->dc_regs + DC_LINE_SIZE);
/* Enable graphics and video data and unmask address lines. */
dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M;
/* Set pixel format. */
switch (info->var.bits_per_pixel) {
case 8:
dcfg |= DC_DCFG_DISP_MODE_8BPP;
break;
case 16:
dcfg |= DC_DCFG_DISP_MODE_16BPP;
dcfg |= DC_DCFG_16BPP_MODE_565;
break;
case 32:
dcfg |= DC_DCFG_DISP_MODE_24BPP;
dcfg |= DC_DCFG_PALB;
break;
}
/* Enable timing generator. */
dcfg |= DC_DCFG_TGEN;
/* Horizontal and vertical timings. */
hactive = info->var.xres;
hblankstart = hactive;
hsyncstart = hblankstart + info->var.right_margin;
hsyncend = hsyncstart + info->var.hsync_len;
hblankend = hsyncend + info->var.left_margin;
htotal = hblankend;
vactive = info->var.yres;
vblankstart = vactive;
vsyncstart = vblankstart + info->var.lower_margin;
vsyncend = vsyncstart + info->var.vsync_len;
vblankend = vsyncend + info->var.upper_margin;
vtotal = vblankend;
writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING);
writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING);
writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING);
writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING);
writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING);
writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING);
/* Write final register values. */
writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
par->vid_ops->configure_display(info);
/* Relock display controller registers */
writel(0, par->dc_regs + DC_UNLOCK);
}
static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
unsigned red, unsigned green, unsigned blue)
{
struct geodefb_par *par = info->par;
int val;
/* Hardware palette is in RGB 8-8-8 format. */
val = (red << 8) & 0xff0000;
val |= (green) & 0x00ff00;
val |= (blue >> 8) & 0x0000ff;
writel(regno, par->dc_regs + DC_PAL_ADDRESS);
writel(val, par->dc_regs + DC_PAL_DATA);
}
struct geode_dc_ops gx_dc_ops = {
.set_mode = gx_set_mode,
.set_palette_reg = gx_set_hw_palette_reg,
};

101
drivers/video/geode/display_gx.h Normal file
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/*
* Geode GX display controller
*
* Copyright (C) 2006 Arcom Control Systems Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DISPLAY_GX_H__
#define __DISPLAY_GX_H__
unsigned int gx_frame_buffer_size(void);
int gx_line_delta(int xres, int bpp);
extern struct geode_dc_ops gx_dc_ops;
/* MSR that tells us if a TFT or CRT is attached */
#define GLD_MSR_CONFIG 0xC0002001
#define GLD_MSR_CONFIG_DM_FP 0x40
/* Display controller registers */
#define DC_UNLOCK 0x00
# define DC_UNLOCK_CODE 0x00004758
#define DC_GENERAL_CFG 0x04
# define DC_GCFG_DFLE 0x00000001
# define DC_GCFG_CURE 0x00000002
# define DC_GCFG_ICNE 0x00000004
# define DC_GCFG_VIDE 0x00000008
# define DC_GCFG_CMPE 0x00000020
# define DC_GCFG_DECE 0x00000040
# define DC_GCFG_VGAE 0x00000080
# define DC_GCFG_DFHPSL_MASK 0x00000F00
# define DC_GCFG_DFHPSL_POS 8
# define DC_GCFG_DFHPEL_MASK 0x0000F000
# define DC_GCFG_DFHPEL_POS 12
# define DC_GCFG_STFM 0x00010000
# define DC_GCFG_FDTY 0x00020000
# define DC_GCFG_VGAFT 0x00040000
# define DC_GCFG_VDSE 0x00080000
# define DC_GCFG_YUVM 0x00100000
# define DC_GCFG_VFSL 0x00800000
# define DC_GCFG_SIGE 0x01000000
# define DC_GCFG_SGRE 0x02000000
# define DC_GCFG_SGFR 0x04000000
# define DC_GCFG_CRC_MODE 0x08000000
# define DC_GCFG_DIAG 0x10000000
# define DC_GCFG_CFRW 0x20000000
#define DC_DISPLAY_CFG 0x08
# define DC_DCFG_TGEN 0x00000001
# define DC_DCFG_GDEN 0x00000008
# define DC_DCFG_VDEN 0x00000010
# define DC_DCFG_TRUP 0x00000040
# define DC_DCFG_DISP_MODE_MASK 0x00000300
# define DC_DCFG_DISP_MODE_8BPP 0x00000000
# define DC_DCFG_DISP_MODE_16BPP 0x00000100
# define DC_DCFG_DISP_MODE_24BPP 0x00000200
# define DC_DCFG_16BPP_MODE_MASK 0x00000c00
# define DC_DCFG_16BPP_MODE_565 0x00000000
# define DC_DCFG_16BPP_MODE_555 0x00000100
# define DC_DCFG_16BPP_MODE_444 0x00000200
# define DC_DCFG_DCEN 0x00080000
# define DC_DCFG_PALB 0x02000000
# define DC_DCFG_FRLK 0x04000000
# define DC_DCFG_VISL 0x08000000
# define DC_DCFG_FRSL 0x20000000
# define DC_DCFG_A18M 0x40000000
# define DC_DCFG_A20M 0x80000000
#define DC_FB_ST_OFFSET 0x10
#define DC_LINE_SIZE 0x30
# define DC_LINE_SIZE_FB_LINE_SIZE_MASK 0x000007ff
# define DC_LINE_SIZE_FB_LINE_SIZE_POS 0
# define DC_LINE_SIZE_CB_LINE_SIZE_MASK 0x007f0000
# define DC_LINE_SIZE_CB_LINE_SIZE_POS 16
# define DC_LINE_SIZE_VID_LINE_SIZE_MASK 0xff000000
# define DC_LINE_SIZE_VID_LINE_SIZE_POS 24
#define DC_GFX_PITCH 0x34
# define DC_GFX_PITCH_FB_PITCH_MASK 0x0000ffff
# define DC_GFX_PITCH_FB_PITCH_POS 0
# define DC_GFX_PITCH_CB_PITCH_MASK 0xffff0000
# define DC_GFX_PITCH_CB_PITCH_POS 16
#define DC_H_ACTIVE_TIMING 0x40
#define DC_H_BLANK_TIMING 0x44
#define DC_H_SYNC_TIMING 0x48
#define DC_V_ACTIVE_TIMING 0x50
#define DC_V_BLANK_TIMING 0x54
#define DC_V_SYNC_TIMING 0x58
#define DC_PAL_ADDRESS 0x70
#define DC_PAL_DATA 0x74
#define DC_GLIU0_MEM_OFFSET 0x84
#endif /* !__DISPLAY_GX1_H__ */

214
drivers/video/geode/display_gx1.c Normal file
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/*
* drivers/video/geode/display_gx1.c
* -- Geode GX1 display controller
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* Based on AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/spinlock.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/div64.h>
#include <asm/delay.h>
#include "geodefb.h"
#include "display_gx1.h"
static DEFINE_SPINLOCK(gx1_conf_reg_lock);
static u8 gx1_read_conf_reg(u8 reg)
{
u8 val, ccr3;
unsigned long flags;
spin_lock_irqsave(&gx1_conf_reg_lock, flags);
outb(CONFIG_CCR3, 0x22);
ccr3 = inb(0x23);
outb(CONFIG_CCR3, 0x22);
outb(ccr3 | CONFIG_CCR3_MAPEN, 0x23);
outb(reg, 0x22);
val = inb(0x23);
outb(CONFIG_CCR3, 0x22);
outb(ccr3, 0x23);
spin_unlock_irqrestore(&gx1_conf_reg_lock, flags);
return val;
}
unsigned gx1_gx_base(void)
{
return (gx1_read_conf_reg(CONFIG_GCR) & 0x03) << 30;
}
int gx1_frame_buffer_size(void)
{
void __iomem *mc_regs;
u32 bank_cfg;
int d;
unsigned dram_size = 0, fb_base;
mc_regs = ioremap(gx1_gx_base() + 0x8400, 0x100);
if (!mc_regs)
return -ENOMEM;
/* Calculate the total size of both DIMM0 and DIMM1. */
bank_cfg = readl(mc_regs + MC_BANK_CFG);
for (d = 0; d < 2; d++) {
if ((bank_cfg & MC_BCFG_DIMM0_PG_SZ_MASK) != MC_BCFG_DIMM0_PG_SZ_NO_DIMM)
dram_size += 0x400000 << ((bank_cfg & MC_BCFG_DIMM0_SZ_MASK) >> 8);
bank_cfg >>= 16; /* look at DIMM1 next */
}
fb_base = (readl(mc_regs + MC_GBASE_ADD) & MC_GADD_GBADD_MASK) << 19;
iounmap(mc_regs);
return dram_size - fb_base;
}
static void gx1_set_mode(struct fb_info *info)
{
struct geodefb_par *par = info->par;
u32 gcfg, tcfg, ocfg, dclk_div, val;
int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
/* Unlock the display controller registers. */
readl(par->dc_regs + DC_UNLOCK);
writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
tcfg = readl(par->dc_regs + DC_TIMING_CFG);
/* Blank the display and disable the timing generator. */
tcfg &= ~(DC_TCFG_BLKE | DC_TCFG_TGEN);
writel(tcfg, par->dc_regs + DC_TIMING_CFG);
/* Wait for pending memory requests before disabling the FIFO load. */
udelay(100);
/* Disable FIFO load and compression. */
gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
/* Setup DCLK and its divisor. */
gcfg &= ~DC_GCFG_DCLK_MASK;
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
par->vid_ops->set_dclk(info);
dclk_div = DC_GCFG_DCLK_DIV_1; /* FIXME: may need to divide DCLK by 2 sometimes? */
gcfg |= dclk_div;
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
/* Wait for the clock generatation to settle. This is needed since
* some of the register writes that follow require that clock to be
* present. */
udelay(1000); /* FIXME: seems a little long */
/*
* Setup new mode.
*/
/* Clear all unused feature bits. */
gcfg = DC_GCFG_VRDY | dclk_div;
/* Set FIFO priority (default 6/5) and enable. */
/* FIXME: increase fifo priority for 1280x1024 modes? */
gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
/* FIXME: Set pixel and line double bits if necessary. */
/* Framebuffer start offset. */
writel(0, par->dc_regs + DC_FB_ST_OFFSET);
/* Line delta and line buffer length. */
writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);
writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
par->dc_regs + DC_BUF_SIZE);
/* Output configuration. Enable panel data, set pixel format. */
ocfg = DC_OCFG_PCKE | DC_OCFG_PDEL | DC_OCFG_PDEH;
if (info->var.bits_per_pixel == 8) ocfg |= DC_OCFG_8BPP;
/* Enable timing generator, sync and FP data. */
tcfg = DC_TCFG_FPPE | DC_TCFG_HSYE | DC_TCFG_VSYE | DC_TCFG_BLKE
| DC_TCFG_TGEN;
/* Horizontal and vertical timings. */
hactive = info->var.xres;
hblankstart = hactive;
hsyncstart = hblankstart + info->var.right_margin;
hsyncend = hsyncstart + info->var.hsync_len;
hblankend = hsyncend + info->var.left_margin;
htotal = hblankend;
vactive = info->var.yres;
vblankstart = vactive;
vsyncstart = vblankstart + info->var.lower_margin;
vsyncend = vsyncstart + info->var.vsync_len;
vblankend = vsyncend + info->var.upper_margin;
vtotal = vblankend;
val = (hactive - 1) | ((htotal - 1) << 16);
writel(val, par->dc_regs + DC_H_TIMING_1);
val = (hblankstart - 1) | ((hblankend - 1) << 16);
writel(val, par->dc_regs + DC_H_TIMING_2);
val = (hsyncstart - 1) | ((hsyncend - 1) << 16);
writel(val, par->dc_regs + DC_H_TIMING_3);
writel(val, par->dc_regs + DC_FP_H_TIMING);
val = (vactive - 1) | ((vtotal - 1) << 16);
writel(val, par->dc_regs + DC_V_TIMING_1);
val = (vblankstart - 1) | ((vblankend - 1) << 16);
writel(val, par->dc_regs + DC_V_TIMING_2);
val = (vsyncstart - 1) | ((vsyncend - 1) << 16);
writel(val, par->dc_regs + DC_V_TIMING_3);
val = (vsyncstart - 2) | ((vsyncend - 2) << 16);
writel(val, par->dc_regs + DC_FP_V_TIMING);
/* Write final register values. */
writel(ocfg, par->dc_regs + DC_OUTPUT_CFG);
writel(tcfg, par->dc_regs + DC_TIMING_CFG);
udelay(1000); /* delay after TIMING_CFG. FIXME: perhaps a little long */
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
par->vid_ops->configure_display(info);
/* Relock display controller registers */
writel(0, par->dc_regs + DC_UNLOCK);
/* FIXME: write line_length and bpp to Graphics Pipeline GP_BLT_STATUS
* register. */
}
static void gx1_set_hw_palette_reg(struct fb_info *info, unsigned regno,
unsigned red, unsigned green, unsigned blue)
{
struct geodefb_par *par = info->par;
int val;
/* Hardware palette is in RGB 6-6-6 format. */
val = (red << 2) & 0x3f000;
val |= (green >> 4) & 0x00fc0;
val |= (blue >> 10) & 0x0003f;
writel(regno, par->dc_regs + DC_PAL_ADDRESS);
writel(val, par->dc_regs + DC_PAL_DATA);
}
struct geode_dc_ops gx1_dc_ops = {
.set_mode = gx1_set_mode,
.set_palette_reg = gx1_set_hw_palette_reg,
};

154
drivers/video/geode/display_gx1.h Normal file
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/*
* drivers/video/geode/display_gx1.h
* -- Geode GX1 display controller
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* Based on AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DISPLAY_GX1_H__
#define __DISPLAY_GX1_H__
unsigned gx1_gx_base(void);
int gx1_frame_buffer_size(void);
extern struct geode_dc_ops gx1_dc_ops;
/* GX1 configuration I/O registers */
#define CONFIG_CCR3 0xc3
# define CONFIG_CCR3_MAPEN 0x10
#define CONFIG_GCR 0xb8
/* Memory controller registers */
#define MC_BANK_CFG 0x08
# define MC_BCFG_DIMM0_SZ_MASK 0x00000700
# define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070
# define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070
#define MC_GBASE_ADD 0x14
# define MC_GADD_GBADD_MASK 0x000003ff
/* Display controller registers */
#define DC_PAL_ADDRESS 0x70
#define DC_PAL_DATA 0x74
#define DC_UNLOCK 0x00
# define DC_UNLOCK_CODE 0x00004758
#define DC_GENERAL_CFG 0x04
# define DC_GCFG_DFLE 0x00000001
# define DC_GCFG_CURE 0x00000002
# define DC_GCFG_VCLK_DIV 0x00000004
# define DC_GCFG_PLNO 0x00000004
# define DC_GCFG_PPC 0x00000008
# define DC_GCFG_CMPE 0x00000010
# define DC_GCFG_DECE 0x00000020
# define DC_GCFG_DCLK_MASK 0x000000C0
# define DC_GCFG_DCLK_DIV_1 0x00000080
# define DC_GCFG_DFHPSL_MASK 0x00000F00
# define DC_GCFG_DFHPSL_POS 8
# define DC_GCFG_DFHPEL_MASK 0x0000F000
# define DC_GCFG_DFHPEL_POS 12
# define DC_GCFG_CIM_MASK 0x00030000
# define DC_GCFG_CIM_POS 16
# define DC_GCFG_FDTY 0x00040000
# define DC_GCFG_RTPM 0x00080000
# define DC_GCFG_DAC_RS_MASK 0x00700000
# define DC_GCFG_DAC_RS_POS 20
# define DC_GCFG_CKWR 0x00800000
# define DC_GCFG_LDBL 0x01000000
# define DC_GCFG_DIAG 0x02000000
# define DC_GCFG_CH4S 0x04000000
# define DC_GCFG_SSLC 0x08000000
# define DC_GCFG_VIDE 0x10000000
# define DC_GCFG_VRDY 0x20000000
# define DC_GCFG_DPCK 0x40000000
# define DC_GCFG_DDCK 0x80000000
#define DC_TIMING_CFG 0x08
# define DC_TCFG_FPPE 0x00000001
# define DC_TCFG_HSYE 0x00000002
# define DC_TCFG_VSYE 0x00000004
# define DC_TCFG_BLKE 0x00000008
# define DC_TCFG_DDCK 0x00000010
# define DC_TCFG_TGEN 0x00000020
# define DC_TCFG_VIEN 0x00000040
# define DC_TCFG_BLNK 0x00000080
# define DC_TCFG_CHSP 0x00000100
# define DC_TCFG_CVSP 0x00000200
# define DC_TCFG_FHSP 0x00000400
# define DC_TCFG_FVSP 0x00000800
# define DC_TCFG_FCEN 0x00001000
# define DC_TCFG_CDCE 0x00002000
# define DC_TCFG_PLNR 0x00002000
# define DC_TCFG_INTL 0x00004000
# define DC_TCFG_PXDB 0x00008000
# define DC_TCFG_BKRT 0x00010000
# define DC_TCFG_PSD_MASK 0x000E0000
# define DC_TCFG_PSD_POS 17
# define DC_TCFG_DDCI 0x08000000
# define DC_TCFG_SENS 0x10000000
# define DC_TCFG_DNA 0x20000000
# define DC_TCFG_VNA 0x40000000
# define DC_TCFG_VINT 0x80000000
#define DC_OUTPUT_CFG 0x0C
# define DC_OCFG_8BPP 0x00000001
# define DC_OCFG_555 0x00000002
# define DC_OCFG_PCKE 0x00000004
# define DC_OCFG_FRME 0x00000008
# define DC_OCFG_DITE 0x00000010
# define DC_OCFG_2PXE 0x00000020
# define DC_OCFG_2XCK 0x00000040
# define DC_OCFG_2IND 0x00000080
# define DC_OCFG_34ADD 0x00000100
# define DC_OCFG_FRMS 0x00000200
# define DC_OCFG_CKSL 0x00000400
# define DC_OCFG_PRMP 0x00000800
# define DC_OCFG_PDEL 0x00001000
# define DC_OCFG_PDEH 0x00002000
# define DC_OCFG_CFRW 0x00004000
# define DC_OCFG_DIAG 0x00008000
#define DC_FB_ST_OFFSET 0x10
#define DC_CB_ST_OFFSET 0x14
#define DC_CURS_ST_OFFSET 0x18
#define DC_ICON_ST_OFFSET 0x1C
#define DC_VID_ST_OFFSET 0x20
#define DC_LINE_DELTA 0x24
#define DC_BUF_SIZE 0x28
#define DC_H_TIMING_1 0x30
#define DC_H_TIMING_2 0x34
#define DC_H_TIMING_3 0x38
#define DC_FP_H_TIMING 0x3C
#define DC_V_TIMING_1 0x40
#define DC_V_TIMING_2 0x44
#define DC_V_TIMING_3 0x48
#define DC_FP_V_TIMING 0x4C
#define DC_CURSOR_X 0x50
#define DC_ICON_X 0x54
#define DC_V_LINE_CNT 0x54
#define DC_CURSOR_Y 0x58
#define DC_ICON_Y 0x5C
#define DC_SS_LINE_CMP 0x5C
#define DC_CURSOR_COLOR 0x60
#define DC_ICON_COLOR 0x64
#define DC_BORDER_COLOR 0x68
#define DC_PAL_ADDRESS 0x70
#define DC_PAL_DATA 0x74
#define DC_DFIFO_DIAG 0x78
#define DC_CFIFO_DIAG 0x7C
#endif /* !__DISPLAY_GX1_H__ */

38
drivers/video/geode/geodefb.h Normal file
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/*
* drivers/video/geode/geodefb.h
* -- Geode framebuffer driver
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __GEODEFB_H__
#define __GEODEFB_H__
struct geodefb_info;
struct geode_dc_ops {
void (*set_mode)(struct fb_info *);
void (*set_palette_reg)(struct fb_info *, unsigned, unsigned, unsigned, unsigned);
};
struct geode_vid_ops {
void (*set_dclk)(struct fb_info *);
void (*configure_display)(struct fb_info *);
int (*blank_display)(struct fb_info *, int blank_mode);
};
struct geodefb_par {
int enable_crt;
int panel_x; /* dimensions of an attached flat panel, non-zero => enable panel */
int panel_y;
void __iomem *dc_regs;
void __iomem *vid_regs;
struct geode_dc_ops *dc_ops;
struct geode_vid_ops *vid_ops;
};
#endif /* !__GEODEFB_H__ */

474
drivers/video/geode/gx1fb_core.c Normal file
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/*
* drivers/video/geode/gx1fb_core.c
* -- Geode GX1 framebuffer driver
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include "geodefb.h"
#include "display_gx1.h"
#include "video_cs5530.h"
static char mode_option[32] = "640x480-16@60";
static int crt_option = 1;
static char panel_option[32] = "";
/* Modes relevant to the GX1 (taken from modedb.c) */
static const struct fb_videomode __initdata gx1_modedb[] = {
/* 640x480-60 VESA */
{ NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 640x480-75 VESA */
{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 640x480-85 VESA */
{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-60 VESA */
{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-75 VESA */
{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-85 VESA */
{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-60 VESA */
{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-75 VESA */
{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-85 VESA */
{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x960-60 VESA */
{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x960-85 VESA */
{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-60 VESA */
{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-75 VESA */
{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-85 VESA */
{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
};
static int gx1_line_delta(int xres, int bpp)
{
int line_delta = xres * (bpp >> 3);
if (line_delta > 2048)
line_delta = 4096;
else if (line_delta > 1024)
line_delta = 2048;
else
line_delta = 1024;
return line_delta;
}
static int gx1fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct geodefb_par *par = info->par;
/* Maximum resolution is 1280x1024. */
if (var->xres > 1280 || var->yres > 1024)
return -EINVAL;
if (par->panel_x && (var->xres > par->panel_x || var->yres > par->panel_y))
return -EINVAL;
/* Only 16 bpp and 8 bpp is supported by the hardware. */
if (var->bits_per_pixel == 16) {
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
var->transp.offset = 0; var->transp.length = 0;
} else if (var->bits_per_pixel == 8) {
var->red.offset = 0; var->red.length = 8;
var->green.offset = 0; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
} else
return -EINVAL;
/* Enough video memory? */
if (gx1_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
return -EINVAL;
/* FIXME: Check timing parameters here? */
return 0;
}
static int gx1fb_set_par(struct fb_info *info)
{
struct geodefb_par *par = info->par;
if (info->var.bits_per_pixel == 16) {
info->fix.visual = FB_VISUAL_TRUECOLOR;
fb_dealloc_cmap(&info->cmap);
} else {
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
}
info->fix.line_length = gx1_line_delta(info->var.xres, info->var.bits_per_pixel);
par->dc_ops->set_mode(info);
return 0;
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int gx1fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct geodefb_par *par = info->par;
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 *pal = info->pseudo_palette;
u32 v;
if (regno >= 16)
return -EINVAL;
v = chan_to_field(red, &info->var.red);
v |= chan_to_field(green, &info->var.green);
v |= chan_to_field(blue, &info->var.blue);
pal[regno] = v;
} else {
if (regno >= 256)
return -EINVAL;
par->dc_ops->set_palette_reg(info, regno, red, green, blue);
}
return 0;
}
static int gx1fb_blank(int blank_mode, struct fb_info *info)
{
struct geodefb_par *par = info->par;
return par->vid_ops->blank_display(info, blank_mode);
}
static int __init gx1fb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
{
struct geodefb_par *par = info->par;
unsigned gx_base;
int fb_len;
int ret;
gx_base = gx1_gx_base();
if (!gx_base)
return -ENODEV;
ret = pci_enable_device(dev);
if (ret < 0)
return ret;
ret = pci_request_region(dev, 0, "gx1fb (video)");
if (ret < 0)
return ret;
par->vid_regs = ioremap(pci_resource_start(dev, 0),
pci_resource_len(dev, 0));
if (!par->vid_regs)
return -ENOMEM;
if (!request_mem_region(gx_base + 0x8300, 0x100, "gx1fb (display controller)"))
return -EBUSY;
par->dc_regs = ioremap(gx_base + 0x8300, 0x100);
if (!par->dc_regs)
return -ENOMEM;
if ((fb_len = gx1_frame_buffer_size()) < 0)
return -ENOMEM;
info->fix.smem_start = gx_base + 0x800000;
info->fix.smem_len = fb_len;
info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
if (!info->screen_base)
return -ENOMEM;
dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
info->fix.smem_len / 1024, info->fix.smem_start);
return 0;
}
static int parse_panel_option(struct fb_info *info)
{
struct geodefb_par *par = info->par;
if (strcmp(panel_option, "") != 0) {
int x, y;
char *s;
x = simple_strtol(panel_option, &s, 10);
if (!x)
return -EINVAL;
y = simple_strtol(s + 1, NULL, 10);
if (!y)
return -EINVAL;
par->panel_x = x;
par->panel_y = y;
}
return 0;
}
static struct fb_ops gx1fb_ops = {
.owner = THIS_MODULE,
.fb_check_var = gx1fb_check_var,
.fb_set_par = gx1fb_set_par,
.fb_setcolreg = gx1fb_setcolreg,
.fb_blank = gx1fb_blank,
/* No HW acceleration for now. */
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static struct fb_info * __init gx1fb_init_fbinfo(struct device *dev)
{
struct geodefb_par *par;
struct fb_info *info;
/* Alloc enough space for the pseudo palette. */
info = framebuffer_alloc(sizeof(struct geodefb_par) + sizeof(u32) * 16, dev);
if (!info)
return NULL;
par = info->par;
strcpy(info->fix.id, "GX1");
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->var.nonstd = 0;
info->var.activate = FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.accel_flags = 0;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->fbops = &gx1fb_ops;
info->flags = FBINFO_DEFAULT;
info->node = -1;
info->pseudo_palette = (void *)par + sizeof(struct geodefb_par);
info->var.grayscale = 0;
/* CRT and panel options */
par->enable_crt = crt_option;
if (parse_panel_option(info) < 0)
printk(KERN_WARNING "gx1fb: invalid 'panel' option -- disabling flat panel\n");
if (!par->panel_x)
par->enable_crt = 1; /* fall back to CRT if no panel is specified */
return info;
}
static int __init gx1fb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct geodefb_par *par;
struct fb_info *info;
int ret;
info = gx1fb_init_fbinfo(&pdev->dev);
if (!info)
return -ENOMEM;
par = info->par;
/* GX1 display controller and CS5530 video device */
par->dc_ops = &gx1_dc_ops;
par->vid_ops = &cs5530_vid_ops;
if ((ret = gx1fb_map_video_memory(info, pdev)) < 0) {
dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
goto err;
}
ret = fb_find_mode(&info->var, info, mode_option,
gx1_modedb, ARRAY_SIZE(gx1_modedb), NULL, 16);
if (ret == 0 || ret == 4) {
dev_err(&pdev->dev, "could not find valid video mode\n");
ret = -EINVAL;
goto err;
}
/* Clear the frame buffer of garbage. */
memset_io(info->screen_base, 0, info->fix.smem_len);
gx1fb_check_var(&info->var, info);
gx1fb_set_par(info);
if (register_framebuffer(info) < 0) {
ret = -EINVAL;
goto err;
}
pci_set_drvdata(pdev, info);
printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
return 0;
err:
if (info->screen_base) {
iounmap(info->screen_base);
pci_release_region(pdev, 0);
}
if (par->vid_regs) {
iounmap(par->vid_regs);
pci_release_region(pdev, 1);
}
if (par->dc_regs) {
iounmap(par->dc_regs);
release_mem_region(gx1_gx_base() + 0x8300, 0x100);
}
if (info)
framebuffer_release(info);
return ret;
}
static void gx1fb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct geodefb_par *par = info->par;
unregister_framebuffer(info);
iounmap((void __iomem *)info->screen_base);
pci_release_region(pdev, 0);
iounmap(par->vid_regs);
pci_release_region(pdev, 1);
iounmap(par->dc_regs);
release_mem_region(gx1_gx_base() + 0x8300, 0x100);
pci_set_drvdata(pdev, NULL);
framebuffer_release(info);
}
#ifndef MODULE
static void __init gx1fb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return;
while ((this_opt = strsep(&options, ","))) {
if (!*this_opt)
continue;
if (!strncmp(this_opt, "mode:", 5))
strlcpy(mode_option, this_opt + 5, sizeof(mode_option));
else if (!strncmp(this_opt, "crt:", 4))
crt_option = !!simple_strtoul(this_opt + 4, NULL, 0);
else if (!strncmp(this_opt, "panel:", 6))
strlcpy(panel_option, this_opt + 6, sizeof(panel_option));
else
strlcpy(mode_option, this_opt, sizeof(mode_option));
}
}
#endif
static struct pci_device_id gx1fb_id_table[] = {
{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_VIDEO,
PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
0xff0000, 0 },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, gx1fb_id_table);
static struct pci_driver gx1fb_driver = {
.name = "gx1fb",
.id_table = gx1fb_id_table,
.probe = gx1fb_probe,
.remove = gx1fb_remove,
};
static int __init gx1fb_init(void)
{
#ifndef MODULE
char *option = NULL;
if (fb_get_options("gx1fb", &option))
return -ENODEV;
gx1fb_setup(option);
#endif
return pci_register_driver(&gx1fb_driver);
}
static void __exit gx1fb_cleanup(void)
{
pci_unregister_driver(&gx1fb_driver);
}
module_init(gx1fb_init);
module_exit(gx1fb_cleanup);
module_param_string(mode, mode_option, sizeof(mode_option), 0444);
MODULE_PARM_DESC(mode, "video mode (<x>x<y>[-<bpp>][@<refr>])");
module_param_named(crt, crt_option, int, 0444);
MODULE_PARM_DESC(crt, "enable CRT output. 0 = off, 1 = on (default)");
module_param_string(panel, panel_option, sizeof(panel_option), 0444);
MODULE_PARM_DESC(panel, "size of attached flat panel (<x>x<y>)");
MODULE_DESCRIPTION("framebuffer driver for the AMD Geode GX1");
MODULE_LICENSE("GPL");

460
drivers/video/geode/gxfb_core.c Normal file
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@@ -0,0 +1,460 @@
/*
* Geode GX framebuffer driver.
*
* Copyright (C) 2006 Arcom Control Systems Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*
* This driver assumes that the BIOS has created a virtual PCI device header
* for the video device. The PCI header is assumed to contain the following
* BARs:
*
* BAR0 - framebuffer memory
* BAR1 - graphics processor registers
* BAR2 - display controller registers
* BAR3 - video processor and flat panel control registers.
*
* 16 MiB of framebuffer memory is assumed to be available.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include "geodefb.h"
#include "display_gx.h"
#include "video_gx.h"
static char *mode_option;
/* Modes relevant to the GX (taken from modedb.c) */
static const struct fb_videomode gx_modedb[] __initdata = {
/* 640x480-60 VESA */
{ NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 640x480-75 VESA */
{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 640x480-85 VESA */
{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-60 VESA */
{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-75 VESA */
{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-85 VESA */
{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-60 VESA */
{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-75 VESA */
{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-85 VESA */
{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x960-60 VESA */
{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x960-85 VESA */
{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-60 VESA */
{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-75 VESA */
{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-85 VESA */
{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1600x1200-60 VESA */
{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1600x1200-75 VESA */
{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1600x1200-85 VESA */
{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
};
static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
if (var->xres > 1600 || var->yres > 1200)
return -EINVAL;
if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16)
return -EINVAL;
if (var->bits_per_pixel == 32) {
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
} else if (var->bits_per_pixel == 16) {
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
} else if (var->bits_per_pixel == 8) {
var->red.offset = 0; var->red.length = 8;
var->green.offset = 0; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
} else
return -EINVAL;
var->transp.offset = 0; var->transp.length = 0;
/* Enough video memory? */
if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
return -EINVAL;
/* FIXME: Check timing parameters here? */
return 0;
}
static int gxfb_set_par(struct fb_info *info)
{
struct geodefb_par *par = info->par;
if (info->var.bits_per_pixel > 8) {
info->fix.visual = FB_VISUAL_TRUECOLOR;
fb_dealloc_cmap(&info->cmap);
} else {
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
}
info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);
par->dc_ops->set_mode(info);
return 0;
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct geodefb_par *par = info->par;
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 *pal = info->pseudo_palette;
u32 v;
if (regno >= 16)
return -EINVAL;
v = chan_to_field(red, &info->var.red);
v |= chan_to_field(green, &info->var.green);
v |= chan_to_field(blue, &info->var.blue);
pal[regno] = v;
} else {
if (regno >= 256)
return -EINVAL;
par->dc_ops->set_palette_reg(info, regno, red, green, blue);
}
return 0;
}
static int gxfb_blank(int blank_mode, struct fb_info *info)
{
struct geodefb_par *par = info->par;
return par->vid_ops->blank_display(info, blank_mode);
}
static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
{
struct geodefb_par *par = info->par;
int fb_len;
int ret;
ret = pci_enable_device(dev);
if (ret < 0)
return ret;
ret = pci_request_region(dev, 3, "gxfb (video processor)");
if (ret < 0)
return ret;
par->vid_regs = ioremap(pci_resource_start(dev, 3),
pci_resource_len(dev, 3));
if (!par->vid_regs)
return -ENOMEM;
ret = pci_request_region(dev, 2, "gxfb (display controller)");
if (ret < 0)
return ret;
par->dc_regs = ioremap(pci_resource_start(dev, 2), pci_resource_len(dev, 2));
if (!par->dc_regs)
return -ENOMEM;
ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
if (ret < 0)
return ret;
if ((fb_len = gx_frame_buffer_size()) < 0)
return -ENOMEM;
info->fix.smem_start = pci_resource_start(dev, 0);
info->fix.smem_len = fb_len;
info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
if (!info->screen_base)
return -ENOMEM;
/* Set the 16MB aligned base address of the graphics memory region
* in the display controller */
writel(info->fix.smem_start & 0xFF000000,
par->dc_regs + DC_GLIU0_MEM_OFFSET);
dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
info->fix.smem_len / 1024, info->fix.smem_start);
return 0;
}
static struct fb_ops gxfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = gxfb_check_var,
.fb_set_par = gxfb_set_par,
.fb_setcolreg = gxfb_setcolreg,
.fb_blank = gxfb_blank,
/* No HW acceleration for now. */
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
{
struct geodefb_par *par;
struct fb_info *info;
/* Alloc enough space for the pseudo palette. */
info = framebuffer_alloc(sizeof(struct geodefb_par) + sizeof(u32) * 16, dev);
if (!info)
return NULL;
par = info->par;
strcpy(info->fix.id, "Geode GX");
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->var.nonstd = 0;
info->var.activate = FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.accel_flags = 0;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->fbops = &gxfb_ops;
info->flags = FBINFO_DEFAULT;
info->node = -1;
info->pseudo_palette = (void *)par + sizeof(struct geodefb_par);
info->var.grayscale = 0;
return info;
}
static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct geodefb_par *par;
struct fb_info *info;
int ret;
unsigned long val;
info = gxfb_init_fbinfo(&pdev->dev);
if (!info)
return -ENOMEM;
par = info->par;
/* GX display controller and GX video device. */
par->dc_ops = &gx_dc_ops;
par->vid_ops = &gx_vid_ops;
if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
goto err;
}
/* Figure out if this is a TFT or CRT part */
rdmsrl(GLD_MSR_CONFIG, val);
if ((val & GLD_MSR_CONFIG_DM_FP) == GLD_MSR_CONFIG_DM_FP)
par->enable_crt = 0;
else
par->enable_crt = 1;
ret = fb_find_mode(&info->var, info, mode_option,
gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16);
if (ret == 0 || ret == 4) {
dev_err(&pdev->dev, "could not find valid video mode\n");
ret = -EINVAL;
goto err;
}
/* Clear the frame buffer of garbage. */
memset_io(info->screen_base, 0, info->fix.smem_len);
gxfb_check_var(&info->var, info);
gxfb_set_par(info);
if (register_framebuffer(info) < 0) {
ret = -EINVAL;
goto err;
}
pci_set_drvdata(pdev, info);
printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
return 0;
err:
if (info->screen_base) {
iounmap(info->screen_base);
pci_release_region(pdev, 0);
}
if (par->vid_regs) {
iounmap(par->vid_regs);
pci_release_region(pdev, 3);
}
if (par->dc_regs) {
iounmap(par->dc_regs);
pci_release_region(pdev, 2);
}
if (info)
framebuffer_release(info);
return ret;
}
static void gxfb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct geodefb_par *par = info->par;
unregister_framebuffer(info);
iounmap((void __iomem *)info->screen_base);
pci_release_region(pdev, 0);
iounmap(par->vid_regs);
pci_release_region(pdev, 3);
iounmap(par->dc_regs);
pci_release_region(pdev, 2);
pci_set_drvdata(pdev, NULL);
framebuffer_release(info);
}
static struct pci_device_id gxfb_id_table[] = {
{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO,
PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
0xff0000, 0 },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, gxfb_id_table);
static struct pci_driver gxfb_driver = {
.name = "gxfb",
.id_table = gxfb_id_table,
.probe = gxfb_probe,
.remove = gxfb_remove,
};
#ifndef MODULE
static int __init gxfb_setup(char *options)
{
char *opt;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
mode_option = opt;
}
return 0;
}
#endif
static int __init gxfb_init(void)
{
#ifndef MODULE
char *option = NULL;
if (fb_get_options("gxfb", &option))
return -ENODEV;
gxfb_setup(option);
#endif
return pci_register_driver(&gxfb_driver);
}
static void __exit gxfb_cleanup(void)
{
pci_unregister_driver(&gxfb_driver);
}
module_init(gxfb_init);
module_exit(gxfb_cleanup);
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
MODULE_LICENSE("GPL");

193
drivers/video/geode/video_cs5530.c Normal file
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@@ -0,0 +1,193 @@
/*
* drivers/video/geode/video_cs5530.c
* -- CS5530 video device
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* Based on AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/delay.h>
#include "geodefb.h"
#include "video_cs5530.h"
/*
* CS5530 PLL table. This maps pixclocks to the appropriate PLL register
* value.
*/
struct cs5530_pll_entry {
long pixclock; /* ps */
u32 pll_value;
};
static const struct cs5530_pll_entry cs5530_pll_table[] = {
{ 39721, 0x31C45801, }, /* 25.1750 MHz */
{ 35308, 0x20E36802, }, /* 28.3220 */
{ 31746, 0x33915801, }, /* 31.5000 */
{ 27777, 0x31EC4801, }, /* 36.0000 */
{ 26666, 0x21E22801, }, /* 37.5000 */
{ 25000, 0x33088801, }, /* 40.0000 */
{ 22271, 0x33E22801, }, /* 44.9000 */
{ 20202, 0x336C4801, }, /* 49.5000 */
{ 20000, 0x23088801, }, /* 50.0000 */
{ 19860, 0x23088801, }, /* 50.3500 */
{ 18518, 0x3708A801, }, /* 54.0000 */
{ 17777, 0x23E36802, }, /* 56.2500 */
{ 17733, 0x23E36802, }, /* 56.3916 */
{ 17653, 0x23E36802, }, /* 56.6444 */
{ 16949, 0x37C45801, }, /* 59.0000 */
{ 15873, 0x23EC4801, }, /* 63.0000 */
{ 15384, 0x37911801, }, /* 65.0000 */
{ 14814, 0x37963803, }, /* 67.5000 */
{ 14124, 0x37058803, }, /* 70.8000 */
{ 13888, 0x3710C805, }, /* 72.0000 */
{ 13333, 0x37E22801, }, /* 75.0000 */
{ 12698, 0x27915801, }, /* 78.7500 */
{ 12500, 0x37D8D802, }, /* 80.0000 */
{ 11135, 0x27588802, }, /* 89.8000 */
{ 10582, 0x27EC4802, }, /* 94.5000 */
{ 10101, 0x27AC6803, }, /* 99.0000 */
{ 10000, 0x27088801, }, /* 100.0000 */
{ 9259, 0x2710C805, }, /* 108.0000 */
{ 8888, 0x27E36802, }, /* 112.5000 */
{ 7692, 0x27C58803, }, /* 130.0000 */
{ 7407, 0x27316803, }, /* 135.0000 */
{ 6349, 0x2F915801, }, /* 157.5000 */
{ 6172, 0x2F08A801, }, /* 162.0000 */
{ 5714, 0x2FB11802, }, /* 175.0000 */
{ 5291, 0x2FEC4802, }, /* 189.0000 */
{ 4950, 0x2F963803, }, /* 202.0000 */
{ 4310, 0x2FB1B802, }, /* 232.0000 */
};
static void cs5530_set_dclk_frequency(struct fb_info *info)
{
struct geodefb_par *par = info->par;
int i;
u32 value;
long min, diff;
/* Search the table for the closest pixclock. */
value = cs5530_pll_table[0].pll_value;
min = cs5530_pll_table[0].pixclock - info->var.pixclock;
if (min < 0) min = -min;
for (i = 1; i < ARRAY_SIZE(cs5530_pll_table); i++) {
diff = cs5530_pll_table[i].pixclock - info->var.pixclock;
if (diff < 0L) diff = -diff;
if (diff < min) {
min = diff;
value = cs5530_pll_table[i].pll_value;
}
}
writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG);
writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */
udelay(500); /* wait for PLL to settle */
writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */
writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */
}
static void cs5530_configure_display(struct fb_info *info)
{
struct geodefb_par *par = info->par;
u32 dcfg;
dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
/* Clear bits from existing mode. */
dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK
| CS5530_DCFG_CRT_HSYNC_POL | CS5530_DCFG_CRT_VSYNC_POL
| CS5530_DCFG_FP_PWR_EN | CS5530_DCFG_FP_DATA_EN
| CS5530_DCFG_DAC_PWR_EN | CS5530_DCFG_VSYNC_EN
| CS5530_DCFG_HSYNC_EN);
/* Set default sync skew and power sequence delays. */
dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT
| CS5530_DCFG_GV_PAL_BYP);
/* Enable DACs, hsync and vsync for CRTs */
if (par->enable_crt) {
dcfg |= CS5530_DCFG_DAC_PWR_EN;
dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN;
}
/* Enable panel power and data if using a flat panel. */
if (par->panel_x > 0) {
dcfg |= CS5530_DCFG_FP_PWR_EN;
dcfg |= CS5530_DCFG_FP_DATA_EN;
}
/* Sync polarities. */
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
dcfg |= CS5530_DCFG_CRT_HSYNC_POL;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
dcfg |= CS5530_DCFG_CRT_VSYNC_POL;
writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
}
static int cs5530_blank_display(struct fb_info *info, int blank_mode)
{
struct geodefb_par *par = info->par;
u32 dcfg;
int blank, hsync, vsync;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
blank = 0; hsync = 1; vsync = 1;
break;
case FB_BLANK_NORMAL:
blank = 1; hsync = 1; vsync = 1;
break;
case FB_BLANK_VSYNC_SUSPEND:
blank = 1; hsync = 1; vsync = 0;
break;
case FB_BLANK_HSYNC_SUSPEND:
blank = 1; hsync = 0; vsync = 1;
break;
case FB_BLANK_POWERDOWN:
blank = 1; hsync = 0; vsync = 0;
break;
default:
return -EINVAL;
}
dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
dcfg &= ~(CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN
| CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN
| CS5530_DCFG_FP_DATA_EN | CS5530_DCFG_FP_PWR_EN);
if (par->enable_crt) {
if (!blank)
dcfg |= CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN;
if (hsync)
dcfg |= CS5530_DCFG_HSYNC_EN;
if (vsync)
dcfg |= CS5530_DCFG_VSYNC_EN;
}
if (par->panel_x > 0) {
if (!blank)
dcfg |= CS5530_DCFG_FP_DATA_EN;
if (hsync && vsync)
dcfg |= CS5530_DCFG_FP_PWR_EN;
}
writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
return 0;
}
struct geode_vid_ops cs5530_vid_ops = {
.set_dclk = cs5530_set_dclk_frequency,
.configure_display = cs5530_configure_display,
.blank_display = cs5530_blank_display,
};

75
drivers/video/geode/video_cs5530.h Normal file
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@@ -0,0 +1,75 @@
/*
* drivers/video/geode/video_cs5530.h
* -- CS5530 video device
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* Based on AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __VIDEO_CS5530_H__
#define __VIDEO_CS5530_H__
extern struct geode_vid_ops cs5530_vid_ops;
/* CS5530 Video device registers */
#define CS5530_VIDEO_CONFIG 0x0000
# define CS5530_VCFG_VID_EN 0x00000001
# define CS5530_VCFG_VID_REG_UPDATE 0x00000002
# define CS5530_VCFG_VID_INP_FORMAT 0x0000000C
# define CS5530_VCFG_8_BIT_4_2_0 0x00000004
# define CS5530_VCFG_16_BIT_4_2_0 0x00000008
# define CS5530_VCFG_GV_SEL 0x00000010
# define CS5530_VCFG_CSC_BYPASS 0x00000020
# define CS5530_VCFG_X_FILTER_EN 0x00000040
# define CS5530_VCFG_Y_FILTER_EN 0x00000080
# define CS5530_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00
# define CS5530_VCFG_INIT_READ_MASK 0x01FF0000
# define CS5530_VCFG_EARLY_VID_RDY 0x02000000
# define CS5530_VCFG_LINE_SIZE_UPPER 0x08000000
# define CS5530_VCFG_4_2_0_MODE 0x10000000
# define CS5530_VCFG_16_BIT_EN 0x20000000
# define CS5530_VCFG_HIGH_SPD_INT 0x40000000
#define CS5530_DISPLAY_CONFIG 0x0004
# define CS5530_DCFG_DIS_EN 0x00000001
# define CS5530_DCFG_HSYNC_EN 0x00000002
# define CS5530_DCFG_VSYNC_EN 0x00000004
# define CS5530_DCFG_DAC_BL_EN 0x00000008
# define CS5530_DCFG_DAC_PWR_EN 0x00000020
# define CS5530_DCFG_FP_PWR_EN 0x00000040
# define CS5530_DCFG_FP_DATA_EN 0x00000080
# define CS5530_DCFG_CRT_HSYNC_POL 0x00000100
# define CS5530_DCFG_CRT_VSYNC_POL 0x00000200
# define CS5530_DCFG_FP_HSYNC_POL 0x00000400
# define CS5530_DCFG_FP_VSYNC_POL 0x00000800
# define CS5530_DCFG_XGA_FP 0x00001000
# define CS5530_DCFG_FP_DITH_EN 0x00002000
# define CS5530_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
# define CS5530_DCFG_CRT_SYNC_SKW_INIT 0x00010000
# define CS5530_DCFG_PWR_SEQ_DLY_MASK 0x000E0000
# define CS5530_DCFG_PWR_SEQ_DLY_INIT 0x00080000
# define CS5530_DCFG_VG_CK 0x00100000
# define CS5530_DCFG_GV_PAL_BYP 0x00200000
# define CS5530_DCFG_DDC_SCL 0x00400000
# define CS5530_DCFG_DDC_SDA 0x00800000
# define CS5530_DCFG_DDC_OE 0x01000000
# define CS5530_DCFG_16_BIT_EN 0x02000000
#define CS5530_VIDEO_X_POS 0x0008
#define CS5530_VIDEO_Y_POS 0x000C
#define CS5530_VIDEO_SCALE 0x0010
#define CS5530_VIDEO_COLOR_KEY 0x0014
#define CS5530_VIDEO_COLOR_MASK 0x0018
#define CS5530_PALETTE_ADDRESS 0x001C
#define CS5530_PALETTE_DATA 0x0020
#define CS5530_DOT_CLK_CONFIG 0x0024
#define CS5530_CRCSIG_TFT_TV 0x0028
#endif /* !__VIDEO_CS5530_H__ */

347
drivers/video/geode/video_gx.c Normal file
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@@ -0,0 +1,347 @@
/*
* Geode GX video processor device.
*
* Copyright (C) 2006 Arcom Control Systems Ltd.
*
* Portions from AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/msr.h>
#include "geodefb.h"
#include "video_gx.h"
/*
* Tables of register settings for various DOTCLKs.
*/
struct gx_pll_entry {
long pixclock; /* ps */
u32 sys_rstpll_bits;
u32 dotpll_value;
};
#define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
#define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
#define PREDIV2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
static const struct gx_pll_entry gx_pll_table_48MHz[] = {
{ 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
{ 39721, 0, 0x00000037 }, /* 25.1750 */
{ 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
{ 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
{ 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
{ 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
{ 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
{ 22271, 0, 0x00000063 }, /* 44.9000 */
{ 20202, 0, 0x0000054B }, /* 49.5000 */
{ 20000, 0, 0x0000026E }, /* 50.0000 */
{ 19860, PREMULT2, 0x00000037 }, /* 50.3500 */
{ 18518, POSTDIV3|PREMULT2, 0x00000B0D }, /* 54.0000 */
{ 17777, 0, 0x00000577 }, /* 56.2500 */
{ 17733, 0, 0x000007F7 }, /* 56.3916 */
{ 17653, 0, 0x0000057B }, /* 56.6444 */
{ 16949, PREMULT2, 0x00000707 }, /* 59.0000 */
{ 15873, POSTDIV3|PREMULT2, 0x00000B39 }, /* 63.0000 */
{ 15384, POSTDIV3|PREMULT2, 0x00000B45 }, /* 65.0000 */
{ 14814, POSTDIV3|PREMULT2, 0x00000FC1 }, /* 67.5000 */
{ 14124, POSTDIV3, 0x00000561 }, /* 70.8000 */
{ 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */
{ 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */
{ 13333, 0, 0x00000052 }, /* 75.0000 */
{ 12698, 0, 0x00000056 }, /* 78.7500 */
{ 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */
{ 11135, PREMULT2, 0x00000262 }, /* 89.8000 */
{ 10582, 0, 0x000002D2 }, /* 94.5000 */
{ 10101, PREMULT2, 0x00000B4A }, /* 99.0000 */
{ 10000, PREMULT2, 0x00000036 }, /* 100.0000 */
{ 9259, 0, 0x000007E2 }, /* 108.0000 */
{ 8888, 0, 0x000007F6 }, /* 112.5000 */
{ 7692, POSTDIV3|PREMULT2, 0x00000FB0 }, /* 130.0000 */
{ 7407, POSTDIV3|PREMULT2, 0x00000B50 }, /* 135.0000 */
{ 6349, 0, 0x00000055 }, /* 157.5000 */
{ 6172, 0, 0x000009C1 }, /* 162.0000 */
{ 5787, PREMULT2, 0x0000002D }, /* 172.798 */
{ 5698, 0, 0x000002C1 }, /* 175.5000 */
{ 5291, 0, 0x000002D1 }, /* 189.0000 */
{ 4938, 0, 0x00000551 }, /* 202.5000 */
{ 4357, 0, 0x0000057D }, /* 229.5000 */
};
static const struct gx_pll_entry gx_pll_table_14MHz[] = {
{ 39721, 0, 0x00000037 }, /* 25.1750 */
{ 35308, 0, 0x00000B7B }, /* 28.3220 */
{ 31746, 0, 0x000004D3 }, /* 31.5000 */
{ 27777, 0, 0x00000BE3 }, /* 36.0000 */
{ 26666, 0, 0x0000074F }, /* 37.5000 */
{ 25000, 0, 0x0000050B }, /* 40.0000 */
{ 22271, 0, 0x00000063 }, /* 44.9000 */
{ 20202, 0, 0x0000054B }, /* 49.5000 */
{ 20000, 0, 0x0000026E }, /* 50.0000 */
{ 19860, 0, 0x000007C3 }, /* 50.3500 */
{ 18518, 0, 0x000007E3 }, /* 54.0000 */
{ 17777, 0, 0x00000577 }, /* 56.2500 */
{ 17733, 0, 0x000002FB }, /* 56.3916 */
{ 17653, 0, 0x0000057B }, /* 56.6444 */
{ 16949, 0, 0x0000058B }, /* 59.0000 */
{ 15873, 0, 0x0000095E }, /* 63.0000 */
{ 15384, 0, 0x0000096A }, /* 65.0000 */
{ 14814, 0, 0x00000BC2 }, /* 67.5000 */
{ 14124, 0, 0x0000098A }, /* 70.8000 */
{ 13888, 0, 0x00000BE2 }, /* 72.0000 */
{ 13333, 0, 0x00000052 }, /* 75.0000 */
{ 12698, 0, 0x00000056 }, /* 78.7500 */
{ 12500, 0, 0x0000050A }, /* 80.0000 */
{ 11135, 0, 0x0000078E }, /* 89.8000 */
{ 10582, 0, 0x000002D2 }, /* 94.5000 */
{ 10101, 0, 0x000011F6 }, /* 99.0000 */
{ 10000, 0, 0x0000054E }, /* 100.0000 */
{ 9259, 0, 0x000007E2 }, /* 108.0000 */
{ 8888, 0, 0x000002FA }, /* 112.5000 */
{ 7692, 0, 0x00000BB1 }, /* 130.0000 */
{ 7407, 0, 0x00000975 }, /* 135.0000 */
{ 6349, 0, 0x00000055 }, /* 157.5000 */
{ 6172, 0, 0x000009C1 }, /* 162.0000 */
{ 5698, 0, 0x000002C1 }, /* 175.5000 */
{ 5291, 0, 0x00000539 }, /* 189.0000 */
{ 4938, 0, 0x00000551 }, /* 202.5000 */
{ 4357, 0, 0x0000057D }, /* 229.5000 */
};
static void gx_set_dclk_frequency(struct fb_info *info)
{
const struct gx_pll_entry *pll_table;
int pll_table_len;
int i, best_i;
long min, diff;
u64 dotpll, sys_rstpll;
int timeout = 1000;
/* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
if (cpu_data->x86_mask == 1) {
pll_table = gx_pll_table_14MHz;
pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
} else {
pll_table = gx_pll_table_48MHz;
pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
}
/* Search the table for the closest pixclock. */
best_i = 0;
min = abs(pll_table[0].pixclock - info->var.pixclock);
for (i = 1; i < pll_table_len; i++) {
diff = abs(pll_table[i].pixclock - info->var.pixclock);
if (diff < min) {
min = diff;
best_i = i;
}
}
rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
rdmsrl(MSR_GLCP_DOTPLL, dotpll);
/* Program new M, N and P. */
dotpll &= 0x00000000ffffffffull;
dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
wrmsrl(MSR_GLCP_DOTPLL, dotpll);
/* Program dividers. */
sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
| MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
| MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
/* Clear reset bit to start PLL. */
dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
wrmsrl(MSR_GLCP_DOTPLL, dotpll);
/* Wait for LOCK bit. */
do {
rdmsrl(MSR_GLCP_DOTPLL, dotpll);
} while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
}
static void
gx_configure_tft(struct fb_info *info)
{
struct geodefb_par *par = info->par;
unsigned long val;
unsigned long fp;
/* Set up the DF pad select MSR */
rdmsrl(GX_VP_MSR_PAD_SELECT, val);
val &= ~GX_VP_PAD_SELECT_MASK;
val |= GX_VP_PAD_SELECT_TFT;
wrmsrl(GX_VP_MSR_PAD_SELECT, val);
/* Turn off the panel */
fp = readl(par->vid_regs + GX_FP_PM);
fp &= ~GX_FP_PM_P;
writel(fp, par->vid_regs + GX_FP_PM);
/* Set timing 1 */
fp = readl(par->vid_regs + GX_FP_PT1);
fp &= GX_FP_PT1_VSIZE_MASK;
fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT;
writel(fp, par->vid_regs + GX_FP_PT1);
/* Timing 2 */
/* Set bits that are always on for TFT */
fp = 0x0F100000;
/* Add sync polarity */
if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
fp |= GX_FP_PT2_VSP;
if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
fp |= GX_FP_PT2_HSP;
writel(fp, par->vid_regs + GX_FP_PT2);
/* Set the dither control */
writel(0x70, par->vid_regs + GX_FP_DFC);
/* Enable the FP data and power (in case the BIOS didn't) */
fp = readl(par->vid_regs + GX_DCFG);
fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN;
writel(fp, par->vid_regs + GX_DCFG);
/* Unblank the panel */
fp = readl(par->vid_regs + GX_FP_PM);
fp |= GX_FP_PM_P;
writel(fp, par->vid_regs + GX_FP_PM);
}
static void gx_configure_display(struct fb_info *info)
{
struct geodefb_par *par = info->par;
u32 dcfg, misc;
/* Set up the MISC register */
misc = readl(par->vid_regs + GX_MISC);
/* Power up the DAC */
misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN);
/* Disable gamma correction */
misc |= GX_MISC_GAM_EN;
writel(misc, par->vid_regs + GX_MISC);
/* Write the display configuration */
dcfg = readl(par->vid_regs + GX_DCFG);
/* Disable hsync and vsync */
dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
writel(dcfg, par->vid_regs + GX_DCFG);
/* Clear bits from existing mode. */
dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
| GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL
| GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
/* Set default sync skew. */
dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT;
/* Enable hsync and vsync. */
dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN;
/* Sync polarities. */
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
dcfg |= GX_DCFG_CRT_HSYNC_POL;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
dcfg |= GX_DCFG_CRT_VSYNC_POL;
/* Enable the display logic */
/* Set up the DACS to blank normally */
dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN;
/* Enable the external DAC VREF? */
writel(dcfg, par->vid_regs + GX_DCFG);
/* Set up the flat panel (if it is enabled) */
if (par->enable_crt == 0)
gx_configure_tft(info);
}
static int gx_blank_display(struct fb_info *info, int blank_mode)
{
struct geodefb_par *par = info->par;
u32 dcfg, fp_pm;
int blank, hsync, vsync;
/* CRT power saving modes. */
switch (blank_mode) {
case FB_BLANK_UNBLANK:
blank = 0; hsync = 1; vsync = 1;
break;
case FB_BLANK_NORMAL:
blank = 1; hsync = 1; vsync = 1;
break;
case FB_BLANK_VSYNC_SUSPEND:
blank = 1; hsync = 1; vsync = 0;
break;
case FB_BLANK_HSYNC_SUSPEND:
blank = 1; hsync = 0; vsync = 1;
break;
case FB_BLANK_POWERDOWN:
blank = 1; hsync = 0; vsync = 0;
break;
default:
return -EINVAL;
}
dcfg = readl(par->vid_regs + GX_DCFG);
dcfg &= ~(GX_DCFG_DAC_BL_EN
| GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN);
if (!blank)
dcfg |= GX_DCFG_DAC_BL_EN;
if (hsync)
dcfg |= GX_DCFG_HSYNC_EN;
if (vsync)
dcfg |= GX_DCFG_VSYNC_EN;
writel(dcfg, par->vid_regs + GX_DCFG);
/* Power on/off flat panel. */
if (par->enable_crt == 0) {
fp_pm = readl(par->vid_regs + GX_FP_PM);
if (blank_mode == FB_BLANK_POWERDOWN)
fp_pm &= ~GX_FP_PM_P;
else
fp_pm |= GX_FP_PM_P;
writel(fp_pm, par->vid_regs + GX_FP_PM);
}
return 0;
}
struct geode_vid_ops gx_vid_ops = {
.set_dclk = gx_set_dclk_frequency,
.configure_display = gx_configure_display,
.blank_display = gx_blank_display,
};

72
drivers/video/geode/video_gx.h Normal file
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@@ -0,0 +1,72 @@
/*
* Geode GX video device
*
* Copyright (C) 2006 Arcom Control Systems Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __VIDEO_GX_H__
#define __VIDEO_GX_H__
extern struct geode_vid_ops gx_vid_ops;
/* GX Flatpanel control MSR */
#define GX_VP_MSR_PAD_SELECT 0xC0002011
#define GX_VP_PAD_SELECT_MASK 0x3FFFFFFF
#define GX_VP_PAD_SELECT_TFT 0x1FFFFFFF
/* Geode GX video processor registers */
#define GX_DCFG 0x0008
# define GX_DCFG_CRT_EN 0x00000001
# define GX_DCFG_HSYNC_EN 0x00000002
# define GX_DCFG_VSYNC_EN 0x00000004
# define GX_DCFG_DAC_BL_EN 0x00000008
# define GX_DCFG_FP_PWR_EN 0x00000040
# define GX_DCFG_FP_DATA_EN 0x00000080
# define GX_DCFG_CRT_HSYNC_POL 0x00000100
# define GX_DCFG_CRT_VSYNC_POL 0x00000200
# define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
# define GX_DCFG_CRT_SYNC_SKW_DFLT 0x00010000
# define GX_DCFG_VG_CK 0x00100000
# define GX_DCFG_GV_GAM 0x00200000
# define GX_DCFG_DAC_VREF 0x04000000
/* Geode GX MISC video configuration */
#define GX_MISC 0x50
#define GX_MISC_GAM_EN 0x00000001
#define GX_MISC_DAC_PWRDN 0x00000400
#define GX_MISC_A_PWRDN 0x00000800
/* Geode GX flat panel display control registers */
#define GX_FP_PT1 0x0400
#define GX_FP_PT1_VSIZE_MASK 0x7FF0000
#define GX_FP_PT1_VSIZE_SHIFT 16
#define GX_FP_PT2 0x408
#define GX_FP_PT2_VSP (1 << 23)
#define GX_FP_PT2_HSP (1 << 22)
#define GX_FP_PM 0x410
# define GX_FP_PM_P 0x01000000
#define GX_FP_DFC 0x418
/* Geode GX clock control MSRs */
#define MSR_GLCP_SYS_RSTPLL 0x4c000014
# define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull)
# define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (0x0000000000000004ull)
# define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (0x0000000000000008ull)
#define MSR_GLCP_DOTPLL 0x4c000015
# define MSR_GLCP_DOTPLL_DOTRESET (0x0000000000000001ull)
# define MSR_GLCP_DOTPLL_BYPASS (0x0000000000008000ull)
# define MSR_GLCP_DOTPLL_LOCK (0x0000000002000000ull)
#endif /* !__VIDEO_GX_H__ */