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Creation of Cybook 2416 (actually Gen4) repository

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mlt
2009-12-18 17:10:00 +00:00
committed by godzil
commit 76f20f4d40
13791 changed files with 6812321 additions and 0 deletions
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1
include/asm-arm/Kbuild Normal file
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include include/asm-generic/Kbuild.asm

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include/asm-arm/a.out.h Normal file
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#ifndef __ARM_A_OUT_H__
#define __ARM_A_OUT_H__
#include <linux/personality.h>
#include <asm/types.h>
struct exec
{
__u32 a_info; /* Use macros N_MAGIC, etc for access */
__u32 a_text; /* length of text, in bytes */
__u32 a_data; /* length of data, in bytes */
__u32 a_bss; /* length of uninitialized data area for file, in bytes */
__u32 a_syms; /* length of symbol table data in file, in bytes */
__u32 a_entry; /* start address */
__u32 a_trsize; /* length of relocation info for text, in bytes */
__u32 a_drsize; /* length of relocation info for data, in bytes */
};
/*
* This is always the same
*/
#define N_TXTADDR(a) (0x00008000)
#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
#define M_ARM 103
#ifdef __KERNEL__
#define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \
TASK_SIZE : TASK_SIZE_26)
#endif
#ifndef LIBRARY_START_TEXT
#define LIBRARY_START_TEXT (0x00c00000)
#endif
#endif /* __A_OUT_GNU_H__ */

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include/asm-arm/arch-aaec2000/aaec2000.h Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/aaec2000.h
*
* AAEC-2000 registers definition
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_AAEC2000_H
#define __ASM_ARCH_AAEC2000_H
#ifndef __ASM_ARCH_HARDWARE_H
#error You must include hardware.h not this file
#endif /* __ASM_ARCH_HARDWARE_H */
/* Chip selects */
#define AAEC_CS0 0x00000000
#define AAEC_CS1 0x10000000
#define AAEC_CS2 0x20000000
#define AAEC_CS3 0x30000000
/* Flash */
#define AAEC_FLASH_BASE AAEC_CS0
#define AAEC_FLASH_SIZE SZ_64M
/* Interrupt controller */
#define IRQ_BASE __REG(0x80000500)
#define IRQ_INTSR __REG(0x80000500) /* Int Status Register */
#define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */
#define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */
#define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */
/* UART 1 */
#define UART1_BASE __REG(0x80000600)
#define UART1_DR __REG(0x80000600) /* Data/FIFO Register */
#define UART1_LCR __REG(0x80000604) /* Link Control Register */
#define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */
#define UART1_CR __REG(0x8000060c) /* Control Register */
#define UART1_SR __REG(0x80000610) /* Status Register */
#define UART1_INT __REG(0x80000614) /* Interrupt Status Register */
#define UART1_INTM __REG(0x80000618) /* Interrupt Mask Register */
#define UART1_INTRES __REG(0x8000061c) /* Int Result (masked status) Register */
/* UART 2 */
#define UART2_BASE __REG(0x80000700)
#define UART2_DR __REG(0x80000700) /* Data/FIFO Register */
#define UART2_LCR __REG(0x80000704) /* Link Control Register */
#define UART2_BRCR __REG(0x80000708) /* Baud Rate Control Register */
#define UART2_CR __REG(0x8000070c) /* Control Register */
#define UART2_SR __REG(0x80000710) /* Status Register */
#define UART2_INT __REG(0x80000714) /* Interrupt Status Register */
#define UART2_INTM __REG(0x80000718) /* Interrupt Mask Register */
#define UART2_INTRES __REG(0x8000071c) /* Int Result (masked status) Register */
/* UART 3 */
#define UART3_BASE __REG(0x80000800)
#define UART3_DR __REG(0x80000800) /* Data/FIFO Register */
#define UART3_LCR __REG(0x80000804) /* Link Control Register */
#define UART3_BRCR __REG(0x80000808) /* Baud Rate Control Register */
#define UART3_CR __REG(0x8000080c) /* Control Register */
#define UART3_SR __REG(0x80000810) /* Status Register */
#define UART3_INT __REG(0x80000814) /* Interrupt Status Register */
#define UART3_INTM __REG(0x80000818) /* Interrupt Mask Register */
#define UART3_INTRES __REG(0x8000081c) /* Int Result (masked status) Register */
/* These are used in some places */
#define _UART1_BASE __PREG(UART1_BASE)
#define _UART2_BASE __PREG(UART2_BASE)
#define _UART3_BASE __PREG(UART3_BASE)
/* UART Registers Offsets */
#define UART_DR 0x00
#define UART_LCR 0x04
#define UART_BRCR 0x08
#define UART_CR 0x0c
#define UART_SR 0x10
#define UART_INT 0x14
#define UART_INTM 0x18
#define UART_INTRES 0x1c
/* UART_LCR Bitmask */
#define UART_LCR_BRK (1 << 0) /* Send Break */
#define UART_LCR_PEN (1 << 1) /* Parity Enable */
#define UART_LCR_EP (1 << 2) /* Even/Odd Parity */
#define UART_LCR_S2 (1 << 3) /* One/Two Stop bits */
#define UART_LCR_FIFO (1 << 4) /* FIFO Enable */
#define UART_LCR_WL5 (0 << 5) /* Word Length - 5 bits */
#define UART_LCR_WL6 (1 << 5) /* Word Length - 6 bits */
#define UART_LCR_WL7 (1 << 6) /* Word Length - 7 bits */
#define UART_LCR_WL8 (1 << 7) /* Word Length - 8 bits */
/* UART_CR Bitmask */
#define UART_CR_EN (1 << 0) /* UART Enable */
#define UART_CR_SIR (1 << 1) /* IrDA SIR Enable */
#define UART_CR_SIRLP (1 << 2) /* Low Power IrDA Enable */
#define UART_CR_RXP (1 << 3) /* Receive Pin Polarity */
#define UART_CR_TXP (1 << 4) /* Transmit Pin Polarity */
#define UART_CR_MXP (1 << 5) /* Modem Pin Polarity */
#define UART_CR_LOOP (1 << 6) /* Loopback Mode */
/* UART_SR Bitmask */
#define UART_SR_CTS (1 << 0) /* Clear To Send Status */
#define UART_SR_DSR (1 << 1) /* Data Set Ready Status */
#define UART_SR_DCD (1 << 2) /* Data Carrier Detect Status */
#define UART_SR_TxBSY (1 << 3) /* Transmitter Busy Status */
#define UART_SR_RxFE (1 << 4) /* Receive FIFO Empty Status */
#define UART_SR_TxFF (1 << 5) /* Transmit FIFO Full Status */
#define UART_SR_RxFF (1 << 6) /* Receive FIFO Full Status */
#define UART_SR_TxFE (1 << 7) /* Transmit FIFO Empty Status */
/* UART_INT Bitmask */
#define UART_INT_RIS (1 << 0) /* Rx Interrupt */
#define UART_INT_TIS (1 << 1) /* Tx Interrupt */
#define UART_INT_MIS (1 << 2) /* Modem Interrupt */
#define UART_INT_RTIS (1 << 3) /* Receive Timeout Interrupt */
/* Timer 1 */
#define TIMER1_BASE __REG(0x80000c00)
#define TIMER1_LOAD __REG(0x80000c00) /* Timer 1 Load Register */
#define TIMER1_VAL __REG(0x80000c04) /* Timer 1 Value Register */
#define TIMER1_CTRL __REG(0x80000c08) /* Timer 1 Control Register */
#define TIMER1_CLEAR __REG(0x80000c0c) /* Timer 1 Clear Register */
/* Timer 2 */
#define TIMER2_BASE __REG(0x80000d00)
#define TIMER2_LOAD __REG(0x80000d00) /* Timer 2 Load Register */
#define TIMER2_VAL __REG(0x80000d04) /* Timer 2 Value Register */
#define TIMER2_CTRL __REG(0x80000d08) /* Timer 2 Control Register */
#define TIMER2_CLEAR __REG(0x80000d0c) /* Timer 2 Clear Register */
/* Timer 3 */
#define TIMER3_BASE __REG(0x80000e00)
#define TIMER3_LOAD __REG(0x80000e00) /* Timer 3 Load Register */
#define TIMER3_VAL __REG(0x80000e04) /* Timer 3 Value Register */
#define TIMER3_CTRL __REG(0x80000e08) /* Timer 3 Control Register */
#define TIMER3_CLEAR __REG(0x80000e0c) /* Timer 3 Clear Register */
/* Timer Control register bits */
#define TIMER_CTRL_ENABLE (1 << 7) /* Enable (Start° Timer */
#define TIMER_CTRL_PERIODIC (1 << 6) /* Periodic Running Mode */
#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */
#define TIMER_CTRL_CLKSEL_508K (1 << 3) /* 508KHz Clock select (Timer 1, 2) */
#define TIMER_CTRL_CLKSEL_2K (0 << 3) /* 2KHz Clock Select (Timer 1, 2)*/
/* Power and State Control */
#define POWER_BASE __REG(0x80000400)
#define POWER_PWRSR __REG(0x80000400) /* Power Status Register */
#define POWER_PWRCNT __REG(0x80000404) /* Power/Clock control */
#define POWER_HALT __REG(0x80000408) /* Power Idle Mode */
#define POWER_STDBY __REG(0x8000040c) /* Power Standby Mode */
#define POWER_BLEOI __REG(0x80000410) /* Battery Low End of Interrupt */
#define POWER_MCEOI __REG(0x80000414) /* Media Changed EoI */
#define POWER_TEOI __REG(0x80000418) /* Tick EoI */
#define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
#define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */
/* GPIO Registers */
#define AAEC_GPIO_PHYS 0x80000e00
#define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00)
#define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04)
#define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08)
#define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c)
#define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10)
#define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14)
#define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18)
#define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c)
#define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20)
#define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24)
#define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28)
#define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c)
#define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30)
#define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34)
#define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38)
#define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c)
#define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40)
#define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44)
#define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48)
#define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c)
#define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50)
#define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54)
#define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58)
#define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c)
#define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60)
#define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64)
#define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68)
#define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c)
#define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70)
#define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74)
#define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78)
#define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c)
#define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80)
#define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84)
#define AAEC_GPIO_PINMUX_PE0CON (1 << 0)
#define AAEC_GPIO_PINMUX_PD0CON (1 << 1)
#define AAEC_GPIO_PINMUX_CODECON (1 << 2)
#define AAEC_GPIO_PINMUX_UART3CON (1 << 3)
/* LCD Controller */
#define AAEC_CLCD_PHYS 0x80003000
#endif /* __ARM_ARCH_AAEC2000_H */

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include/asm-arm/arch-aaec2000/aaed2000.h Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/aaed2000.h
*
* AAED-2000 specific bits definition
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_AAED2000_H
#define __ASM_ARCH_AAED2000_H
/* External GPIOs. */
#define EXT_GPIO_PBASE AAEC_CS3
#define EXT_GPIO_VBASE 0xf8100000
#define EXT_GPIO_LENGTH 0x00001000
#define __ext_gpio_p2v(x) ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE)
#define __ext_gpio_v2p(x) ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE)
#define __EXT_GPIO_REG(x) (*((volatile u32 *)__ext_gpio_p2v(x)))
#define __EXT_GPIO_PREG(x) (__ext_gpio_v2p((u32)&(x)))
#define AAED_EXT_GPIO __EXT_GPIO_REG(EXT_GPIO_PBASE)
#define AAED_EGPIO_KBD_SCAN 0x00003fff /* Keyboard scan data */
#define AAED_EGPIO_PWR_INT 0x00008fff /* Smart battery charger interrupt */
#define AAED_EGPIO_SWITCHED 0x000f0000 /* DIP Switches */
#define AAED_EGPIO_USB_VBUS 0x00400000 /* USB Vbus sense */
#define AAED_EGPIO_LCD_PWR_EN 0x02000000 /* LCD and backlight PWR enable */
#define AAED_EGPIO_nLED0 0x20000000 /* LED 0 */
#define AAED_EGPIO_nLED1 0x20000000 /* LED 1 */
#define AAED_EGPIO_nLED2 0x20000000 /* LED 2 */
#endif /* __ARM_ARCH_AAED2000_H */

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include/asm-arm/arch-aaec2000/debug-macro.S Normal file
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/* linux/include/asm-arm/arch-aaec2000/debug-macro.S
*
* Debugging macro include header
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "hardware.h"
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x80000000 @ physical
movne \rx, #io_p2v(0x80000000) @ virtual
orr \rx, \rx, #0x00000800
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0]
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #0x10]
tst \rd, #(1 << 7)
beq 1002b
.endm
.macro waituart,rd,rx
#if 0
1001: ldr \rd, [\rx, #0x10]
tst \rd, #(1 << 5)
beq 1001b
#endif
.endm

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include/asm-arm/arch-aaec2000/dma.h Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/dma.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/

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include/asm-arm/arch-aaec2000/entry-macro.S Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/entry-macro.S
*
* Low-level IRQ helper for aaec-2000 based platforms
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <asm/arch/irqs.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xf8000000
add r4, r4, #0x00000500
mov \base, r4
ldr \irqstat, [\base, #0]
cmp \irqstat, #0
bne 1001f
ldr \irqnr, =NR_IRQS+1
b 1003f
1001: mov \irqnr, #0
1002: ands \tmp, \irqstat, #1
mov \irqstat, \irqstat, LSR #1
add \irqnr, \irqnr, #1
beq 1002b
sub \irqnr, \irqnr, #1
1003:
.endm

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include/asm-arm/arch-aaec2000/hardware.h Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/hardware.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#include <asm/arch/aaec2000.h>
/* The kernel is loaded at physical address 0xf8000000.
* We map the IO space a bit after
*/
#define PIO_APB_BASE 0x80000000
#define VIO_APB_BASE 0xf8000000
#define IO_APB_LENGTH 0x2000
#define PIO_AHB_BASE 0x80002000
#define VIO_AHB_BASE 0xf8002000
#define IO_AHB_LENGTH 0x2000
#define VIO_BASE VIO_APB_BASE
#define PIO_BASE PIO_APB_BASE
#define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE )
#define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE )
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* FIXME: Is it needed to optimize this a la pxa ?? */
#define __REG(x) (*((volatile u32 *)io_p2v(x)))
#define __PREG(x) (io_v2p((u32)&(x)))
#else /* __ASSEMBLY__ */
#define __REG(x) io_p2v(x)
#define __PREG(x) io_v2p(x)
#endif
#include "aaec2000.h"
#endif /* __ASM_ARCH_HARDWARE_H */

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include/asm-arm/arch-aaec2000/io.h Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/io.h
*
* Copied from asm/arch/sa1100/io.h
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#endif

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include/asm-arm/arch-aaec2000/irqs.h Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/irqs.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#define INT_GPIOF0_FIQ 0 /* External GPIO Port F O Fast Interrupt Input */
#define INT_BL_FIQ 1 /* Battery Low Fast Interrupt */
#define INT_WE_FIQ 2 /* Watchdog Expired Fast Interrupt */
#define INT_MV_FIQ 3 /* Media Changed Interrupt */
#define INT_SC 4 /* Sound Codec Interrupt */
#define INT_GPIO1 5 /* GPIO Port F Configurable Int 1 */
#define INT_GPIO2 6 /* GPIO Port F Configurable Int 2 */
#define INT_GPIO3 7 /* GPIO Port F Configurable Int 3 */
#define INT_TMR1_OFL 8 /* Timer 1 Overflow Interrupt */
#define INT_TMR2_OFL 9 /* Timer 2 Overflow Interrupt */
#define INT_RTC_CM 10 /* RTC Compare Match Interrupt */
#define INT_TICK 11 /* 64Hz Tick Interrupt */
#define INT_UART1 12 /* UART1 Interrupt */
#define INT_UART2 13 /* UART2 & Modem State Changed Interrupt */
#define INT_LCD 14 /* LCD Interrupt */
#define INT_SSI 15 /* SSI End of Transfer Interrupt */
#define INT_UART3 16 /* UART3 Interrupt */
#define INT_SCI 17 /* SCI Interrupt */
#define INT_AAC 18 /* Advanced Audio Codec Interrupt */
#define INT_MMC 19 /* MMC Interrupt */
#define INT_USB 20 /* USB Interrupt */
#define INT_DMA 21 /* DMA Interrupt */
#define INT_TMR3_UOFL 22 /* Timer 3 Underflow Interrupt */
#define INT_GPIO4 23 /* GPIO Port F Configurable Int 4 */
#define INT_GPIO5 24 /* GPIO Port F Configurable Int 4 */
#define INT_GPIO6 25 /* GPIO Port F Configurable Int 4 */
#define INT_GPIO7 26 /* GPIO Port F Configurable Int 4 */
#define INT_BMI 27 /* BMI Interrupt */
#define NR_IRQS (INT_BMI + 1)
#endif /* __ASM_ARCH_IRQS_H */

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include/asm-arm/arch-aaec2000/memory.h Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/memory.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET UL(0xf0000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
/*
* The nodes are the followings:
*
* node 0: 0xf000.0000 - 0xf3ff.ffff
* node 1: 0xf400.0000 - 0xf7ff.ffff
* node 2: 0xf800.0000 - 0xfbff.ffff
* node 3: 0xfc00.0000 - 0xffff.ffff
*/
#define NODE_MEM_SIZE_BITS 26
#endif /* __ASM_ARCH_MEMORY_H */

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include/asm-arm/arch-aaec2000/system.h Normal file
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/*
* linux/include/asm-arm/arch-aaed2000/system.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
cpu_reset(0);
}
#endif /* __ASM_ARCH_SYSTEM_H */

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include/asm-arm/arch-aaec2000/timex.h Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/timex.h
*
* AAEC-2000 Architecture timex specification
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#define CLOCK_TICK_RATE 508000
#endif /* __ASM_ARCH_TIMEX_H */

46
include/asm-arm/arch-aaec2000/uncompress.h Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/uncompress.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include "hardware.h"
#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
static void putc(int c)
{
unsigned long serial_port;
do {
serial_port = _UART3_BASE;
if (UART(UART_CR) & UART_CR_EN) break;
serial_port = _UART1_BASE;
if (UART(UART_CR) & UART_CR_EN) break;
serial_port = _UART2_BASE;
if (UART(UART_CR) & UART_CR_EN) break;
return;
} while (0);
/* wait for space in the UART's transmitter */
while ((UART(UART_SR) & UART_SR_TxFF))
barrier();
/* send the character out. */
UART(UART_DR) = c;
}
static inline void flush(void)
{
}
#define arch_decomp_setup()
#define arch_decomp_wdog()
#endif /* __ASM_ARCH_UNCOMPRESS_H */

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include/asm-arm/arch-aaec2000/vmalloc.h Normal file
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/*
* linux/include/asm-arm/arch-aaec2000/vmalloc.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
#endif /* __ASM_ARCH_VMALLOC_H */

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/*
* include/asm-arm/arch-at91/at91_aic.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Advanced Interrupt Controller (AIC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_AIC_H
#define AT91_AIC_H
#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
#define AT91_AIC_SRCTYPE_LOW (0 << 5)
#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
#define AT91_AIC_SRCTYPE_RISING (3 << 5)
#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
#endif

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include/asm-arm/arch-at91/at91_dbgu.h Normal file
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/*
* include/asm-arm/arch-at91/at91_dbgu.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Debug Unit (DBGU) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
#define AT91_CIDR_SRAMSIZ_1K (1 << 16)
#define AT91_CIDR_SRAMSIZ_2K (2 << 16)
#define AT91_CIDR_SRAMSIZ_112K (4 << 16)
#define AT91_CIDR_SRAMSIZ_4K (5 << 16)
#define AT91_CIDR_SRAMSIZ_80K (6 << 16)
#define AT91_CIDR_SRAMSIZ_160K (7 << 16)
#define AT91_CIDR_SRAMSIZ_8K (8 << 16)
#define AT91_CIDR_SRAMSIZ_16K (9 << 16)
#define AT91_CIDR_SRAMSIZ_32K (10 << 16)
#define AT91_CIDR_SRAMSIZ_64K (11 << 16)
#define AT91_CIDR_SRAMSIZ_128K (12 << 16)
#define AT91_CIDR_SRAMSIZ_256K (13 << 16)
#define AT91_CIDR_SRAMSIZ_96K (14 << 16)
#define AT91_CIDR_SRAMSIZ_512K (15 << 16)
#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
#endif

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/*
* include/asm-arm/arch-at91/at91_ecc.h
*
* Error Corrected Code Controller (ECC) - System peripherals regsters.
* Based on AT91SAM9260 datasheet revision B.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef AT91_ECC_H
#define AT91_ECC_H
#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
#define AT91_ECC_RST (1 << 0) /* Reset parity */
#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
#define AT91_ECC_PAGESIZE_528 (0)
#define AT91_ECC_PAGESIZE_1056 (1)
#define AT91_ECC_PAGESIZE_2112 (2)
#define AT91_ECC_PAGESIZE_4224 (3)
#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
#endif

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include/asm-arm/arch-at91/at91_lcdc.h Normal file
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/*
* include/asm-arm/arch-at91/at91_lcdc.h
*
* LCD Controller (LCDC).
* Based on AT91SAM9261 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_LCDC_H
#define AT91_LCDC_H
#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */
#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */
#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */
#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */
#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */
#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */
#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */
#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */
#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */
#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */
#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */
#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */
#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */
#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */
#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */
#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */
#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */
#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */
#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */
#define AT91_LCDC_DISTYPE_STNMONO (0 << 0)
#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0)
#define AT91_LCDC_DISTYPE_TFT (2 << 0)
#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */
#define AT91_LCDC_SCANMOD_SINGLE (0 << 2)
#define AT91_LCDC_SCANMOD_DUAL (1 << 2)
#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */
#define AT91_LCDC_IFWIDTH_4 (0 << 3)
#define AT91_LCDC_IFWIDTH_8 (1 << 3)
#define AT91_LCDC_IFWIDTH_16 (2 << 3)
#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */
#define AT91_LCDC_PIXELSIZE_1 (0 << 5)
#define AT91_LCDC_PIXELSIZE_2 (1 << 5)
#define AT91_LCDC_PIXELSIZE_4 (2 << 5)
#define AT91_LCDC_PIXELSIZE_8 (3 << 5)
#define AT91_LCDC_PIXELSIZE_16 (4 << 5)
#define AT91_LCDC_PIXELSIZE_24 (5 << 5)
#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */
#define AT91_LCDC_INVVD_NORMAL (0 << 8)
#define AT91_LCDC_INVVD_INVERTED (1 << 8)
#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */
#define AT91_LCDC_INVFRAME_NORMAL (0 << 9)
#define AT91_LCDC_INVFRAME_INVERTED (1 << 9)
#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */
#define AT91_LCDC_INVLINE_NORMAL (0 << 10)
#define AT91_LCDC_INVLINE_INVERTED (1 << 10)
#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */
#define AT91_LCDC_INVCLK_NORMAL (0 << 11)
#define AT91_LCDC_INVCLK_INVERTED (1 << 11)
#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */
#define AT91_LCDC_INVDVAL_NORMAL (0 << 12)
#define AT91_LCDC_INVDVAL_INVERTED (1 << 12)
#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */
#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */
#define AT91_LCDC_MEMOR_BIG (0 << 31)
#define AT91_LCDC_MEMOR_LITTLE (1 << 31)
#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */
#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */
#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */
#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */
#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */
#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */
#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */
#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */
#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */
#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */
#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */
#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */
#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */
#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */
#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */
#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */
#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */
#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */
#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */
#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */
#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */
#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */
#define AT91_LCDC_DP1_2_VAL (0xff)
#define AT91_LCDC_DP4_7_VAL (0xfffffff)
#define AT91_LCDC_DP3_5_VAL (0xfffff)
#define AT91_LCDC_DP2_3_VAL (0xfff)
#define AT91_LCDC_DP5_7_VAL (0xfffffff)
#define AT91_LCDC_DP3_4_VAL (0xffff)
#define AT91_LCDC_DP4_5_VAL (0xfffff)
#define AT91_LCDC_DP6_7_VAL (0xfffffff)
#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */
#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */
#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */
#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */
#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */
#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */
#define AT91_LCDC_PS_DIV1 (0 << 0)
#define AT91_LCDC_PS_DIV2 (1 << 0)
#define AT91_LCDC_PS_DIV4 (2 << 0)
#define AT91_LCDC_PS_DIV8 (3 << 0)
#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */
#define AT91_LCDC_POL_NEGATIVE (0 << 2)
#define AT91_LCDC_POL_POSITIVE (1 << 2)
#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */
#define AT91_LCDC_ENA_PWMDISABLE (0 << 3)
#define AT91_LCDC_ENA_PWMENABLE (1 << 3)
#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */
#define AT91_LCDC_CVAL (0xff) /* PWM compare value */
#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */
#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */
#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */
#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */
#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */
#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */
#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */
#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */
#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */
#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */
#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */
#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */
#endif

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/*
* include/asm-arm/arch-at91/at91_mci.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* MultiMedia Card Interface (MCI) registers.
* Based on AT91RM9200 datasheet revision F.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_MCI_H
#define AT91_MCI_H
#define AT91_MCI_CR 0x00 /* Control Register */
#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
#define AT91_MCI_SWRST (1 << 7) /* Software Reset */
#define AT91_MCI_MR 0x04 /* Mode Register */
#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
#define AT91_MCI_DTOMUL_1 (0 << 4)
#define AT91_MCI_DTOMUL_16 (1 << 4)
#define AT91_MCI_DTOMUL_128 (2 << 4)
#define AT91_MCI_DTOMUL_256 (3 << 4)
#define AT91_MCI_DTOMUL_1K (4 << 4)
#define AT91_MCI_DTOMUL_4K (5 << 4)
#define AT91_MCI_DTOMUL_64K (6 << 4)
#define AT91_MCI_DTOMUL_1M (7 << 4)
#define AT91_MCI_SDCR 0x0c /* SD Card Register */
#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
#define AT91_MCI_ARGR 0x10 /* Argument Register */
#define AT91_MCI_CMDR 0x14 /* Command Register */
#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */
#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */
#define AT91_MCI_RSPTYP_NONE (0 << 6)
#define AT91_MCI_RSPTYP_48 (1 << 6)
#define AT91_MCI_RSPTYP_136 (2 << 6)
#define AT91_MCI_SPCMD (7 << 8) /* Special Command */
#define AT91_MCI_SPCMD_NONE (0 << 8)
#define AT91_MCI_SPCMD_INIT (1 << 8)
#define AT91_MCI_SPCMD_SYNC (2 << 8)
#define AT91_MCI_SPCMD_ICMD (4 << 8)
#define AT91_MCI_SPCMD_IRESP (5 << 8)
#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */
#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */
#define AT91_MCI_TRCMD_NONE (0 << 16)
#define AT91_MCI_TRCMD_START (1 << 16)
#define AT91_MCI_TRCMD_STOP (2 << 16)
#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */
#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */
#define AT91_MCI_TRTYP_BLOCK (0 << 19)
#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
#define AT91_MCI_TRTYP_STREAM (2 << 19)
#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
#define AT91_MCR_RDR 0x30 /* Receive Data Register */
#define AT91_MCR_TDR 0x34 /* Transmit Data Register */
#define AT91_MCI_SR 0x40 /* Status Register */
#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */
#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */
#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
#define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */
#define AT91_MCI_OVRE (1 << 30) /* Overrun */
#define AT91_MCI_UNRE (1 << 31) /* Underrun */
#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */
#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */
#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */
#endif

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/*
* include/asm-arm/arch-at91/at91_pio.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIO_H
#define AT91_PIO_H
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#endif

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/*
* include/asm-arm/arch-at91/at91_pit.h
*
* Periodic Interval Timer (PIT) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIT_H
#define AT91_PIT_H
#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
#define AT91_PIT_PITS (1 << 0) /* Timer Status */
#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
#endif

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/*
* include/asm-arm/arch-at91/at91_pmc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Power Management Controller (PMC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PMC_H
#define AT91_PMC_H
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_PLLA (2 << 0)
#define AT91_PMC_CSS_PLLB (3 << 0)
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
#define AT91_PMC_PRES_1 (0 << 2)
#define AT91_PMC_PRES_2 (1 << 2)
#define AT91_PMC_PRES_4 (2 << 2)
#define AT91_PMC_PRES_8 (3 << 2)
#define AT91_PMC_PRES_16 (4 << 2)
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
#define AT91_PMC_MDIV_1 (0 << 8)
#define AT91_PMC_MDIV_2 (1 << 8)
#define AT91_PMC_MDIV_3 (2 << 8)
#define AT91_PMC_MDIV_4 (3 << 8)
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#endif

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/*
* include/asm-arm/arch-at91/at91_rstc.h
*
* Reset Controller (RSTC) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
#define AT91_RSTC_RSTTYP_USER (4 << 8)
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
#endif

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/*
* include/asm-arm/arch-at91/at91_rtc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Real Time Clock (RTC) - System peripheral registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_RTC_H
#define AT91_RTC_H
#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
#define AT91_RTC_DAY (7 << 21) /* Current Day */
#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
#define AT91_RTC_SECEV (1 << 2) /* Second Event */
#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
#endif

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/*
* include/asm-arm/arch-at91/at91_rtt.h
*
* Real-time Timer (RTT) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_RTT_H
#define AT91_RTT_H
#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */
#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */
#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */
#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */
#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
#endif

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/*
* include/asm-arm/arch-at91/at91_shdwc.h
*
* Shutdown Controller (SHDWC) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_SHDWC_H
#define AT91_SHDWC_H
#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */
#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */
#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
#define AT91_SHDW_WKMODE0_NONE 0
#define AT91_SHDW_WKMODE0_HIGH 1
#define AT91_SHDW_WKMODE0_LOW 2
#define AT91_SHDW_WKMODE0_ANYLEVEL 3
#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
#endif

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/*
* include/asm-arm/arch-at91/at91_spi.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Serial Peripheral Interface (SPI) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_SPI_H
#define AT91_SPI_H
#define AT91_SPI_CR 0x00 /* Control Register */
#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
#define AT91_SPI_MR 0x04 /* Mode Register */
#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
#define AT91_SPI_PS_FIXED (0 << 1)
#define AT91_SPI_PS_VARIABLE (1 << 1)
#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
#define AT91_SPI_RDR 0x08 /* Receive Data Register */
#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
#define AT91_SPI_SR 0x10 /* Status Register */
#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
#define AT91_SPI_BITS_8 (0 << 4)
#define AT91_SPI_BITS_9 (1 << 4)
#define AT91_SPI_BITS_10 (2 << 4)
#define AT91_SPI_BITS_11 (3 << 4)
#define AT91_SPI_BITS_12 (4 << 4)
#define AT91_SPI_BITS_13 (5 << 4)
#define AT91_SPI_BITS_14 (6 << 4)
#define AT91_SPI_BITS_15 (7 << 4)
#define AT91_SPI_BITS_16 (8 << 4)
#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
#endif

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/*
* include/asm-arm/arch-at91/at91_ssc.h
*
* Copyright (C) SAN People
*
* Serial Synchronous Controller (SSC) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_SSC_H
#define AT91_SSC_H
#define AT91_SSC_CR 0x00 /* Control Register */
#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */
#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */
#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */
#define AT91_SSC_SWRST (1 << 15) /* Software Reset */
#define AT91_SSC_CMR 0x04 /* Clock Mode Register */
#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */
#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */
#define AT91_SSC_CKS (3 << 0) /* Clock Selection */
#define AT91_SSC_CKS_DIV (0 << 0)
#define AT91_SSC_CKS_CLOCK (1 << 0)
#define AT91_SSC_CKS_PIN (2 << 0)
#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */
#define AT91_SSC_CKO_NONE (0 << 2)
#define AT91_SSC_CKO_CONTINUOUS (1 << 2)
#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
#define AT91_SSC_CKI_FALLING (0 << 5)
#define AT91_SSC_CK_RISING (1 << 5)
#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */
#define AT91_SSC_CKG_NONE (0 << 6)
#define AT91_SSC_CKG_RFLOW (1 << 6)
#define AT91_SSC_CKG_RFHIGH (2 << 6)
#define AT91_SSC_START (0xf << 8) /* Start Selection */
#define AT91_SSC_START_CONTINUOUS (0 << 8)
#define AT91_SSC_START_TX_RX (1 << 8)
#define AT91_SSC_START_LOW_RF (2 << 8)
#define AT91_SSC_START_HIGH_RF (3 << 8)
#define AT91_SSC_START_FALLING_RF (4 << 8)
#define AT91_SSC_START_RISING_RF (5 << 8)
#define AT91_SSC_START_LEVEL_RF (6 << 8)
#define AT91_SSC_START_EDGE_RF (7 << 8)
#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */
#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */
#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */
#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */
#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */
#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */
#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */
#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */
#define AT91_SSC_FSOS_NONE (0 << 20)
#define AT91_SSC_FSOS_NEGATIVE (1 << 20)
#define AT91_SSC_FSOS_POSITIVE (2 << 20)
#define AT91_SSC_FSOS_LOW (3 << 20)
#define AT91_SSC_FSOS_HIGH (4 << 20)
#define AT91_SSC_FSOS_TOGGLE (5 << 20)
#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
#define AT91_SSC_FSEDGE_POSITIVE (0 << 24)
#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24)
#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */
#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */
#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */
#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */
#define AT91_SSC_RHR 0x20 /* Receive Holding Register */
#define AT91_SSC_THR 0x24 /* Transmit Holding Register */
#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */
#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */
#define AT91_SSC_SR 0x40 /* Status Register */
#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */
#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */
#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */
#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */
#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */
#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */
#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */
#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */
#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */
#endif

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/*
* include/asm-arm/arch-at91/at91_st.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* System Timer (ST) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_ST_H
#define AT91_ST_H
#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
#endif

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/*
* include/asm-arm/arch-at91/at91_tc.h
*
* Copyright (C) SAN People
*
* Timer/Counter Unit (TC) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_TC_H
#define AT91_TC_H
#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
#define AT91_TC_TC0XC0S_NONE (1 << 0)
#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
#define AT91_TC_TC1XC1S_NONE (1 << 2)
#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
#define AT91_TC_TC2XC2S_NONE (1 << 4)
#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
#define AT91_TC_CCR 0x00 /* Channel Control Register */
#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
#define AT91_TC_CMR 0x04 /* Channel Mode Register */
#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
#define AT91_TC_TIMER_CLOCK1 (0 << 0)
#define AT91_TC_TIMER_CLOCK2 (1 << 0)
#define AT91_TC_TIMER_CLOCK3 (2 << 0)
#define AT91_TC_TIMER_CLOCK4 (3 << 0)
#define AT91_TC_TIMER_CLOCK5 (4 << 0)
#define AT91_TC_XC0 (5 << 0)
#define AT91_TC_XC1 (6 << 0)
#define AT91_TC_XC2 (7 << 0)
#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
#define AT91_TC_EEVTEDG_NONE (0 << 8)
#define AT91_TC_EEVTEDG_RISING (1 << 8)
#define AT91_TC_EEVTEDG_FALLING (2 << 8)
#define AT91_TC_EEVTEDG_BOTH (3 << 8)
#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
#define AT91_TC_EEVT_TIOB (0 << 10)
#define AT91_TC_EEVT_XC0 (1 << 10)
#define AT91_TC_EEVT_XC1 (2 << 10)
#define AT91_TC_EEVT_XC2 (3 << 10)
#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
#define AT91_TC_WAVESEL_UP (0 << 13)
#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
#define AT91_TC_ACPA_NONE (0 << 16)
#define AT91_TC_ACPA_SET (1 << 16)
#define AT91_TC_ACPA_CLEAR (2 << 16)
#define AT91_TC_ACPA_TOGGLE (3 << 16)
#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
#define AT91_TC_ACPC_NONE (0 << 18)
#define AT91_TC_ACPC_SET (1 << 18)
#define AT91_TC_ACPC_CLEAR (2 << 18)
#define AT91_TC_ACPC_TOGGLE (3 << 18)
#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
#define AT91_TC_AEEVT_NONE (0 << 20)
#define AT91_TC_AEEVT_SET (1 << 20)
#define AT91_TC_AEEVT_CLEAR (2 << 20)
#define AT91_TC_AEEVT_TOGGLE (3 << 20)
#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
#define AT91_TC_ASWTRG_NONE (0 << 22)
#define AT91_TC_ASWTRG_SET (1 << 22)
#define AT91_TC_ASWTRG_CLEAR (2 << 22)
#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
#define AT91_TC_BCPB_NONE (0 << 24)
#define AT91_TC_BCPB_SET (1 << 24)
#define AT91_TC_BCPB_CLEAR (2 << 24)
#define AT91_TC_BCPB_TOGGLE (3 << 24)
#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
#define AT91_TC_BCPC_NONE (0 << 26)
#define AT91_TC_BCPC_SET (1 << 26)
#define AT91_TC_BCPC_CLEAR (2 << 26)
#define AT91_TC_BCPC_TOGGLE (3 << 26)
#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
#define AT91_TC_BEEVT_NONE (0 << 28)
#define AT91_TC_BEEVT_SET (1 << 28)
#define AT91_TC_BEEVT_CLEAR (2 << 28)
#define AT91_TC_BEEVT_TOGGLE (3 << 28)
#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
#define AT91_TC_BSWTRG_NONE (0 << 30)
#define AT91_TC_BSWTRG_SET (1 << 30)
#define AT91_TC_BSWTRG_CLEAR (2 << 30)
#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
#define AT91_TC_CV 0x10 /* Counter Value */
#define AT91_TC_RA 0x14 /* Register A */
#define AT91_TC_RB 0x18 /* Register B */
#define AT91_TC_RC 0x1c /* Register C */
#define AT91_TC_SR 0x20 /* Status Register */
#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
#endif

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/*
* include/asm-arm/arch-at91/at91_twi.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Two-wire Interface (TWI) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_TWI_H
#define AT91_TWI_H
#define AT91_TWI_CR 0x00 /* Control Register */
#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
#define AT91_TWI_MMR 0x04 /* Master Mode Register */
#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */
#define AT91_TWI_IADRSZ_NO (0 << 8)
#define AT91_TWI_IADRSZ_1 (1 << 8)
#define AT91_TWI_IADRSZ_2 (2 << 8)
#define AT91_TWI_IADRSZ_3 (3 << 8)
#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
#define AT91_TWI_IADR 0x0c /* Internal Address Register */
#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */
#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */
#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */
#define AT91_TWI_SR 0x20 /* Status Register */
#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */
#define AT91_TWI_RHR 0x30 /* Receive Holding Register */
#define AT91_TWI_THR 0x34 /* Transmit Holding Register */
#endif

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/*
* include/asm-arm/arch-at91/at91_wdt.h
*
* Watchdog Timer (WDT) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_WDT_H
#define AT91_WDT_H
#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
#define AT91_WDT_KEY (0xff << 24) /* KEY Password */
#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
#endif

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/*
* include/asm-arm/arch-at91/at91rm9200.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Common definitions.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_H
#define AT91RM9200_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripheral */
#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
#define AT91RM9200_ID_US0 6 /* USART 0 */
#define AT91RM9200_ID_US1 7 /* USART 1 */
#define AT91RM9200_ID_US2 8 /* USART 2 */
#define AT91RM9200_ID_US3 9 /* USART 3 */
#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
#define AT91RM9200_ID_UDP 11 /* USB Device Port */
#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
#define AT91RM9200_ID_UHP 23 /* USB Host port */
#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
/*
* Peripheral physical base addresses.
*/
#define AT91RM9200_BASE_TCB0 0xfffa0000
#define AT91RM9200_BASE_TC0 0xfffa0000
#define AT91RM9200_BASE_TC1 0xfffa0040
#define AT91RM9200_BASE_TC2 0xfffa0080
#define AT91RM9200_BASE_TCB1 0xfffa4000
#define AT91RM9200_BASE_TC3 0xfffa4000
#define AT91RM9200_BASE_TC4 0xfffa4040
#define AT91RM9200_BASE_TC5 0xfffa4080
#define AT91RM9200_BASE_UDP 0xfffb0000
#define AT91RM9200_BASE_MCI 0xfffb4000
#define AT91RM9200_BASE_TWI 0xfffb8000
#define AT91RM9200_BASE_EMAC 0xfffbc000
#define AT91RM9200_BASE_US0 0xfffc0000
#define AT91RM9200_BASE_US1 0xfffc4000
#define AT91RM9200_BASE_US2 0xfffc8000
#define AT91RM9200_BASE_US3 0xfffcc000
#define AT91RM9200_BASE_SSC0 0xfffd0000
#define AT91RM9200_BASE_SSC1 0xfffd4000
#define AT91RM9200_BASE_SSC2 0xfffd8000
#define AT91RM9200_BASE_SPI 0xfffe0000
#define AT91_BASE_SYS 0xfffff000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */
#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
#define AT91_MATRIX 0 /* not supported */
/*
* Internal Memory.
*/
#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
#if 0
/*
* PIO pin definitions (peripheral A/B multiplexing).
*/
#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */
#define AT91_PA0_PCK3 (1 << 0) /* B: PMC Programmable Clock Output 3 */
#define AT91_PA1_MOSI (1 << 1) /* A: SPI Master-Out Slave-In */
#define AT91_PA1_PCK0 (1 << 1) /* B: PMC Programmable Clock Output 0 */
#define AT91_PA2_SPCK (1 << 2) /* A: SPI Serial Clock */
#define AT91_PA2_IRQ4 (1 << 2) /* B: External Interrupt 4 */
#define AT91_PA3_NPCS0 (1 << 3) /* A: SPI Peripheral Chip Select 0 */
#define AT91_PA3_IRQ5 (1 << 3) /* B: External Interrupt 5 */
#define AT91_PA4_NPCS1 (1 << 4) /* A: SPI Peripheral Chip Select 1 */
#define AT91_PA4_PCK1 (1 << 4) /* B: PMC Programmable Clock Output 1 */
#define AT91_PA5_NPCS2 (1 << 5) /* A: SPI Peripheral Chip Select 2 */
#define AT91_PA5_TXD3 (1 << 5) /* B: USART Transmit Data 3 */
#define AT91_PA6_NPCS3 (1 << 6) /* A: SPI Peripheral Chip Select 3 */
#define AT91_PA6_RXD3 (1 << 6) /* B: USART Receive Data 3 */
#define AT91_PA7_ETXCK_EREFCK (1 << 7) /* A: Ethernet Reference Clock / Transmit Clock */
#define AT91_PA7_PCK2 (1 << 7) /* B: PMC Programmable Clock Output 2 */
#define AT91_PA8_ETXEN (1 << 8) /* A: Ethernet Transmit Enable */
#define AT91_PA8_MCCDB (1 << 8) /* B: MMC Multimedia Card B Command */
#define AT91_PA9_ETX0 (1 << 9) /* A: Ethernet Transmit Data 0 */
#define AT91_PA9_MCDB0 (1 << 9) /* B: MMC Multimedia Card B Data 0 */
#define AT91_PA10_ETX1 (1 << 10) /* A: Ethernet Transmit Data 1 */
#define AT91_PA10_MCDB1 (1 << 10) /* B: MMC Multimedia Card B Data 1 */
#define AT91_PA11_ECRS_ECRSDV (1 << 11) /* A: Ethernet Carrier Sense / Data Valid */
#define AT91_PA11_MCDB2 (1 << 11) /* B: MMC Multimedia Card B Data 2 */
#define AT91_PA12_ERX0 (1 << 12) /* A: Ethernet Receive Data 0 */
#define AT91_PA12_MCDB3 (1 << 12) /* B: MMC Multimedia Card B Data 3 */
#define AT91_PA13_ERX1 (1 << 13) /* A: Ethernet Receive Data 1 */
#define AT91_PA13_TCLK0 (1 << 13) /* B: TC External Clock Input 0 */
#define AT91_PA14_ERXER (1 << 14) /* A: Ethernet Receive Error */
#define AT91_PA14_TCLK1 (1 << 14) /* B: TC External Clock Input 1 */
#define AT91_PA15_EMDC (1 << 15) /* A: Ethernet Management Data Clock */
#define AT91_PA15_TCLK2 (1 << 15) /* B: TC External Clock Input 2 */
#define AT91_PA16_EMDIO (1 << 16) /* A: Ethernet Management Data I/O */
#define AT91_PA16_IRQ6 (1 << 16) /* B: External Interrupt 6 */
#define AT91_PA17_TXD0 (1 << 17) /* A: USART Transmit Data 0 */
#define AT91_PA17_TIOA0 (1 << 17) /* B: TC I/O Line A 0 */
#define AT91_PA18_RXD0 (1 << 18) /* A: USART Receive Data 0 */
#define AT91_PA18_TIOB0 (1 << 18) /* B: TC I/O Line B 0 */
#define AT91_PA19_SCK0 (1 << 19) /* A: USART Serial Clock 0 */
#define AT91_PA19_TIOA1 (1 << 19) /* B: TC I/O Line A 1 */
#define AT91_PA20_CTS0 (1 << 20) /* A: USART Clear To Send 0 */
#define AT91_PA20_TIOB1 (1 << 20) /* B: TC I/O Line B 1 */
#define AT91_PA21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
#define AT91_PA21_TIOA2 (1 << 21) /* B: TC I/O Line A 2 */
#define AT91_PA22_RXD2 (1 << 22) /* A: USART Receive Data 2 */
#define AT91_PA22_TIOB2 (1 << 22) /* B: TC I/O Line B 2 */
#define AT91_PA23_TXD2 (1 << 23) /* A: USART Transmit Data 2 */
#define AT91_PA23_IRQ3 (1 << 23) /* B: External Interrupt 3 */
#define AT91_PA24_SCK2 (1 << 24) /* A: USART Serial Clock 2 */
#define AT91_PA24_PCK1 (1 << 24) /* B: PMC Programmable Clock Output 1 */
#define AT91_PA25_TWD (1 << 25) /* A: TWI Two-wire Serial Data */
#define AT91_PA25_IRQ2 (1 << 25) /* B: External Interrupt 2 */
#define AT91_PA26_TWCK (1 << 26) /* A: TWI Two-wire Serial Clock */
#define AT91_PA26_IRQ1 (1 << 26) /* B: External Interrupt 1 */
#define AT91_PA27_MCCK (1 << 27) /* A: MMC Multimedia Card Clock */
#define AT91_PA27_TCLK3 (1 << 27) /* B: TC External Clock Input 3 */
#define AT91_PA28_MCCDA (1 << 28) /* A: MMC Multimedia Card A Command */
#define AT91_PA28_TCLK4 (1 << 28) /* B: TC External Clock Input 4 */
#define AT91_PA29_MCDA0 (1 << 29) /* A: MMC Multimedia Card A Data 0 */
#define AT91_PA29_TCLK5 (1 << 29) /* B: TC External Clock Input 5 */
#define AT91_PA30_DRXD (1 << 30) /* A: DBGU Receive Data */
#define AT91_PA30_CTS2 (1 << 30) /* B: USART Clear To Send 2 */
#define AT91_PA31_DTXD (1 << 31) /* A: DBGU Transmit Data */
#define AT91_PA31_RTS2 (1 << 31) /* B: USART Ready To Send 2 */
#define AT91_PB0_TF0 (1 << 0) /* A: SSC Transmit Frame Sync 0 */
#define AT91_PB0_RTS3 (1 << 0) /* B: USART Ready To Send 3 */
#define AT91_PB1_TK0 (1 << 1) /* A: SSC Transmit Clock 0 */
#define AT91_PB1_CTS3 (1 << 1) /* B: USART Clear To Send 3 */
#define AT91_PB2_TD0 (1 << 2) /* A: SSC Transmit Data 0 */
#define AT91_PB2_SCK3 (1 << 2) /* B: USART Serial Clock 3 */
#define AT91_PB3_RD0 (1 << 3) /* A: SSC Receive Data 0 */
#define AT91_PB3_MCDA1 (1 << 3) /* B: MMC Multimedia Card A Data 1 */
#define AT91_PB4_RK0 (1 << 4) /* A: SSC Receive Clock 0 */
#define AT91_PB4_MCDA2 (1 << 4) /* B: MMC Multimedia Card A Data 2 */
#define AT91_PB5_RF0 (1 << 5) /* A: SSC Receive Frame Sync 0 */
#define AT91_PB5_MCDA3 (1 << 5) /* B: MMC Multimedia Card A Data 3 */
#define AT91_PB6_TF1 (1 << 6) /* A: SSC Transmit Frame Sync 1 */
#define AT91_PB6_TIOA3 (1 << 6) /* B: TC I/O Line A 3 */
#define AT91_PB7_TK1 (1 << 7) /* A: SSC Transmit Clock 1 */
#define AT91_PB7_TIOB3 (1 << 7) /* B: TC I/O Line B 3 */
#define AT91_PB8_TD1 (1 << 8) /* A: SSC Transmit Data 1 */
#define AT91_PB8_TIOA4 (1 << 8) /* B: TC I/O Line A 4 */
#define AT91_PB9_RD1 (1 << 9) /* A: SSC Receive Data 1 */
#define AT91_PB9_TIOB4 (1 << 9) /* B: TC I/O Line B 4 */
#define AT91_PB10_RK1 (1 << 10) /* A: SSC Receive Clock 1 */
#define AT91_PB10_TIOA5 (1 << 10) /* B: TC I/O Line A 5 */
#define AT91_PB11_RF1 (1 << 11) /* A: SSC Receive Frame Sync 1 */
#define AT91_PB11_TIOB5 (1 << 11) /* B: TC I/O Line B 5 */
#define AT91_PB12_TF2 (1 << 12) /* A: SSC Transmit Frame Sync 2 */
#define AT91_PB12_ETX2 (1 << 12) /* B: Ethernet Transmit Data 2 */
#define AT91_PB13_TK2 (1 << 13) /* A: SSC Transmit Clock 3 */
#define AT91_PB13_ETX3 (1 << 13) /* B: Ethernet Transmit Data 3 */
#define AT91_PB14_TD2 (1 << 14) /* A: SSC Transmit Data 2 */
#define AT91_PB14_ETXER (1 << 14) /* B: Ethernet Transmit Coding Error */
#define AT91_PB15_RD2 (1 << 15) /* A: SSC Receive Data 2 */
#define AT91_PB15_ERX2 (1 << 15) /* B: Ethernet Receive Data 2 */
#define AT91_PB16_RK2 (1 << 16) /* A: SSC Receive Clock 2 */
#define AT91_PB16_ERX3 (1 << 16) /* B: Ethernet Receive Data 3 */
#define AT91_PB17_RF2 (1 << 17) /* A: SSC Receive Frame Sync 2 */
#define AT91_PB17_ERXDV (1 << 17) /* B: Ethernet Receive Data Valid */
#define AT91_PB18_RI1 (1 << 18) /* A: USART Ring Indicator 1 */
#define AT91_PB18_ECOL (1 << 18) /* B: Ethernet Collision Detected */
#define AT91_PB19_DTR1 (1 << 19) /* A: USART Data Terminal Ready 1 */
#define AT91_PB19_ERXCK (1 << 19) /* B: Ethernet Receive Clock */
#define AT91_PB20_TXD1 (1 << 20) /* A: USART Transmit Data 1 */
#define AT91_PB21_RXD1 (1 << 21) /* A: USART Receive Data 1 */
#define AT91_PB22_SCK1 (1 << 22) /* A: USART Serial Clock 1 */
#define AT91_PB23_DCD1 (1 << 23) /* A: USART Data Carrier Detect 1 */
#define AT91_PB24_CTS1 (1 << 24) /* A: USART Clear To Send 1 */
#define AT91_PB25_DSR1 (1 << 25) /* A: USART Data Set Ready 1 */
#define AT91_PB25_EF100 (1 << 25) /* B: Ethernet Force 100 Mbit */
#define AT91_PB26_RTS1 (1 << 26) /* A: USART Ready To Send 1 */
#define AT91_PB27_PCK0 (1 << 27) /* B: PMC Programmable Clock Output 0 */
#define AT91_PB28_FIQ (1 << 28) /* A: Fast Interrupt */
#define AT91_PB29_IRQ0 (1 << 29) /* A: External Interrupt 0 */
#define AT91_PC0_BFCK (1 << 0) /* A: Burst Flash Clock */
#define AT91_PC1_BFRDY_SMOE (1 << 1) /* A: Burst Flash Ready / SmartMedia Output Enable */
#define AT91_PC2_BFAVD (1 << 2) /* A: Burst Flash Address Valid */
#define AT91_PC3_BFBAA_SMWE (1 << 3) /* A: Burst Flash Address Advance / SmartMedia Write Enable */
#define AT91_PC4_BFOE (1 << 4) /* A: Burst Flash Output Enable */
#define AT91_PC5_BFWE (1 << 5) /* A: Burst Flash Write Enable */
#define AT91_PC6_NWAIT (1 << 6) /* A: SMC Wait Signal */
#define AT91_PC7_A23 (1 << 7) /* A: Address Bus 23 */
#define AT91_PC8_A24 (1 << 8) /* A: Address Bus 24 */
#define AT91_PC9_A25_CFRNW (1 << 9) /* A: Address Bus 25 / Compact Flash Read Not Write */
#define AT91_PC10_NCS4_CFCS (1 << 10) /* A: SMC Chip Select 4 / Compact Flash Chip Select */
#define AT91_PC11_NCS5_CFCE1 (1 << 11) /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
#define AT91_PC12_NCS6_CFCE2 (1 << 12) /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
#define AT91_PC13_NCS7 (1 << 13) /* A: Chip Select 7 */
#define AT91_PD0_ETX0 (1 << 0) /* A: Ethernet Transmit Data 0 */
#define AT91_PD1_ETX1 (1 << 1) /* A: Ethernet Transmit Data 1 */
#define AT91_PD2_ETX2 (1 << 2) /* A: Ethernet Transmit Data 2 */
#define AT91_PD3_ETX3 (1 << 3) /* A: Ethernet Transmit Data 3 */
#define AT91_PD4_ETXEN (1 << 4) /* A: Ethernet Transmit Enable */
#define AT91_PD5_ETXER (1 << 5) /* A: Ethernet Transmit Coding Error */
#define AT91_PD6_DTXD (1 << 6) /* A: DBGU Transmit Data */
#define AT91_PD7_PCK0 (1 << 7) /* A: PMC Programmable Clock Output 0 */
#define AT91_PD7_TSYNC (1 << 7) /* B: ETM Trace Synchronization Signal */
#define AT91_PD8_PCK1 (1 << 8) /* A: PMC Programmable Clock Output 1 */
#define AT91_PD8_TCLK (1 << 8) /* B: ETM Trace Clock */
#define AT91_PD9_PCK2 (1 << 9) /* A: PMC Programmable Clock Output 2 */
#define AT91_PD9_TPS0 (1 << 9) /* B: ETM Trace ARM Pipeline Status 0 */
#define AT91_PD10_PCK3 (1 << 10) /* A: PMC Programmable Clock Output 3 */
#define AT91_PD10_TPS1 (1 << 10) /* B: ETM Trace ARM Pipeline Status 1 */
#define AT91_PD11_TPS2 (1 << 11) /* B: ETM Trace ARM Pipeline Status 2 */
#define AT91_PD12_TPK0 (1 << 12) /* B: ETM Trace Packet Port 0 */
#define AT91_PD13_TPK1 (1 << 13) /* B: ETM Trace Packet Port 1 */
#define AT91_PD14_TPK2 (1 << 14) /* B: ETM Trace Packet Port 2 */
#define AT91_PD15_TD0 (1 << 15) /* A: SSC Transmit Data 0 */
#define AT91_PD15_TPK3 (1 << 15) /* B: ETM Trace Packet Port 3 */
#define AT91_PD16_TD1 (1 << 16) /* A: SSC Transmit Data 1 */
#define AT91_PD16_TPK4 (1 << 16) /* B: ETM Trace Packet Port 4 */
#define AT91_PD17_TD2 (1 << 17) /* A: SSC Transmit Data 2 */
#define AT91_PD17_TPK5 (1 << 17) /* B: ETM Trace Packet Port 5 */
#define AT91_PD18_NPCS1 (1 << 18) /* A: SPI Peripheral Chip Select 1 */
#define AT91_PD18_TPK6 (1 << 18) /* B: ETM Trace Packet Port 6 */
#define AT91_PD19_NPCS2 (1 << 19) /* A: SPI Peripheral Chip Select 2 */
#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */
#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */
#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */
#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */
#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */
#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */
#define AT91_PD23_RTS2 (1 << 23) /* A: USART Ready To Send 2 */
#define AT91_PD23_TPK11 (1 << 23) /* B: ETM Trace Packet Port 11 */
#define AT91_PD24_RTS3 (1 << 24) /* A: USART Ready To Send 3 */
#define AT91_PD24_TPK12 (1 << 24) /* B: ETM Trace Packet Port 12 */
#define AT91_PD25_DTR1 (1 << 25) /* A: USART Data Terminal Ready 1 */
#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */
#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */
#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */
#endif
#endif

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/*
* include/asm-arm/arch-at91/at91rm9200_emac.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Ethernet MAC registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_EMAC_H
#define AT91RM9200_EMAC_H
#define AT91_EMAC_CTL 0x00 /* Control Register */
#define AT91_EMAC_LB (1 << 0) /* Loopback */
#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */
#define AT91_EMAC_RE (1 << 2) /* Receive Enable */
#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */
#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */
#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */
#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */
#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */
#define AT91_EMAC_BP (1 << 8) /* Back Pressure */
#define AT91_EMAC_CFG 0x04 /* Configuration Register */
#define AT91_EMAC_SPD (1 << 0) /* Speed */
#define AT91_EMAC_FD (1 << 1) /* Full Duplex */
#define AT91_EMAC_BR (1 << 2) /* Bit Rate */
#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */
#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */
#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */
#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */
#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */
#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */
#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */
#define AT91_EMAC_CLK_DIV8 (0 << 10)
#define AT91_EMAC_CLK_DIV16 (1 << 10)
#define AT91_EMAC_CLK_DIV32 (2 << 10)
#define AT91_EMAC_CLK_DIV64 (3 << 10)
#define AT91_EMAC_RTY (1 << 12) /* Retry Test */
#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */
#define AT91_EMAC_SR 0x08 /* Status Register */
#define AT91_EMAC_SR_LINK (1 << 0) /* Link */
#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */
#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */
#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */
#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */
#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */
#define AT91_EMAC_NCRC (1 << 15) /* No CRC */
#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */
#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */
#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */
#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */
#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */
#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */
#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */
#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */
#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */
#define AT91_EMAC_RSR 0x20 /* Receive Status Register */
#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */
#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */
#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */
#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */
#define AT91_EMAC_DONE (1 << 0) /* Management Done */
#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */
#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */
#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */
#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */
#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */
#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */
#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */
#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */
#define AT91_EMAC_LINK (1 << 9) /* Link */
#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */
#define AT91_EMAC_ABT (1 << 11) /* Abort */
#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */
#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */
#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */
#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */
#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */
#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */
#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */
#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */
#define AT91_EMAC_RW_W (1 << 28)
#define AT91_EMAC_RW_R (2 << 28)
#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */
/*
* Statistics Registers.
*/
#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */
#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */
#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */
#define AT91_EMAC_OK 0x4c /* Frames Received OK */
#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */
#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */
#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */
#define AT91_EMAC_LCOL 0x5c /* Late Collision */
#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */
#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */
#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */
#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */
#define AT91_EMAC_ROV 0x70 /* Receive Overrun */
#define AT91_EMAC_CDE 0x74 /* Code Error */
#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */
#define AT91_EMAC_RJB 0x7c /* Receive Jabber */
#define AT91_EMAC_USF 0x80 /* Undersize Frame */
#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */
/*
* Address Registers.
*/
#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */
#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */
#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */
#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */
#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */
#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */
#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */
#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */
#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */
#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */
#endif

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/*
* include/asm-arm/arch-at91/at91rm9200_mc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_MC_H
#define AT91RM9200_MC_H
/* Memory Controller */
#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
#define AT91_MC_ABTSZ_BYTE (0 << 8)
#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
#define AT91_MC_ABTSZ_WORD (2 << 8)
#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
#define AT91_MC_ABTTYP_FETCH (2 << 10)
#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
/* External Bus Interface (EBI) registers */
#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
#define AT91_EBI_CS0A_SMC (0 << 0)
#define AT91_EBI_CS0A_BFC (1 << 0)
#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_EBI_CS1A_SMC (0 << 1)
#define AT91_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
#define AT91_EBI_CS3A_SMC (0 << 3)
#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
#define AT91_EBI_CS4A_SMC (0 << 4)
#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
/* Static Memory Controller (SMC) registers */
#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
#define AT91_SMC_NWS_(x) ((x) << 0)
#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
#define AT91_SMC_TDF_(x) ((x) << 8)
#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
#define AT91_SMC_DBW_16 (1 << 13)
#define AT91_SMC_DBW_8 (2 << 13)
#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
#define AT91_SMC_ACSS_STD (0 << 16)
#define AT91_SMC_ACSS_1 (1 << 16)
#define AT91_SMC_ACSS_2 (2 << 16)
#define AT91_SMC_ACSS_3 (3 << 16)
#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
#define AT91_SMC_RWSETUP_(x) ((x) << 24)
#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
#define AT91_SMC_RWHOLD_(x) ((x) << 28)
/* SDRAM Controller registers */
#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
#define AT91_SDRAMC_MODE_NOP (1 << 0)
#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
#define AT91_SDRAMC_MODE_LMR (3 << 0)
#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 4)
#define AT91_SDRAMC_DBW_16 (1 << 4)
#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
#define AT91_SDRAMC_NC_10 (2 << 0)
#define AT91_SDRAMC_NC_11 (3 << 0)
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91_SDRAMC_NR_11 (0 << 2)
#define AT91_SDRAMC_NR_12 (1 << 2)
#define AT91_SDRAMC_NR_13 (2 << 2)
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91_SDRAMC_NB_2 (0 << 4)
#define AT91_SDRAMC_NB_4 (1 << 4)
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91_SDRAMC_CAS_2 (2 << 5)
#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
/* Burst Flash Controller register */
#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
#define AT91_BFC_BFCOM_DISABLED (0 << 0)
#define AT91_BFC_BFCOM_ASYNC (1 << 0)
#define AT91_BFC_BFCOM_BURST (2 << 0)
#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
#define AT91_BFC_BFCC_MCK (1 << 2)
#define AT91_BFC_BFCC_DIV2 (2 << 2)
#define AT91_BFC_BFCC_DIV4 (3 << 2)
#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
#define AT91_BFC_PAGES (7 << 8) /* Page Size */
#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
#define AT91_BFC_PAGES_16 (1 << 8)
#define AT91_BFC_PAGES_32 (2 << 8)
#define AT91_BFC_PAGES_64 (3 << 8)
#define AT91_BFC_PAGES_128 (4 << 8)
#define AT91_BFC_PAGES_256 (5 << 8)
#define AT91_BFC_PAGES_512 (6 << 8)
#define AT91_BFC_PAGES_1024 (7 << 8)
#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
#endif

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include/asm-arm/arch-at91/at91sam9260.h Normal file
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/*
* include/asm-arm/arch-at91/at91sam9260.h
*
* (C) 2006 Andrew Victor
*
* Common definitions.
* Based on AT91SAM9260 datasheet revision A (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9260_H
#define AT91SAM9260_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
#define AT91SAM9260_ID_US0 6 /* USART 0 */
#define AT91SAM9260_ID_US1 7 /* USART 1 */
#define AT91SAM9260_ID_US2 8 /* USART 2 */
#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
#define AT91SAM9260_ID_UHP 20 /* USB Host port */
#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
#define AT91SAM9260_ID_US3 23 /* USART 3 */
#define AT91SAM9260_ID_US4 24 /* USART 4 */
#define AT91SAM9260_ID_US5 25 /* USART 5 */
#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9260_BASE_TCB0 0xfffa0000
#define AT91SAM9260_BASE_TC0 0xfffa0000
#define AT91SAM9260_BASE_TC1 0xfffa0040
#define AT91SAM9260_BASE_TC2 0xfffa0080
#define AT91SAM9260_BASE_UDP 0xfffa4000
#define AT91SAM9260_BASE_MCI 0xfffa8000
#define AT91SAM9260_BASE_TWI 0xfffac000
#define AT91SAM9260_BASE_US0 0xfffb0000
#define AT91SAM9260_BASE_US1 0xfffb4000
#define AT91SAM9260_BASE_US2 0xfffb8000
#define AT91SAM9260_BASE_SSC 0xfffbc000
#define AT91SAM9260_BASE_ISI 0xfffc0000
#define AT91SAM9260_BASE_EMAC 0xfffc4000
#define AT91SAM9260_BASE_SPI0 0xfffc8000
#define AT91SAM9260_BASE_SPI1 0xfffcc000
#define AT91SAM9260_BASE_US3 0xfffd0000
#define AT91SAM9260_BASE_US4 0xfffd4000
#define AT91SAM9260_BASE_US5 0xfffd8000
#define AT91SAM9260_BASE_TCB1 0xfffdc000
#define AT91SAM9260_BASE_TC3 0xfffdc000
#define AT91SAM9260_BASE_TC4 0xfffdc040
#define AT91SAM9260_BASE_TC5 0xfffdc080
#define AT91SAM9260_BASE_ADC 0xfffe0000
#define AT91_BASE_SYS 0xffffe800
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
/*
* Internal Memory.
*/
#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#if 0
/*
* PIO pin definitions (peripheral A/B multiplexing).
*/
// TODO: Add
#endif
#endif

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include/asm-arm/arch-at91/at91sam9260_matrix.h Normal file
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/*
* include/asm-arm/arch-at91/at91sam9260_matrix.h
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9260 datasheet revision B.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9260_MATRIX_H
#define AT91SAM9260_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_CS3A_SMC (0 << 3)
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
#endif

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include/asm-arm/arch-at91/at91sam9261.h Normal file
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/*
* include/asm-arm/arch-at91/at91sam9261.h
*
* Copyright (C) SAN People
*
* Common definitions.
* Based on AT91SAM9261 datasheet revision E. (Preliminary)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9261_H
#define AT91SAM9261_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9261_ID_US0 6 /* USART 0 */
#define AT91SAM9261_ID_US1 7 /* USART 1 */
#define AT91SAM9261_ID_US2 8 /* USART 2 */
#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
#define AT91SAM9261_ID_UHP 20 /* USB Host port */
#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9261_BASE_TCB0 0xfffa0000
#define AT91SAM9261_BASE_TC0 0xfffa0000
#define AT91SAM9261_BASE_TC1 0xfffa0040
#define AT91SAM9261_BASE_TC2 0xfffa0080
#define AT91SAM9261_BASE_UDP 0xfffa4000
#define AT91SAM9261_BASE_MCI 0xfffa8000
#define AT91SAM9261_BASE_TWI 0xfffac000
#define AT91SAM9261_BASE_US0 0xfffb0000
#define AT91SAM9261_BASE_US1 0xfffb4000
#define AT91SAM9261_BASE_US2 0xfffb8000
#define AT91SAM9261_BASE_SSC0 0xfffbc000
#define AT91SAM9261_BASE_SSC1 0xfffc0000
#define AT91SAM9261_BASE_SSC2 0xfffc4000
#define AT91SAM9261_BASE_SPI0 0xfffc8000
#define AT91SAM9261_BASE_SPI1 0xfffcc000
#define AT91_BASE_SYS 0xffffea00
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
/*
* Internal Memory.
*/
#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
#if 0
/*
* PIO pin definitions (peripheral A/B multiplexing).
*/
#define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */
#define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */
#define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */
#define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */
#define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */
#define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */
#define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */
#define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */
#define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */
#define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */
#define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */
#define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */
#define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */
#define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */
#define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */
#define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */
#define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */
#define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */
#define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */
#define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */
#define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */
#define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */
#define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */
#define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */
#define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */
#define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */
#define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */
#define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */
#define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */
#define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */
#define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */
#define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */
#define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */
#define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */
#define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */
#define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */
#define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */
#define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */
#define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */
#define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */
#define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */
#define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */
#define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */
#define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */
#define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */
#define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */
#define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */
#define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */
#define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */
#define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */
#define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */
#define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */
#define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */
#define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */
#define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */
#define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */
#define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */
#define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */
#define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */
#define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */
#define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */
#define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */
#define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */
#define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */
#define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */
#define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */
#define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */
#define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */
#define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */
#define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */
#define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */
#define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */
#define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */
#define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */
#define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */
#define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */
#define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */
#define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */
#define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */
#define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */
#define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */
#define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */
#define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */
#define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */
#define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */
#define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */
#define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */
#define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */
#define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */
#define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */
#define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */
#define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */
#define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */
#define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */
#define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */
#define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */
#define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */
#define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */
#define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */
#define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */
#define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */
#define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */
#define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */
#define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */
#define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */
#define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */
#define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */
#define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */
#define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */
#define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */
#define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */
#define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */
#define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */
#define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */
#define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */
#define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */
#define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */
#define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */
#define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */
#define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */
#define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */
#define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */
#define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */
#define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */
#define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */
#define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */
#define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */
#define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */
#define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */
#define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */
#define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */
#define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */
#define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */
#define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */
#define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */
#define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */
#define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */
#define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */
#define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */
#define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */
#define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */
#define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */
#define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */
#define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */
#define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */
#define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */
#define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */
#define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */
#define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */
#define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */
#define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */
#define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */
#define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */
#define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */
#define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */
#define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */
#define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */
#define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */
#define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
#define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */
#define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
#define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */
#define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
#define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */
#define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
#define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */
#define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
#define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */
#define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
#define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */
#define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */
#define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */
#define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */
#define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */
#define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */
#define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */
#define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */
#define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */
#define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */
#define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */
#define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */
#define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */
#define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */
#endif
#endif

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/*
* include/asm-arm/arch-at91/at91sam9261_matrix.h
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9261_MATRIX_H
#define AT91SAM9261_MATRIX_H
#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_ITCM_64 (7 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_DTCM_64 (7 << 4)
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_CS3A_SMC (0 << 3)
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
#endif

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/*
* include/asm-arm/arch-at91/at91sam9263.h
*
* (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_H
#define AT91SAM9263_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
#define AT91SAM9263_ID_US0 7 /* USART 0 */
#define AT91SAM9263_ID_US1 8 /* USART 1 */
#define AT91SAM9263_ID_US2 9 /* USART 2 */
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
#define AT91SAM9263_ID_CAN 12 /* CAN */
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
#define AT91SAM9263_ID_UHP 29 /* USB Host port */
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9263_BASE_UDP 0xfff78000
#define AT91SAM9263_BASE_TCB0 0xfff7c000
#define AT91SAM9263_BASE_TC0 0xfff7c000
#define AT91SAM9263_BASE_TC1 0xfff7c040
#define AT91SAM9263_BASE_TC2 0xfff7c080
#define AT91SAM9263_BASE_MCI0 0xfff80000
#define AT91SAM9263_BASE_MCI1 0xfff84000
#define AT91SAM9263_BASE_TWI 0xfff88000
#define AT91SAM9263_BASE_US0 0xfff8c000
#define AT91SAM9263_BASE_US1 0xfff90000
#define AT91SAM9263_BASE_US2 0xfff94000
#define AT91SAM9263_BASE_SSC0 0xfff98000
#define AT91SAM9263_BASE_SSC1 0xfff9c000
#define AT91SAM9263_BASE_AC97C 0xfffa0000
#define AT91SAM9263_BASE_SPI0 0xfffa4000
#define AT91SAM9263_BASE_SPI1 0xfffa8000
#define AT91SAM9263_BASE_CAN 0xfffac000
#define AT91SAM9263_BASE_PWMC 0xfffb8000
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
#define AT91_BASE_SYS 0xffffe000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_SMC AT91_SMC0
/*
* Internal Memory.
*/
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
#if 0
/*
* PIO pin definitions (peripheral A/B multiplexing).
*/
// TODO: Add
#endif
#endif

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/*
* include/asm-arm/arch-at91/at91sam9263_matrix.h
*
* Copyright (C) 2006 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_MATRIX_H
#define AT91SAM9263_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
#endif

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/*
* include/asm-arm/arch-at91/at91sam926x_mc.h
*
* Memory Controllers (SMC, SDRAMC) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM926x_MC_H
#define AT91SAM926x_MC_H
/* SDRAM Controller (SDRAMC) registers */
#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL 0
#define AT91_SDRAMC_MODE_NOP 1
#define AT91_SDRAMC_MODE_PRECHARGE 2
#define AT91_SDRAMC_MODE_LMR 3
#define AT91_SDRAMC_MODE_REFRESH 4
#define AT91_SDRAMC_MODE_EXT_LMR 5
#define AT91_SDRAMC_MODE_DEEP 6
#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
#define AT91_SDRAMC_NC_10 (2 << 0)
#define AT91_SDRAMC_NC_11 (3 << 0)
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91_SDRAMC_NR_11 (0 << 2)
#define AT91_SDRAMC_NR_12 (1 << 2)
#define AT91_SDRAMC_NR_13 (2 << 2)
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91_SDRAMC_NB_2 (0 << 4)
#define AT91_SDRAMC_NB_4 (1 << 4)
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91_SDRAMC_CAS_1 (1 << 5)
#define AT91_SDRAMC_CAS_2 (2 << 5)
#define AT91_SDRAMC_CAS_3 (3 << 5)
#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 7)
#define AT91_SDRAMC_DBW_16 (1 << 7)
#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_SDRAMC_LPCB_DISABLE 0
#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
#define AT91_SDRAMC_LPCB_POWER_DOWN 2
#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
#define AT91_SDRAMC_MD_SDRAM 0
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
/* Static Memory Controller (SMC) registers */
#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
#define AT91_SMC_EXNWMODE_READY (3 << 4)
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
#define AT91_SMC_BAT_SELECT (0 << 8)
#define AT91_SMC_BAT_WRITE (1 << 8)
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
#define AT91_SMC_DBW_8 (0 << 12)
#define AT91_SMC_DBW_16 (1 << 12)
#define AT91_SMC_DBW_32 (2 << 12)
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
#define AT91_SMC_TDF_(x) ((x) << 16)
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
#define AT91_SMC_PS (3 << 28) /* Page Size */
#define AT91_SMC_PS_4 (0 << 28)
#define AT91_SMC_PS_8 (1 << 28)
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
#endif
#endif

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/*
* include/asm-arm/arch-at91/board.h
*
* Copyright (C) 2005 HP Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* These are data structures found in platform_device.dev.platform_data,
* and describing board-specific data needed by drivers. For example,
* which pin is used for a given GPIO role.
*
* In 2.6, drivers should strongly avoid board-specific knowledge so
* that supporting new boards normally won't require driver patches.
* Most board-specific knowledge should be in arch/.../board-*.c files.
*/
#ifndef __ASM_ARCH_BOARD_H
#define __ASM_ARCH_BOARD_H
#include <linux/mtd/partitions.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
/* USB Device */
struct at91_udc_data {
u8 vbus_pin; /* high == host powering us */
u8 pullup_pin; /* high == D+ pulled up */
};
extern void __init at91_add_device_udc(struct at91_udc_data *data);
/* Compact Flash */
struct at91_cf_data {
u8 irq_pin; /* I/O IRQ */
u8 det_pin; /* Card detect */
u8 vcc_pin; /* power switching */
u8 rst_pin; /* card reset */
u8 chipselect; /* EBI Chip Select number */
};
extern void __init at91_add_device_cf(struct at91_cf_data *data);
/* MMC / SD */
struct at91_mmc_data {
u8 det_pin; /* card detect IRQ */
unsigned slot_b:1; /* uses Slot B */
unsigned wire4:1; /* (SD) supports DAT0..DAT3 */
u8 wp_pin; /* (SD) writeprotect detect */
u8 vcc_pin; /* power switching (high == on) */
};
extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
/* Ethernet */
struct at91_eth_data {
u8 phy_irq_pin; /* PHY IRQ */
u8 is_rmii; /* using RMII interface? */
};
extern void __init at91_add_device_eth(struct at91_eth_data *data);
#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263)
#define eth_platform_data at91_eth_data
#endif
/* USB Host */
struct at91_usbh_data {
u8 ports; /* number of ports on root hub */
u8 vbus_pin[]; /* port power-control pin */
};
extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
/* NAND / SmartMedia */
struct at91_nand_data {
u8 enable_pin; /* chip enable */
u8 det_pin; /* card detect */
u8 rdy_pin; /* ready/busy */
u8 ale; /* address line number connected to ALE */
u8 cle; /* address line number connected to CLE */
u8 bus_width_16; /* buswidth is 16 bit */
struct mtd_partition* (*partition_info)(int, int*);
};
extern void __init at91_add_device_nand(struct at91_nand_data *data);
/* I2C*/
extern void __init at91_add_device_i2c(void);
/* SPI */
extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
/* Serial */
struct at91_uart_config {
unsigned short console_tty; /* tty number of serial console */
unsigned short nr_tty; /* number of serial tty's */
short tty_map[]; /* map UART to tty number */
};
extern struct platform_device *atmel_default_console_device;
extern void __init at91_init_serial(struct at91_uart_config *config);
struct atmel_uart_data {
short use_dma_tx; /* use transmit DMA? */
short use_dma_rx; /* use receive DMA? */
void __iomem *regs; /* virtual base address, if any */
};
extern void __init at91_add_device_serial(void);
/* LEDs */
extern u8 at91_leds_cpu;
extern u8 at91_leds_timer;
extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
#endif

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/*
* include/asm-arm/arch-at91/cpu.h
*
* Copyright (C) 2006 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_CPU_H
#define __ASM_ARCH_CPU_H
#include <asm/hardware.h>
#include <asm/arch/at91_dbgu.h>
#define ARCH_ID_AT91RM9200 0x09290780
#define ARCH_ID_AT91SAM9260 0x019803a0
#define ARCH_ID_AT91SAM9261 0x019703a0
#define ARCH_ID_AT91SAM9263 0x019607a0
#define ARCH_ID_AT91SAM9XE128 0x329973a0
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
static inline unsigned long at91_cpu_identify(void)
{
return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
}
#define ARCH_FAMILY_AT91X92 0x09200000
#define ARCH_FAMILY_AT91SAM9 0x01900000
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
static inline unsigned long at91_arch_identify(void)
{
return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH);
}
#ifdef CONFIG_ARCH_AT91RM9200
#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
#else
#define cpu_is_at91rm9200() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9260
#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE)
#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe())
#else
#define cpu_is_at91sam9xe() (0)
#define cpu_is_at91sam9260() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9261
#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
#else
#define cpu_is_at91sam9261() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9263
#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
#else
#define cpu_is_at91sam9263() (0)
#endif
#endif

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/*
* include/asm-arm/arch-at91/debug-macro.S
*
* Copyright (C) 2003-2005 SAN People
*
* Debugging macro include header
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <asm/hardware.h>
#include <asm/arch/at91_dbgu.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
ldrne \rx, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register
tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register
tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
beq 1001b
.endm

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/*
* include/asm-arm/arch-at91/dma.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/

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/*
* include/asm-arm/arch-at91/entry-macro.S
*
* Copyright (C) 2003-2005 SAN People
*
* Low-level IRQ helper macros for AT91RM9200 platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware.h>
#include <asm/arch/at91_aic.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number
teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now.
.endm

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/*
* include/asm-arm/arch-at91/gpio.h
*
* Copyright (C) 2005 HP Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
#define __ASM_ARCH_AT91RM9200_GPIO_H
#include <asm/irq.h>
#define PIN_BASE NR_AIC_IRQS
#define MAX_GPIO_BANKS 5
/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0)
#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1)
#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0)
#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1)
#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2)
#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3)
#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4)
#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5)
#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6)
#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7)
#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8)
#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9)
#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10)
#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11)
#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12)
#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13)
#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14)
#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15)
#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16)
#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17)
#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18)
#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19)
#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20)
#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21)
#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22)
#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23)
#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24)
#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25)
#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26)
#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27)
#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28)
#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29)
#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30)
#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31)
#ifndef __ASSEMBLY__
/* setup setup routines, called from board init or driver probe() */
extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
/* callable at any time */
extern int at91_set_gpio_value(unsigned pin, int value);
extern int at91_get_gpio_value(unsigned pin);
/* callable only from core power-management code */
extern void at91_gpio_suspend(void);
extern void at91_gpio_resume(void);
/*-------------------------------------------------------------------------*/
/* wrappers for "new style" GPIO calls. the old AT91-specfic ones should
* eventually be removed (along with this errno.h inclusion), and the
* gpio request/free calls should probably be implemented.
*/
#include <asm/errno.h>
static inline int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
static inline void gpio_free(unsigned gpio)
{
}
extern int gpio_direction_input(unsigned gpio);
extern int gpio_direction_output(unsigned gpio, int value);
static inline int gpio_get_value(unsigned gpio)
{
return at91_get_gpio_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
at91_set_gpio_value(gpio, value);
}
#include <asm-generic/gpio.h> /* cansleep wrappers */
static inline int gpio_to_irq(unsigned gpio)
{
return gpio;
}
static inline int irq_to_gpio(unsigned irq)
{
return irq;
}
#endif /* __ASSEMBLY__ */
#endif

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/*
* include/asm-arm/arch-at91/hardware.h
*
* Copyright (C) 2003 SAN People
* Copyright (C) 2003 ATMEL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#if defined(CONFIG_ARCH_AT91RM9200)
#include <asm/arch/at91rm9200.h>
#elif defined(CONFIG_ARCH_AT91SAM9260)
#include <asm/arch/at91sam9260.h>
#elif defined(CONFIG_ARCH_AT91SAM9261)
#include <asm/arch/at91sam9261.h>
#elif defined(CONFIG_ARCH_AT91SAM9263)
#include <asm/arch/at91sam9263.h>
#else
#error "Unsupported AT91 processor"
#endif
/*
* Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
* to 0xFEF78000 .. 0xFF000000. (544Kb)
*/
#define AT91_IO_PHYS_BASE 0xFFF78000
#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE)
/* Convert a physical IO address to virtual IO address */
#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
/*
* Virtual to Physical Address mapping for IO devices.
*/
#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
/* Internal SRAM is mapped below the IO devices */
#define AT91_SRAM_MAX SZ_1M
#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
/* Serial ports */
#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */
/* External Memory Map */
#define AT91_CHIPSELECT_0 0x10000000
#define AT91_CHIPSELECT_1 0x20000000
#define AT91_CHIPSELECT_2 0x30000000
#define AT91_CHIPSELECT_3 0x40000000
#define AT91_CHIPSELECT_4 0x50000000
#define AT91_CHIPSELECT_5 0x60000000
#define AT91_CHIPSELECT_6 0x70000000
#define AT91_CHIPSELECT_7 0x80000000
/* SDRAM */
#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
/* Clocks */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#ifndef __ASSEMBLY__
#include <asm/io.h>
static inline unsigned int at91_sys_read(unsigned int reg_offset)
{
void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
return __raw_readl(addr + reg_offset);
}
static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
{
void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
__raw_writel(value, addr + reg_offset);
}
#endif
#endif

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/*
* include/asm-arm/arch-at91/io.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <asm/io.h>
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#endif

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/*
* include/asm-arm/arch-at91/irqs.h
*
* Copyright (C) 2004 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#include <asm/arch/at91_aic.h>
#define NR_AIC_IRQS 32
/*
* Acknowledge interrupt with AIC after interrupt has been handled.
* (by kernel/irq.c)
*/
#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
/*
* IRQ interrupt symbols are the AT91xxx_ID_* symbols
* for IRQs handled directly through the AIC, or else the AT91_PIN_*
* symbols in gpio.h for ones handled indirectly as GPIOs.
* We make provision for 5 banks of GPIO.
*/
#define NR_IRQS (NR_AIC_IRQS + (5 * 32))
#endif

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/*
* include/asm-arm/arch-at91/memory.h
*
* Copyright (C) 2004 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <asm/hardware.h>
#define PHYS_OFFSET (AT91_SDRAM_BASE)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif

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/*
* include/asm-arm/arch-at91/system.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/hardware.h>
#include <asm/arch/at91_st.h>
#include <asm/arch/at91_dbgu.h>
static inline void arch_idle(void)
{
/*
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
*/
// at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
/*
* Set the processor (CP15) into 'Wait for Interrupt' mode.
* Unlike disabling the processor clock via the PMC (above)
* this allows the processor to be woken via JTAG.
*/
cpu_do_idle();
}
void (*at91_arch_reset)(void);
static inline void arch_reset(char mode)
{
/* call the CPU-specific reset function */
if (at91_arch_reset)
(at91_arch_reset)();
}
#endif

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include/asm-arm/arch-at91/timex.h Normal file
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/*
* include/asm-arm/arch-at91/timex.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#include <asm/hardware.h>
#if defined(CONFIG_ARCH_AT91RM9200)
#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
#define AT91SAM9_MASTER_CLOCK 99300000
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
#elif defined(CONFIG_ARCH_AT91SAM9263)
#define AT91SAM9_MASTER_CLOCK 99959500
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
#endif
#endif

56
include/asm-arm/arch-at91/uncompress.h Normal file
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/*
* include/asm-arm/arch-at91/uncompress.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <asm/hardware.h>
#include <asm/arch/at91_dbgu.h>
/*
* The following code assumes the serial port has already been
* initialized by the bootloader. If you didn't setup a port in
* your bootloader then nothing will appear (which might be desired).
*
* This does not append a newline
*/
static void putc(int c)
{
void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY))
barrier();
__raw_writel(c, sys + AT91_DBGU_THR);
}
static inline void flush(void)
{
void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
/* wait for transmission to complete */
while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY))
barrier();
}
#define arch_decomp_setup()
#define arch_decomp_wdog()
#endif

26
include/asm-arm/arch-at91/vmalloc.h Normal file
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/*
* include/asm-arm/arch-at91/vmalloc.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK)
#endif

33
include/asm-arm/arch-cl7500/acornfb.h Normal file
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#define acornfb_valid_pixrate(var) (var->pixclock >= 39325 && var->pixclock <= 40119)
static inline void
acornfb_vidc20_find_rates(struct vidc_timing *vidc,
struct fb_var_screeninfo *var)
{
u_int bandwidth;
vidc->control |= VIDC20_CTRL_PIX_CK;
/* Calculate bandwidth */
bandwidth = var->pixclock * 8 / var->bits_per_pixel;
/* Encode bandwidth as VIDC20 setting */
if (bandwidth > 16667*2)
vidc->control |= VIDC20_CTRL_FIFO_16;
else if (bandwidth > 13333*2)
vidc->control |= VIDC20_CTRL_FIFO_20;
else if (bandwidth > 11111*2)
vidc->control |= VIDC20_CTRL_FIFO_24;
else
vidc->control |= VIDC20_CTRL_FIFO_28;
vidc->pll_ctl = 0x2020;
}
#ifdef CONFIG_CHRONTEL_7003
#define acornfb_default_control() VIDC20_CTRL_PIX_HCLK
#else
#define acornfb_default_control() VIDC20_CTRL_PIX_VCLK
#endif
#define acornfb_default_econtrol() VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3) | VIDC20_ECTL_ECK

21
include/asm-arm/arch-cl7500/debug-macro.S Normal file
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/* linux/include/asm-arm/arch-cl7500/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
.macro addruart,rx
mov \rx, #0xe0000000
orr \rx, \rx, #0x00010000
orr \rx, \rx, #0x00000be0
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

21
include/asm-arm/arch-cl7500/dma.h Normal file
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/*
* linux/include/asm-arm/arch-cl7500/dma.h
*
* Copyright (C) 1999 Nexus Electronics Ltd.
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
/*
* This is the maximum DMA address that can be DMAd to.
* There should not be more than (0xd0000000 - 0xc0000000)
* bytes of RAM.
*/
#define MAX_DMA_ADDRESS 0xd0000000
#define DMA_S0 0
#endif /* _ASM_ARCH_DMA_H */

8
include/asm-arm/arch-cl7500/entry-macro.S Normal file
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#include <asm/hardware.h>
#include <asm/hardware/entry-macro-iomd.S>
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm

67
include/asm-arm/arch-cl7500/hardware.h Normal file
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/*
* linux/include/asm-arm/arch-cl7500/hardware.h
*
* Copyright (C) 1996-1999 Russell King.
* Copyright (C) 1999 Nexus Electronics Ltd.
*
* This file contains the hardware definitions of the
* CL7500 evaluation board.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/arch/memory.h>
#include <asm/hardware/iomd.h>
#ifdef __ASSEMBLY__
#define IOMEM(x) x
#else
#define IOMEM(x) ((void __iomem *)(x))
#endif
/*
* What hardware must be present
*/
#define HAS_IOMD
#define HAS_VIDC20
/* Hardware addresses of major areas.
* *_START is the physical address
* *_SIZE is the size of the region
* *_BASE is the virtual address
*/
#define IO_START 0x03000000 /* I/O */
#define IO_SIZE 0x01000000
#define IO_BASE IOMEM(0xe0000000)
#define ISA_START 0x0c000000 /* ISA */
#define ISA_SIZE 0x00010000
#define ISA_BASE 0xe1000000
#define FLASH_START 0x01000000 /* XXX */
#define FLASH_SIZE 0x01000000
#define FLASH_BASE 0xe2000000
#define LED_START 0x0302B000
#define LED_SIZE 0x00001000
#define LED_BASE 0xe3000000
#define LED_ADDRESS (LED_BASE + 0xa00)
/* Let's define SCREEN_START for CL7500, even though it's a lie. */
#define SCREEN_START 0x02000000 /* VRAM */
#define SCREEN_END 0xdfc00000
#define SCREEN_BASE 0xdf800000
#define VIDC_BASE (void __iomem *)0xe0400000
#define IOMD_BASE IOMEM(0xe0200000)
#define IOC_BASE IOMEM(0xe0200000)
#define FLOPPYDMA_BASE IOMEM(0xe002a000)
#define PCIO_BASE IOMEM(0xe0010000)
#define vidc_writel(val) __raw_writel(val, VIDC_BASE)
/* in/out bias for the ISA slot region */
#define ISASLOT_IO 0x80400000
#endif

255
include/asm-arm/arch-cl7500/io.h Normal file
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/*
* linux/include/asm-arm/arch-cl7500/io.h
* from linux/include/asm-arm/arch-rpc/io.h
*
* Copyright (C) 1997 Russell King
*
* Modifications:
* 06-Dec-1997 RMK Created.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
* GCC is totally crap at loading/storing data. We try to persuade it
* to do the right thing by using these whereever possible instead of
* the above.
*/
#define __arch_base_getb(b,o) \
({ \
unsigned int v, r = (b); \
__asm__ __volatile__( \
"ldrb %0, [%1, %2]" \
: "=r" (v) \
: "r" (r), "Ir" (o)); \
v; \
})
#define __arch_base_getl(b,o) \
({ \
unsigned int v, r = (b); \
__asm__ __volatile__( \
"ldr %0, [%1, %2]" \
: "=r" (v) \
: "r" (r), "Ir" (o)); \
v; \
})
#define __arch_base_putb(v,b,o) \
({ \
unsigned int r = (b); \
__asm__ __volatile__( \
"strb %0, [%1, %2]" \
: \
: "r" (v), "r" (r), "Ir" (o)); \
})
#define __arch_base_putl(v,b,o) \
({ \
unsigned int r = (b); \
__asm__ __volatile__( \
"str %0, [%1, %2]" \
: \
: "r" (v), "r" (r), "Ir" (o)); \
})
/*
* We use two different types of addressing - PC style addresses, and ARM
* addresses. PC style accesses the PC hardware with the normal PC IO
* addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+
* and are translated to the start of IO. Note that all addresses are
* shifted left!
*/
#define __PORT_PCIO(x) (!((x) & 0x80000000))
/*
* Dynamic IO functions - let the compiler
* optimize the expressions
*/
static inline void __outb (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
"tst %2, #0x80000000\n\t"
"mov %0, %4\n\t"
"addeq %0, %0, %3\n\t"
"strb %1, [%0, %2, lsl #2] @ outb"
: "=&r" (temp)
: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
: "cc");
}
static inline void __outw (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
"tst %2, #0x80000000\n\t"
"mov %0, %4\n\t"
"addeq %0, %0, %3\n\t"
"str %1, [%0, %2, lsl #2] @ outw"
: "=&r" (temp)
: "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
: "cc");
}
static inline void __outl (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
"tst %2, #0x80000000\n\t"
"mov %0, %4\n\t"
"addeq %0, %0, %3\n\t"
"str %1, [%0, %2, lsl #2] @ outl"
: "=&r" (temp)
: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
: "cc");
}
#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
static inline unsigned sz __in##fnsuffix (unsigned int port) \
{ \
unsigned long temp, value; \
__asm__ __volatile__( \
"tst %2, #0x80000000\n\t" \
"mov %0, %4\n\t" \
"addeq %0, %0, %3\n\t" \
"ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \
: "=&r" (temp), "=r" (value) \
: "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \
: "cc"); \
return (unsigned sz)value; \
}
static inline unsigned int __ioaddr (unsigned int port) \
{ \
if (__PORT_PCIO(port)) \
return (unsigned int)(PCIO_BASE + (port << 2)); \
else \
return (unsigned int)(IO_BASE + (port << 2)); \
}
#define DECLARE_IO(sz,fnsuffix,instr) \
DECLARE_DYN_IN(sz,fnsuffix,instr)
DECLARE_IO(char,b,"b")
DECLARE_IO(short,w,"")
DECLARE_IO(int,l,"")
#undef DECLARE_IO
#undef DECLARE_DYN_IN
/*
* Constant address IO functions
*
* These have to be macros for the 'J' constraint to work -
* +/-4096 immediate operand.
*/
#define __outbc(value,port) \
({ \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"strb %0, [%1, %2] @ outbc" \
: : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
else \
__asm__ __volatile__( \
"strb %0, [%1, %2] @ outbc" \
: : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \
})
#define __inbc(port) \
({ \
unsigned char result; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"ldrb %0, [%1, %2] @ inbc" \
: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
else \
__asm__ __volatile__( \
"ldrb %0, [%1, %2] @ inbc" \
: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
result; \
})
#define __outwc(value,port) \
({ \
unsigned long v = value; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"str %0, [%1, %2] @ outwc" \
: : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
else \
__asm__ __volatile__( \
"str %0, [%1, %2] @ outwc" \
: : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \
})
#define __inwc(port) \
({ \
unsigned short result; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"ldr %0, [%1, %2] @ inwc" \
: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
else \
__asm__ __volatile__( \
"ldr %0, [%1, %2] @ inwc" \
: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
result & 0xffff; \
})
#define __outlc(value,port) \
({ \
unsigned long v = value; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"str %0, [%1, %2] @ outlc" \
: : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
else \
__asm__ __volatile__( \
"str %0, [%1, %2] @ outlc" \
: : "r" (v), "r" (IO_BASE), "r" ((port) << 2)); \
})
#define __inlc(port) \
({ \
unsigned long result; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"ldr %0, [%1, %2] @ inlc" \
: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
else \
__asm__ __volatile__( \
"ldr %0, [%1, %2] @ inlc" \
: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
result; \
})
#define __ioaddrc(port) \
(__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2))
#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
/* the following macro is deprecated */
#define ioaddr(port) __ioaddr((port))
#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
/*
* 1:1 mapping for ioremapped regions.
*/
#define __mem_pci(x) (x)
#endif

32
include/asm-arm/arch-cl7500/irq.h Normal file
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/*
* include/asm-arm/arch-cl7500/irq.h
*
* Copyright (C) 1996 Russell King
* Copyright (C) 1999, 2001 Nexus Electronics Ltd.
*
* Changelog:
* 10-10-1996 RMK Brought up to date with arch-sa110eval
* 22-08-1998 RMK Restructured IRQ routines
* 11-08-1999 PJB Created ARM7500 version, derived from RiscPC code
*/
#include <asm/hardware/iomd.h>
#include <asm/io.h>
static inline int fixup_irq(unsigned int irq)
{
if (irq == IRQ_ISA) {
int isabits = *((volatile unsigned int *)0xe002b700);
if (isabits == 0) {
printk("Spurious ISA IRQ!\n");
return irq;
}
irq = IRQ_ISA_BASE;
while (!(isabits & 1)) {
irq++;
isabits >>= 1;
}
}
return irq;
}

66
include/asm-arm/arch-cl7500/irqs.h Normal file
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/*
* linux/include/asm-arm/arch-cl7500/irqs.h
*
* Copyright (C) 1999 Nexus Electronics Ltd
*/
#define IRQ_INT2 0
#define IRQ_INT1 2
#define IRQ_VSYNCPULSE 3
#define IRQ_POWERON 4
#define IRQ_TIMER0 5
#define IRQ_TIMER1 6
#define IRQ_FORCE 7
#define IRQ_INT8 8
#define IRQ_ISA 9
#define IRQ_INT6 10
#define IRQ_INT5 11
#define IRQ_INT4 12
#define IRQ_INT3 13
#define IRQ_KEYBOARDTX 14
#define IRQ_KEYBOARDRX 15
#define IRQ_DMA0 16
#define IRQ_DMA1 17
#define IRQ_DMA2 18
#define IRQ_DMA3 19
#define IRQ_DMAS0 20
#define IRQ_DMAS1 21
#define IRQ_IOP0 24
#define IRQ_IOP1 25
#define IRQ_IOP2 26
#define IRQ_IOP3 27
#define IRQ_IOP4 28
#define IRQ_IOP5 29
#define IRQ_IOP6 30
#define IRQ_IOP7 31
#define IRQ_MOUSERX 40
#define IRQ_MOUSETX 41
#define IRQ_ADC 42
#define IRQ_EVENT1 43
#define IRQ_EVENT2 44
#define IRQ_ISA_BASE 48
#define IRQ_ISA_3 48
#define IRQ_ISA_4 49
#define IRQ_ISA_5 50
#define IRQ_ISA_7 51
#define IRQ_ISA_9 52
#define IRQ_ISA_10 53
#define IRQ_ISA_11 54
#define IRQ_ISA_14 55
#define FIQ_INT9 0
#define FIQ_INT5 1
#define FIQ_INT6 4
#define FIQ_INT8 6
#define FIQ_FORCE 7
/*
* This is the offset of the FIQ "IRQ" numbers
*/
#define FIQ_START 64
#define IRQ_TIMER IRQ_TIMER0

35
include/asm-arm/arch-cl7500/memory.h Normal file
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/*
* linux/include/asm-arm/arch-cl7500/memory.h
*
* Copyright (c) 1996,1997,1998 Russell King.
*
* Changelog:
* 20-Oct-1996 RMK Created
* 31-Dec-1997 RMK Fixed definitions to reduce warnings
* 11-Jan-1998 RMK Uninlined to reduce hits on cache
* 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt
* 21-Mar-1999 RMK Renamed to memory.h
* RMK Added TASK_SIZE and PAGE_OFFSET
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0x10000000)
/*
* These are exactly the same on the RiscPC as the
* physical memory view.
*/
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
/*
* Cache flushing area - ROM
*/
#define FLUSH_BASE_PHYS 0x00000000
#define FLUSH_BASE 0xdf000000
#endif

23
include/asm-arm/arch-cl7500/system.h Normal file
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/*
* linux/include/asm-arm/arch-cl7500/system.h
*
* Copyright (c) 1999 Nexus Electronics Ltd.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/hardware/iomd.h>
#include <asm/io.h>
static inline void arch_idle(void)
{
iomd_writeb(0, IOMD_SUSMODE);
}
#define arch_reset(mode) \
do { \
iomd_writeb(0, IOMD_ROMCR0); \
cpu_reset(0); \
} while (0)
#endif

13
include/asm-arm/arch-cl7500/timex.h Normal file
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/*
* linux/include/asm-arm/arch-cl7500/timex.h
*
* CL7500 architecture timex specifications
*
* Copyright (C) 1999 Nexus Electronics Ltd
*/
/*
* On the ARM7500, the clock ticks at 2MHz.
*/
#define CLOCK_TICK_RATE 2000000

35
include/asm-arm/arch-cl7500/uncompress.h Normal file
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/*
* linux/include/asm-arm/arch-cl7500/uncompress.h
*
* Copyright (C) 1999, 2000 Nexus Electronics Ltd.
*/
#define BASE 0x03010000
#define SERBASE (BASE + (0x2f8 << 2))
static inline void putc(char c)
{
while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20))
barrier();
*((volatile unsigned int *)(SERBASE)) = c;
}
static inline void flush(void)
{
}
static __inline__ void arch_decomp_setup(void)
{
int baud = 3686400 / (9600 * 32);
*((volatile unsigned int *)(SERBASE + 0xC)) = 0x80;
*((volatile unsigned int *)(SERBASE + 0x0)) = baud & 0xff;
*((volatile unsigned int *)(SERBASE + 0x4)) = (baud & 0xff00) >> 8;
*((volatile unsigned int *)(SERBASE + 0xC)) = 3; /* 8 bits */
*((volatile unsigned int *)(SERBASE + 0x10)) = 3; /* DTR, RTS */
}
/*
* nothing to do
*/
#define arch_decomp_wdog()

4
include/asm-arm/arch-cl7500/vmalloc.h Normal file
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/*
* linux/include/asm-arm/arch-cl7500/vmalloc.h
*/
#define VMALLOC_END (PAGE_OFFSET + 0x1c000000)

78
include/asm-arm/arch-clps711x/autcpu12.h Normal file
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/*
* AUTCPU12 specific defines
*
* (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_AUTCPU12_H
#define __ASM_ARCH_AUTCPU12_H
/*
* The CS8900A ethernet chip has its I/O registers wired to chip select 2
* (nCS2). This is the mapping for it.
*/
#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE /* physical */
#define AUTCPU12_VIRT_CS8900A (0xfe000000) /* virtual */
/*
* The flash bank is wired to chip select 0
*/
#define AUTCPU12_PHYS_FLASH CS0_PHYS_BASE /* physical */
/* offset for device specific information structure */
#define AUTCPU12_LCDINFO_OFFS (0x00010000)
/*
* Videomemory is the internal SRAM (CS 6)
*/
#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE
#define AUTCPU12_VIRT_VIDEO (0xfd000000)
/*
* All special IO's are tied to CS1
*/
#define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */
#define AUTCPU12_PHYS_NVRAM CS1_PHYS_BASE +0x02000000 /* physical */
#define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */
#define AUTCPU12_PHYS_SMC CS1_PHYS_BASE +0x06000000 /* physical */
#define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */
#define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */
#define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */
#define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */
/*
* defines for smartmedia card access
*/
#define AUTCPU12_SMC_RDY (1<<2)
#define AUTCPU12_SMC_ALE (1<<3)
#define AUTCPU12_SMC_CLE (1<<4)
#define AUTCPU12_SMC_PORT_OFFSET PBDR
#define AUTCPU12_SMC_SELECT_OFFSET 0x10
/*
* defines for lcd contrast
*/
#define AUTCPU12_DPOT_PORT_OFFSET PEDR
#define AUTCPU12_DPOT_CS (1<<0)
#define AUTCPU12_DPOT_CLK (1<<1)
#define AUTCPU12_DPOT_UD (1<<2)
#endif

46
include/asm-arm/arch-clps711x/debug-macro.S Normal file
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/* linux/include/asm-arm/arch-clps711x/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <asm/hardware/clps7111.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #CLPS7111_PHYS_BASE
movne \rx, #CLPS7111_VIRT_BASE
#ifndef CONFIG_DEBUG_CLPS711X_UART2
add \rx, \rx, #0x0000 @ UART1
#else
add \rx, \rx, #0x1000 @ UART2
#endif
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0x0480] @ UARTDR
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
tst \rd, #1 << 11 @ UBUSYx
bne 1001b
.endm
.macro busyuart,rd,rx
tst \rx, #0x1000 @ UART2 does not have CTS here
bne 1002f
1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
tst \rd, #1 << 8 @ CTS
bne 1001b
1002:
.endm

19
include/asm-arm/arch-clps711x/dma.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/dma.h
*
* Copyright (C) 1997,1998 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/

58
include/asm-arm/arch-clps711x/entry-macro.S Normal file
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/*
* include/asm-arm/arch-clps711x/entry-macro.S
*
* Low-level IRQ helper macros for CLPS711X-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware.h>
#include <asm/hardware/clps7111.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
#error INTSR stride != INTMR stride
#endif
.macro get_irqnr_and_base, irqnr, stat, base, mask
mov \base, #CLPS7111_BASE
ldr \stat, [\base, #INTSR1]
ldr \mask, [\base, #INTMR1]
mov \irqnr, #4
mov \mask, \mask, lsl #16
and \stat, \stat, \mask, lsr #16
movs \stat, \stat, lsr #4
bne 1001f
add \base, \base, #INTSR2 - INTSR1
ldr \stat, [\base, #INTSR1]
ldr \mask, [\base, #INTMR1]
mov \irqnr, #16
mov \mask, \mask, lsl #16
and \stat, \stat, \mask, lsr #16
1001: tst \stat, #255
addeq \irqnr, \irqnr, #8
moveq \stat, \stat, lsr #8
tst \stat, #15
addeq \irqnr, \irqnr, #4
moveq \stat, \stat, lsr #4
tst \stat, #3
addeq \irqnr, \irqnr, #2
moveq \stat, \stat, lsr #2
tst \stat, #1
addeq \irqnr, \irqnr, #1
moveq \stat, \stat, lsr #1
tst \stat, #1 @ bit 0 should be set
.endm

237
include/asm-arm/arch-clps711x/hardware.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/hardware.h
*
* This file contains the hardware definitions of the Prospector P720T.
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#define CLPS7111_VIRT_BASE 0xff000000
#define CLPS7111_BASE CLPS7111_VIRT_BASE
/*
* The physical addresses that the external chip select signals map to is
* dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
* processors. CONFIG_EP72XX_BOOT_ROM is only available if these
* processors are in use.
*/
#ifndef CONFIG_EP72XX_ROM_BOOT
#define CS0_PHYS_BASE (0x00000000)
#define CS1_PHYS_BASE (0x10000000)
#define CS2_PHYS_BASE (0x20000000)
#define CS3_PHYS_BASE (0x30000000)
#define CS4_PHYS_BASE (0x40000000)
#define CS5_PHYS_BASE (0x50000000)
#define CS6_PHYS_BASE (0x60000000)
#define CS7_PHYS_BASE (0x70000000)
#else
#define CS0_PHYS_BASE (0x70000000)
#define CS1_PHYS_BASE (0x60000000)
#define CS2_PHYS_BASE (0x50000000)
#define CS3_PHYS_BASE (0x40000000)
#define CS4_PHYS_BASE (0x30000000)
#define CS5_PHYS_BASE (0x20000000)
#define CS6_PHYS_BASE (0x10000000)
#define CS7_PHYS_BASE (0x00000000)
#endif
#if defined (CONFIG_ARCH_EP7211)
#define EP7211_VIRT_BASE CLPS7111_VIRT_BASE
#define EP7211_BASE CLPS7111_VIRT_BASE
#include <asm/hardware/ep7211.h>
#elif defined (CONFIG_ARCH_EP7212)
#define EP7212_VIRT_BASE CLPS7111_VIRT_BASE
#define EP7212_BASE CLPS7111_VIRT_BASE
#include <asm/hardware/ep7212.h>
#endif
#define SYSPLD_VIRT_BASE 0xfe000000
#define SYSPLD_BASE SYSPLD_VIRT_BASE
#ifndef __ASSEMBLER__
#define PCIO_BASE IO_BASE
#endif
#if defined (CONFIG_ARCH_AUTCPU12)
#define CS89712_VIRT_BASE CLPS7111_VIRT_BASE
#define CS89712_BASE CLPS7111_VIRT_BASE
#include <asm/hardware/clps7111.h>
#include <asm/hardware/ep7212.h>
#include <asm/hardware/cs89712.h>
#endif
#if defined (CONFIG_ARCH_CDB89712)
#include <asm/hardware/clps7111.h>
#include <asm/hardware/ep7212.h>
#include <asm/hardware/cs89712.h>
/* dynamic ioremap() areas */
#define FLASH_START 0x00000000
#define FLASH_SIZE 0x800000
#define FLASH_WIDTH 4
#define SRAM_START 0x60000000
#define SRAM_SIZE 0xc000
#define SRAM_WIDTH 4
#define BOOTROM_START 0x70000000
#define BOOTROM_SIZE 0x80
#define BOOTROM_WIDTH 4
/* static cdb89712_map_io() areas */
#define REGISTER_START 0x80000000
#define REGISTER_SIZE 0x4000
#define REGISTER_BASE 0xff000000
#define ETHER_START 0x20000000
#define ETHER_SIZE 0x1000
#define ETHER_BASE 0xfe000000
#endif
#if defined (CONFIG_ARCH_EDB7211)
/*
* The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
* and repeat across it. This is the mapping for it.
*
* In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
* was cause for much consternation and headscratching. This should probably
* be made a compile/run time kernel option.
*/
#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */
#define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */
/*
* The CS8900A ethernet chip has its I/O registers wired to chip select 2
* (nCS2). This is the mapping for it.
*
* In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
* was cause for much consternation and headscratching. This should probably
* be made a compile/run time kernel option.
*/
#define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */
#define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */
/*
* The two flash banks are wired to chip selects 0 and 1. This is the mapping
* for them.
*
* nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
* in jumpered boot mode.
*/
#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
#define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */
#define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */
#endif /* CONFIG_ARCH_EDB7211 */
/*
* Relevant bits in port D, which controls power to the various parts of
* the LCD on the EDB7211.
*/
#define EDB_PD1_LCD_DC_DC_EN (1<<1)
#define EDB_PD2_LCDEN (1<<2)
#define EDB_PD3_LCDBL (1<<3)
#if defined (CONFIG_ARCH_CEIVA)
#define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE
#define CEIVA_BASE CLPS7111_VIRT_BASE
#include <asm/hardware/clps7111.h>
#include <asm/hardware/ep7212.h>
/*
* The two flash banks are wired to chip selects 0 and 1. This is the mapping
* for them.
*
* nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
* in jumpered boot mode.
*/
#define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
#define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
#define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */
#define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */
#define CEIVA_FLASH_SIZE 0x100000
#define CEIVA_FLASH_WIDTH 2
#define SRAM_START 0x60000000
#define SRAM_SIZE 0xc000
#define SRAM_WIDTH 4
#define BOOTROM_START 0x70000000
#define BOOTROM_SIZE 0x80
#define BOOTROM_WIDTH 4
/*
* SED1355 LCD controller
*/
#define CEIVA_PHYS_SED1355 CS2_PHYS_BASE
#define CEIVA_VIRT_SED1355 (0xfc000000)
/*
* Relevant bits in port D, which controls power to the various parts of
* the LCD on the Ceiva Photo Max, and reset to the LCD controller.
*/
// Reset line to SED1355 (must be high to operate)
#define CEIVA_PD1_LCDRST (1<<1)
// LCD panel enable (set to one, to enable LCD)
#define CEIVA_PD4_LCDEN (1<<4)
// Backlight (set to one, to turn on backlight
#define CEIVA_PD5_LCDBL (1<<5)
/*
* Relevant bits in port B, which report the status of the buttons.
*/
// White button
#define CEIVA_PB4_WHT_BTN (1<<4)
// Black button
#define CEIVA_PB0_BLK_BTN (1<<0)
#endif // #if defined (CONFIG_ARCH_CEIVA)
#endif

38
include/asm-arm/arch-clps711x/io.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/io.h
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
/*
* We don't support ins[lb]/outs[lb]. Make them fault.
*/
#define __raw_readsb(p,d,l) do { *(int *)0 = 0; } while (0)
#define __raw_readsl(p,d,l) do { *(int *)0 = 0; } while (0)
#define __raw_writesb(p,d,l) do { *(int *)0 = 0; } while (0)
#define __raw_writesl(p,d,l) do { *(int *)0 = 0; } while (0)
#endif

53
include/asm-arm/arch-clps711x/irqs.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/irqs.h
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Interrupts from INTSR1
*/
#define IRQ_CSINT 4
#define IRQ_EINT1 5
#define IRQ_EINT2 6
#define IRQ_EINT3 7
#define IRQ_TC1OI 8
#define IRQ_TC2OI 9
#define IRQ_RTCMI 10
#define IRQ_TINT 11
#define IRQ_UTXINT1 12
#define IRQ_URXINT1 13
#define IRQ_UMSINT 14
#define IRQ_SSEOTI 15
#define INT1_IRQS (0x0000fff0)
#define INT1_ACK_IRQS (0x00004f10)
/*
* Interrupts from INTSR2
*/
#define IRQ_KBDINT (16+0) /* bit 0 */
#define IRQ_SS2RX (16+1) /* bit 1 */
#define IRQ_SS2TX (16+2) /* bit 2 */
#define IRQ_UTXINT2 (16+12) /* bit 12 */
#define IRQ_URXINT2 (16+13) /* bit 13 */
#define INT2_IRQS (0x30070000)
#define INT2_ACK_IRQS (0x00010000)
#define NR_IRQS 30

94
include/asm-arm/arch-clps711x/memory.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/memory.h
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0xc0000000)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
#if defined(CONFIG_ARCH_CDB89712)
#define __virt_to_bus(x) (x)
#define __bus_to_virt(x) (x)
#elif defined (CONFIG_ARCH_AUTCPU12)
#define __virt_to_bus(x) (x)
#define __bus_to_virt(x) (x)
#else
#define __virt_to_bus(x) ((x) - PAGE_OFFSET)
#define __bus_to_virt(x) ((x) + PAGE_OFFSET)
#endif
/*
* Like the SA1100, the EDB7211 has a large gap between physical RAM
* banks. In 2.2, the Psion (CL-PS7110) port added custom support for
* discontiguous physical memory. In 2.4, we can use the standard
* Linux NUMA support.
*
* This is not necessary for EP7211 implementations with only one used
* memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM.
*/
/*
* The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
* uses only one of the two banks (bank #1). However, even within
* bank #1, memory is discontiguous.
*
* The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
* them, so we use 24 for the node max shift to get 16MB node sizes.
*/
/*
* Because of the wide memory address space between physical RAM banks on the
* SA1100, it's much more convenient to use Linux's NUMA support to implement
* our memory map representation. Assuming all memory nodes have equal access
* characteristics, we then have generic discontiguous memory support.
*
* Of course, all this isn't mandatory for SA1100 implementations with only
* one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM.
*
* The nodes are matched with the physical memory bank addresses which are
* incidentally the same as virtual addresses.
*
* node 0: 0xc0000000 - 0xc7ffffff
* node 1: 0xc8000000 - 0xcfffffff
* node 2: 0xd0000000 - 0xd7ffffff
* node 3: 0xd8000000 - 0xdfffffff
*/
#define NODE_MEM_SIZE_BITS 24
#endif

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include/asm-arm/arch-clps711x/syspld.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/syspld.h
*
* System Control PLD register definitions.
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSPLD_H
#define __ASM_ARCH_SYSPLD_H
#define SYSPLD_PHYS_BASE (0x10000000)
#ifndef __ASSEMBLY__
#include <asm/types.h>
#define SYSPLD_REG(type,off) (*(volatile type *)(SYSPLD_BASE + off))
#else
#define SYSPLD_REG(type,off) (off)
#endif
#define PLD_INT SYSPLD_REG(u32, 0x000000)
#define PLD_INT_PENIRQ (1 << 5)
#define PLD_INT_UCB_IRQ (1 << 1)
#define PLD_INT_KBD_ATN (1 << 0) /* EINT1 */
#define PLD_PWR SYSPLD_REG(u32, 0x000004)
#define PLD_PWR_EXT (1 << 5)
#define PLD_PWR_MODE (1 << 4) /* 1 = PWM, 0 = PFM */
#define PLD_S4_ON (1 << 3) /* LCD bias voltage enable */
#define PLD_S3_ON (1 << 2) /* LCD backlight enable */
#define PLD_S2_ON (1 << 1) /* LCD 3V3 supply enable */
#define PLD_S1_ON (1 << 0) /* LCD 3V supply enable */
#define PLD_KBD SYSPLD_REG(u32, 0x000008)
#define PLD_KBD_WAKE (1 << 1)
#define PLD_KBD_EN (1 << 0)
#define PLD_SPI SYSPLD_REG(u32, 0x00000c)
#define PLD_SPI_EN (1 << 0)
#define PLD_IO SYSPLD_REG(u32, 0x000010)
#define PLD_IO_BOOTSEL (1 << 6) /* boot sel switch */
#define PLD_IO_USER (1 << 5) /* user defined switch */
#define PLD_IO_LED3 (1 << 4)
#define PLD_IO_LED2 (1 << 3)
#define PLD_IO_LED1 (1 << 2)
#define PLD_IO_LED0 (1 << 1)
#define PLD_IO_LEDEN (1 << 0)
#define PLD_IRDA SYSPLD_REG(u32, 0x000014)
#define PLD_IRDA_EN (1 << 0)
#define PLD_COM2 SYSPLD_REG(u32, 0x000018)
#define PLD_COM2_EN (1 << 0)
#define PLD_COM1 SYSPLD_REG(u32, 0x00001c)
#define PLD_COM1_EN (1 << 0)
#define PLD_AUD SYSPLD_REG(u32, 0x000020)
#define PLD_AUD_DIV1 (1 << 6)
#define PLD_AUD_DIV0 (1 << 5)
#define PLD_AUD_CLK_SEL1 (1 << 4)
#define PLD_AUD_CLK_SEL0 (1 << 3)
#define PLD_AUD_MIC_PWR (1 << 2)
#define PLD_AUD_MIC_GAIN (1 << 1)
#define PLD_AUD_CODEC_EN (1 << 0)
#define PLD_CF SYSPLD_REG(u32, 0x000024)
#define PLD_CF2_SLEEP (1 << 5)
#define PLD_CF1_SLEEP (1 << 4)
#define PLD_CF2_nPDREQ (1 << 3)
#define PLD_CF1_nPDREQ (1 << 2)
#define PLD_CF2_nIRQ (1 << 1)
#define PLD_CF1_nIRQ (1 << 0)
#define PLD_SDC SYSPLD_REG(u32, 0x000028)
#define PLD_SDC_INT_EN (1 << 2)
#define PLD_SDC_WP (1 << 1)
#define PLD_SDC_CD (1 << 0)
#define PLD_FPGA SYSPLD_REG(u32, 0x00002c)
#define PLD_CODEC SYSPLD_REG(u32, 0x400000)
#define PLD_CODEC_IRQ3 (1 << 4)
#define PLD_CODEC_IRQ2 (1 << 3)
#define PLD_CODEC_IRQ1 (1 << 2)
#define PLD_CODEC_EN (1 << 0)
#define PLD_BRITE SYSPLD_REG(u32, 0x400004)
#define PLD_BRITE_UP (1 << 1)
#define PLD_BRITE_DN (1 << 0)
#define PLD_LCDEN SYSPLD_REG(u32, 0x400008)
#define PLD_LCDEN_EN (1 << 0)
#define PLD_ID SYSPLD_REG(u32, 0x40000c)
#define PLD_TCH SYSPLD_REG(u32, 0x400010)
#define PLD_TCH_PENIRQ (1 << 1)
#define PLD_TCH_EN (1 << 0)
#define PLD_GPIO SYSPLD_REG(u32, 0x400014)
#define PLD_GPIO2 (1 << 2)
#define PLD_GPIO1 (1 << 1)
#define PLD_GPIO0 (1 << 0)
#endif

40
include/asm-arm/arch-clps711x/system.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/system.h
*
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/hardware.h>
#include <asm/hardware/clps7111.h>
#include <asm/io.h>
static inline void arch_idle(void)
{
clps_writel(1, HALT);
__asm__ __volatile__(
"mov r0, r0\n\
mov r0, r0");
}
static inline void arch_reset(char mode)
{
cpu_reset(0);
}
#endif

49
include/asm-arm/arch-clps711x/time.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/time.h
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <asm/leds.h>
#include <asm/hardware/clps7111.h>
extern void clps711x_setup_timer(void);
/*
* IRQ handler for the timer
*/
static irqreturn_t
p720t_timer_interrupt(int irq, void *dev_id)
{
struct pt_regs *regs = get_irq_regs();
do_leds();
do_timer(1);
#ifndef CONFIG_SMP
update_process_times(user_mode(regs));
#endif
do_profile(regs);
return IRQ_HANDLED;
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
void __init time_init(void)
{
clps711x_setup_timer();
timer_irq.handler = p720t_timer_interrupt;
setup_irq(IRQ_TC2OI, &timer_irq);
}

23
include/asm-arm/arch-clps711x/timex.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/timex.h
*
* Prospector 720T architecture timex specifications
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define CLOCK_TICK_RATE 512000

59
include/asm-arm/arch-clps711x/uncompress.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/uncompress.h
*
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <asm/arch/io.h>
#include <asm/hardware.h>
#include <asm/hardware/clps7111.h>
#undef CLPS7111_BASE
#define CLPS7111_BASE CLPS7111_PHYS_BASE
#define __raw_readl(p) (*(unsigned long *)(p))
#define __raw_writel(v,p) (*(unsigned long *)(p) = (v))
#ifdef CONFIG_DEBUG_CLPS711X_UART2
#define SYSFLGx SYSFLG2
#define UARTDRx UARTDR2
#else
#define SYSFLGx SYSFLG1
#define UARTDRx UARTDR1
#endif
/*
* This does not append a newline
*/
static inline void putc(int c)
{
while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
barrier();
clps_writel(c, UARTDRx);
}
static inline void flush(void)
{
while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()

20
include/asm-arm/arch-clps711x/vmalloc.h Normal file
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/*
* linux/include/asm-arm/arch-clps711x/vmalloc.h
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)

21
include/asm-arm/arch-ebsa110/debug-macro.S Normal file
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/* linux/include/asm-arm/arch-ebsa110/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
**/
.macro addruart,rx
mov \rx, #0xf0000000
orr \rx, \rx, #0x00000be0
.endm
#define UART_SHIFT 2
#define FLOW_CONTROL
#include <asm/hardware/debug-8250.S>

11
include/asm-arm/arch-ebsa110/dma.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa110/dma.h
*
* Copyright (C) 1997,1998 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* EBSA110 DMA definitions
*/

39
include/asm-arm/arch-ebsa110/entry-macro.S Normal file
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/*
* include/asm-arm/arch-ebsa110/entry-macro.S
*
* Low-level IRQ helper macros for ebsa110 platform.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define IRQ_STAT 0xff000000 /* read */
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, stat, base, tmp
mov \base, #IRQ_STAT
ldrb \stat, [\base] @ get interrupts
mov \irqnr, #0
tst \stat, #15
addeq \irqnr, \irqnr, #4
moveq \stat, \stat, lsr #4
tst \stat, #3
addeq \irqnr, \irqnr, #2
moveq \stat, \stat, lsr #2
tst \stat, #1
addeq \irqnr, \irqnr, #1
moveq \stat, \stat, lsr #1
tst \stat, #1 @ bit 0 should be set
.endm

63
include/asm-arm/arch-ebsa110/hardware.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa110/hardware.h
*
* Copyright (C) 1996-2000 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This file contains the hardware definitions of the EBSA-110.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/*
* The EBSA110 has a weird "ISA IO" region:
*
* Region 0 (addr = 0xf0000000 + io << 2)
* --------------------------------------------------------
* Physical region IO region
* f0000fe0 - f0000ffc 3f8 - 3ff ttyS0
* f0000e60 - f0000e64 398 - 399
* f0000de0 - f0000dfc 378 - 37f lp0
* f0000be0 - f0000bfc 2f8 - 2ff ttyS1
*
* Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1))
* --------------------------------------------------------
* Physical region IO region
* f00014f1 a79 pnp write data
* f00007c0 - f00007c1 3e0 - 3e1 pcmcia
* f00004f1 279 pnp address
* f0000440 - f000046c 220 - 236 eth0
* f0000405 203 pnp read data
*/
#define ISAMEM_PHYS 0xe0000000
#define ISAMEM_SIZE 0x10000000
#define ISAIO_PHYS 0xf0000000
#define ISAIO_SIZE PGDIR_SIZE
#define TRICK0_PHYS 0xf2000000
#define TRICK1_PHYS 0xf2400000
#define TRICK2_PHYS 0xf2800000
#define TRICK3_PHYS 0xf2c00000
#define TRICK4_PHYS 0xf3000000
#define TRICK5_PHYS 0xf3400000
#define TRICK6_PHYS 0xf3800000
#define TRICK7_PHYS 0xf3c00000
#define ISAMEM_BASE 0xe0000000
#define ISAIO_BASE 0xf0000000
#define PIT_BASE 0xfc000000
#define SOFT_BASE 0xfd000000
/*
* RAM definitions
*/
#define UNCACHEABLE_ADDR 0xff000000 /* IRQ_STAT */
#endif

84
include/asm-arm/arch-ebsa110/io.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa110/io.h
*
* Copyright (C) 1997,1998 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Modifications:
* 06-Dec-1997 RMK Created.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffff
u8 __inb8(unsigned int port);
void __outb8(u8 val, unsigned int port);
u8 __inb16(unsigned int port);
void __outb16(u8 val, unsigned int port);
u16 __inw(unsigned int port);
void __outw(u16 val, unsigned int port);
u32 __inl(unsigned int port);
void __outl(u32 val, unsigned int port);
u8 __readb(const volatile void __iomem *addr);
u16 __readw(const volatile void __iomem *addr);
u32 __readl(const volatile void __iomem *addr);
void __writeb(u8 val, void __iomem *addr);
void __writew(u16 val, void __iomem *addr);
void __writel(u32 val, void __iomem *addr);
/*
* Argh, someone forgot the IOCS16 line. We therefore have to handle
* the byte stearing by selecting the correct byte IO functions here.
*/
#ifdef ISA_SIXTEEN_BIT_PERIPHERAL
#define inb(p) __inb16(p)
#define outb(v,p) __outb16(v,p)
#else
#define inb(p) __inb8(p)
#define outb(v,p) __outb8(v,p)
#endif
#define inw(p) __inw(p)
#define outw(v,p) __outw(v,p)
#define inl(p) __inl(p)
#define outl(v,p) __outl(v,p)
#define readb(b) __readb(b)
#define readw(b) __readw(b)
#define readl(b) __readl(b)
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
#define writeb(v,b) __writeb(v,b)
#define writew(v,b) __writew(v,b)
#define writel(v,b) __writel(v,b)
static inline void __iomem *__arch_ioremap(unsigned long cookie, size_t size,
unsigned int flags)
{
return (void __iomem *)cookie;
}
#define __arch_ioremap __arch_ioremap
#define __arch_iounmap(cookie) do { } while (0)
extern void insb(unsigned int port, void *buf, int sz);
extern void insw(unsigned int port, void *buf, int sz);
extern void insl(unsigned int port, void *buf, int sz);
extern void outsb(unsigned int port, const void *buf, int sz);
extern void outsw(unsigned int port, const void *buf, int sz);
extern void outsl(unsigned int port, const void *buf, int sz);
#endif

20
include/asm-arm/arch-ebsa110/irqs.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa110/irqs.h
*
* Copyright (C) 1996 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define NR_IRQS 8
#define IRQ_EBSA110_PRINTER 0
#define IRQ_EBSA110_COM1 1
#define IRQ_EBSA110_COM2 2
#define IRQ_EBSA110_ETHERNET 3
#define IRQ_EBSA110_TIMER0 4
#define IRQ_EBSA110_TIMER1 5
#define IRQ_EBSA110_PCMCIA 6
#define IRQ_EBSA110_IMMEDIATE 7

37
include/asm-arm/arch-ebsa110/memory.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa110/memory.h
*
* Copyright (C) 1996-1999 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 20-Oct-1996 RMK Created
* 31-Dec-1997 RMK Fixed definitions to reduce warnings
* 21-Mar-1999 RMK Renamed to memory.h
* RMK Moved TASK_SIZE and PAGE_OFFSET here
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0x00000000)
/*
* We keep this 1:1 so that we don't interfere
* with the PCMCIA memory regions
*/
#define __virt_to_bus(x) (x)
#define __bus_to_virt(x) (x)
/*
* Cache flushing area - SRAM
*/
#define FLUSH_BASE_PHYS 0x40000000
#define FLUSH_BASE 0xdf000000
#endif

39
include/asm-arm/arch-ebsa110/system.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa110/system.h
*
* Copyright (C) 1996-2000 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
/*
* EBSA110 idling methodology:
*
* We can not execute the "wait for interrupt" instruction since that
* will stop our MCLK signal (which provides the clock for the glue
* logic, and therefore the timer interrupt).
*
* Instead, we spin, polling the IRQ_STAT register for the occurrence
* of any interrupt with core clock down to the memory clock.
*/
static inline void arch_idle(void)
{
const char *irq_stat = (char *)0xff000000;
/* disable clock switching */
asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
/* wait for an interrupt to occur */
while (!*irq_stat);
/* enable clock switching */
asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
}
#define arch_reset(mode) cpu_reset(0x80000000)
#endif

19
include/asm-arm/arch-ebsa110/timex.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa110/timex.h
*
* Copyright (C) 1997, 1998 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* EBSA110 architecture timex specifications
*/
/*
* On the EBSA, the clock ticks at weird rates.
* This is therefore not used to calculate the
* divisor.
*/
#define CLOCK_TICK_RATE 47894000

45
include/asm-arm/arch-ebsa110/uncompress.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa110/uncompress.h
*
* Copyright (C) 1996,1997,1998 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/serial_reg.h>
#define SERIAL_BASE ((unsigned char *)0xf0000be0)
/*
* This does not append a newline
*/
static inline void putc(int c)
{
unsigned char v, *base = SERIAL_BASE;
do {
v = base[UART_LSR << 2];
barrier();
} while (!(v & UART_LSR_THRE));
base[UART_TX << 2] = c;
}
static inline void flush(void)
{
unsigned char v, *base = SERIAL_BASE;
do {
v = base[UART_LSR << 2];
barrier();
} while ((v & (UART_LSR_TEMT|UART_LSR_THRE)) !=
(UART_LSR_TEMT|UART_LSR_THRE));
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()

10
include/asm-arm/arch-ebsa110/vmalloc.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa110/vmalloc.h
*
* Copyright (C) 1998 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define VMALLOC_END (PAGE_OFFSET + 0x1f000000)

57
include/asm-arm/arch-ebsa285/debug-macro.S Normal file
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/* linux/include/asm-arm/arch-ebsa285/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <asm/hardware/dec21285.h>
#ifndef CONFIG_DEBUG_DC21285_PORT
/* For NetWinder debugging */
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x7c000000 @ physical
movne \rx, #0xff000000 @ virtual
orr \rx, \rx, #0x000003f8
.endm
#define UART_SHIFT 0
#define FLOW_CONTROL
#include <asm/hardware/debug-8250.S>
#else
/* For EBSA285 debugging */
.equ dc21285_high, ARMCSR_BASE & 0xff000000
.equ dc21285_low, ARMCSR_BASE & 0x00ffffff
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x42000000
movne \rx, #dc21285_high
.if dc21285_low
orrne \rx, \rx, #dc21285_low
.endif
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0x160] @ UARTDR
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x178] @ UARTFLG
tst \rd, #1 << 3
bne 1001b
.endm
.macro waituart,rd,rx
.endm
#endif

25
include/asm-arm/arch-ebsa285/dma.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa285/dma.h
*
* Architecture DMA routines
*
* Copyright (C) 1998,1999 Russell King
* Copyright (C) 1998,1999 Philip Blundell
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
/*
* The 21285 has two internal DMA channels; we call these 8 and 9.
* On CATS hardware we have an additional eight ISA dma channels
* numbered 0..7.
*/
#define _ISA_DMA(x) (0+(x))
#define _DC21285_DMA(x) (8+(x))
#define MAX_DMA_CHANNELS 10
#define DMA_FLOPPY _ISA_DMA(2)
#define DMA_ISA_CASCADE _ISA_DMA(4)
#endif /* _ASM_ARCH_DMA_H */

113
include/asm-arm/arch-ebsa285/entry-macro.S Normal file
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/*
* include/asm-arm/arch-ebsa285/entry-macro.S
*
* Low-level IRQ helper macros for footbridge-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware.h>
#include <asm/arch/irqs.h>
#include <asm/hardware/dec21285.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.equ dc21285_high, ARMCSR_BASE & 0xff000000
.equ dc21285_low, ARMCSR_BASE & 0x00ffffff
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #dc21285_high
.if dc21285_low
orr r4, r4, #dc21285_low
.endif
ldr \irqstat, [r4, #0x180] @ get interrupts
mov \irqnr, #IRQ_SDRAMPARITY
tst \irqstat, #IRQ_MASK_SDRAMPARITY
bne 1001f
tst \irqstat, #IRQ_MASK_UART_RX
movne \irqnr, #IRQ_CONRX
bne 1001f
tst \irqstat, #IRQ_MASK_DMA1
movne \irqnr, #IRQ_DMA1
bne 1001f
tst \irqstat, #IRQ_MASK_DMA2
movne \irqnr, #IRQ_DMA2
bne 1001f
tst \irqstat, #IRQ_MASK_IN0
movne \irqnr, #IRQ_IN0
bne 1001f
tst \irqstat, #IRQ_MASK_IN1
movne \irqnr, #IRQ_IN1
bne 1001f
tst \irqstat, #IRQ_MASK_IN2
movne \irqnr, #IRQ_IN2
bne 1001f
tst \irqstat, #IRQ_MASK_IN3
movne \irqnr, #IRQ_IN3
bne 1001f
tst \irqstat, #IRQ_MASK_PCI
movne \irqnr, #IRQ_PCI
bne 1001f
tst \irqstat, #IRQ_MASK_DOORBELLHOST
movne \irqnr, #IRQ_DOORBELLHOST
bne 1001f
tst \irqstat, #IRQ_MASK_I2OINPOST
movne \irqnr, #IRQ_I2OINPOST
bne 1001f
tst \irqstat, #IRQ_MASK_TIMER1
movne \irqnr, #IRQ_TIMER1
bne 1001f
tst \irqstat, #IRQ_MASK_TIMER2
movne \irqnr, #IRQ_TIMER2
bne 1001f
tst \irqstat, #IRQ_MASK_TIMER3
movne \irqnr, #IRQ_TIMER3
bne 1001f
tst \irqstat, #IRQ_MASK_UART_TX
movne \irqnr, #IRQ_CONTX
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_ABORT
movne \irqnr, #IRQ_PCI_ABORT
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_SERR
movne \irqnr, #IRQ_PCI_SERR
bne 1001f
tst \irqstat, #IRQ_MASK_DISCARD_TIMER
movne \irqnr, #IRQ_DISCARD_TIMER
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_DPERR
movne \irqnr, #IRQ_PCI_DPERR
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_PERR
movne \irqnr, #IRQ_PCI_PERR
1001:
.endm

131
include/asm-arm/arch-ebsa285/hardware.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa285/hardware.h
*
* Copyright (C) 1998-1999 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This file contains the hardware definitions of the EBSA-285.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/arch/memory.h>
#ifdef CONFIG_ARCH_FOOTBRIDGE
/* Virtual Physical Size
* 0xff800000 0x40000000 1MB X-Bus
* 0xff000000 0x7c000000 1MB PCI I/O space
* 0xfe000000 0x42000000 1MB CSR
* 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
* 0xfc000000 0x79000000 1MB PCI IACK/special space
* 0xfb000000 0x7a000000 16MB PCI Config type 1
* 0xfa000000 0x7b000000 16MB PCI Config type 0
* 0xf9000000 0x50000000 1MB Cache flush
* 0xf0000000 0x80000000 16MB ISA memory
*/
#define XBUS_SIZE 0x00100000
#define XBUS_BASE 0xff800000
#define PCIO_SIZE 0x00100000
#define PCIO_BASE 0xff000000
#define ARMCSR_SIZE 0x00100000
#define ARMCSR_BASE 0xfe000000
#define WFLUSH_SIZE 0x00100000
#define WFLUSH_BASE 0xfd000000
#define PCIIACK_SIZE 0x00100000
#define PCIIACK_BASE 0xfc000000
#define PCICFG1_SIZE 0x01000000
#define PCICFG1_BASE 0xfb000000
#define PCICFG0_SIZE 0x01000000
#define PCICFG0_BASE 0xfa000000
#define PCIMEM_SIZE 0x01000000
#define PCIMEM_BASE 0xf0000000
#elif defined(CONFIG_ARCH_CO285)
/*
* This is the COEBSA285 cut-down mapping
*/
#define PCIMEM_SIZE 0x80000000
#define PCIMEM_BASE 0x80000000
#define WFLUSH_SIZE 0x01000000
#define WFLUSH_BASE 0x7d000000
#define ARMCSR_SIZE 0x00100000
#define ARMCSR_BASE 0x7cf00000
#define XBUS_SIZE 0x00020000
#define XBUS_BASE 0x7cee0000
#define PCIO_SIZE 0x00010000
#define PCIO_BASE 0x7ced0000
#else
#error "Undefined footbridge architecture"
#endif
#define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000))
#define XBUS_LED_AMBER (1 << 0)
#define XBUS_LED_GREEN (1 << 1)
#define XBUS_LED_RED (1 << 2)
#define XBUS_LED_TOGGLE (1 << 8)
#define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000))
#define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15)
#define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4))
#define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5))
#define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6))
#define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108)
/* PIC irq control */
#define PIC_LO 0x20
#define PIC_MASK_LO 0x21
#define PIC_HI 0xA0
#define PIC_MASK_HI 0xA1
/* GPIO pins */
#define GPIO_CCLK 0x800
#define GPIO_DSCLK 0x400
#define GPIO_E2CLK 0x200
#define GPIO_IOLOAD 0x100
#define GPIO_RED_LED 0x080
#define GPIO_WDTIMER 0x040
#define GPIO_DATA 0x020
#define GPIO_IOCLK 0x010
#define GPIO_DONE 0x008
#define GPIO_FAN 0x004
#define GPIO_GREEN_LED 0x002
#define GPIO_RESET 0x001
/* CPLD pins */
#define CPLD_DS_ENABLE 8
#define CPLD_7111_DISABLE 4
#define CPLD_UNMUTE 2
#define CPLD_FLASH_WR_ENABLE 1
#ifndef __ASSEMBLY__
extern void gpio_modify_op(int mask, int set);
extern void gpio_modify_io(int mask, int in);
extern int gpio_read(void);
extern void cpld_modify(int mask, int set);
#endif
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x81000000
#endif

39
include/asm-arm/arch-ebsa285/io.h Normal file
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/*
* linux/include/asm-arm/arch-ebsa285/io.h
*
* Copyright (C) 1997-1999 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Modifications:
* 06-12-1997 RMK Created.
* 07-04-1999 RMK Major cleanup
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffff
/*
* Translation of various region addresses to virtual addresses
*/
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
#if 1
#define __mem_pci(a) (a)
#else
static inline void __iomem *___mem_pci(void __iomem *p)
{
unsigned long a = (unsigned long)p;
BUG_ON(a <= 0xc0000000 || a >= 0xe0000000);
return p;
}
#define __mem_pci(a) ___mem_pci(a)
#endif
#endif

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