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Creation of Cybook 2416 (actually Gen4) repository

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This commit is contained in:
mlt
2009-12-18 17:10:00 +00:00
committed by godzil
commit 76f20f4d40
13791 changed files with 6812321 additions and 0 deletions
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32
include/asm-arm/arch-pxa/akita.h Normal file
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/*
* Hardware specific definitions for SL-C1000 (Akita)
*
* Copyright (c) 2005 Richard Purdie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/* Akita IO Expander GPIOs */
#define AKITA_IOEXP_RESERVED_7 (1 << 7)
#define AKITA_IOEXP_IR_ON (1 << 6)
#define AKITA_IOEXP_AKIN_PULLUP (1 << 5)
#define AKITA_IOEXP_BACKLIGHT_CONT (1 << 4)
#define AKITA_IOEXP_BACKLIGHT_ON (1 << 3)
#define AKITA_IOEXP_MIC_BIAS (1 << 2)
#define AKITA_IOEXP_RESERVED_1 (1 << 1)
#define AKITA_IOEXP_RESERVED_0 (1 << 0)
/* Direction Bitfield 0=output 1=input */
#define AKITA_IOEXP_IO_DIR 0
/* Default Values */
#define AKITA_IOEXP_IO_OUT (AKITA_IOEXP_IR_ON | AKITA_IOEXP_AKIN_PULLUP)
extern struct platform_device akitaioexp_device;
void akita_set_ioexp(struct device *dev, unsigned char bitmask);
void akita_reset_ioexp(struct device *dev, unsigned char bitmask);

16
include/asm-arm/arch-pxa/audio.h Normal file
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#ifndef __ASM_ARCH_AUDIO_H__
#define __ASM_ARCH_AUDIO_H__
#include <sound/driver.h>
#include <sound/core.h>
#include <sound/pcm.h>
typedef struct {
int (*startup)(struct snd_pcm_substream *, void *);
void (*shutdown)(struct snd_pcm_substream *, void *);
void (*suspend)(void *);
void (*resume)(void *);
void *priv;
} pxa2xx_audio_ops_t;
#endif

113
include/asm-arm/arch-pxa/bitfield.h Normal file
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/*
* FILE bitfield.h
*
* Version 1.1
* Author Copyright (c) Marc A. Viredaz, 1998
* DEC Western Research Laboratory, Palo Alto, CA
* Date April 1998 (April 1997)
* System Advanced RISC Machine (ARM)
* Language C or ARM Assembly
* Purpose Definition of macros to operate on bit fields.
*/
#ifndef __BITFIELD_H
#define __BITFIELD_H
#ifndef __ASSEMBLY__
#define UData(Data) ((unsigned long) (Data))
#else
#define UData(Data) (Data)
#endif
/*
* MACRO: Fld
*
* Purpose
* The macro "Fld" encodes a bit field, given its size and its shift value
* with respect to bit 0.
*
* Note
* A more intuitive way to encode bit fields would have been to use their
* mask. However, extracting size and shift value information from a bit
* field's mask is cumbersome and might break the assembler (255-character
* line-size limit).
*
* Input
* Size Size of the bit field, in number of bits.
* Shft Shift value of the bit field with respect to bit 0.
*
* Output
* Fld Encoded bit field.
*/
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
/*
* MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
*
* Purpose
* The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
* the size, shift value, mask, aligned mask, and first bit of a
* bit field.
*
* Input
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FSize Size of the bit field, in number of bits.
* FShft Shift value of the bit field with respect to bit 0.
* FMsk Mask for the bit field.
* FAlnMsk Mask for the bit field, aligned on bit 0.
* F1stBit First bit of the bit field.
*/
#define FSize(Field) ((Field) >> 16)
#define FShft(Field) ((Field) & 0x0000FFFF)
#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
#define F1stBit(Field) (UData (1) << FShft (Field))
/*
* MACRO: FInsrt
*
* Purpose
* The macro "FInsrt" inserts a value into a bit field by shifting the
* former appropriately.
*
* Input
* Value Bit-field value.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FInsrt Bit-field value positioned appropriately.
*/
#define FInsrt(Value, Field) \
(UData (Value) << FShft (Field))
/*
* MACRO: FExtr
*
* Purpose
* The macro "FExtr" extracts the value of a bit field by masking and
* shifting it appropriately.
*
* Input
* Data Data containing the bit-field to be extracted.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FExtr Bit-field value.
*/
#define FExtr(Data, Field) \
((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
#endif /* __BITFIELD_H */

110
include/asm-arm/arch-pxa/corgi.h Normal file
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/*
* Hardware specific definitions for SL-C7xx series of PDAs
*
* Copyright (c) 2004-2005 Richard Purdie
*
* Based on Sharp's 2.4 kernel patches
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_CORGI_H
#define __ASM_ARCH_CORGI_H 1
/*
* Corgi (Non Standard) GPIO Definitions
*/
#define CORGI_GPIO_KEY_INT (0) /* Keyboard Interrupt */
#define CORGI_GPIO_AC_IN (1) /* Charger Detection */
#define CORGI_GPIO_WAKEUP (3) /* System wakeup notification? */
#define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */
#define CORGI_GPIO_TP_INT (5) /* Touch Panel Interrupt */
#define CORGI_GPIO_nSD_WP (7) /* SD Write Protect? */
#define CORGI_GPIO_nSD_DETECT (9) /* MMC/SD Card Detect */
#define CORGI_GPIO_nSD_INT (10) /* SD Interrupt for SDIO? */
#define CORGI_GPIO_MAIN_BAT_LOW (11) /* Main Battery Low Notification */
#define CORGI_GPIO_BAT_COVER (11) /* Battery Cover Detect */
#define CORGI_GPIO_LED_ORANGE (13) /* Orange LED Control */
#define CORGI_GPIO_CF_CD (14) /* Compact Flash Card Detect */
#define CORGI_GPIO_CHRG_FULL (16) /* Charging Complete Notification */
#define CORGI_GPIO_CF_IRQ (17) /* Compact Flash Interrupt */
#define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */
#define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */
#define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */
#define CORGI_GPIO_IR_ON (22) /* Enable IR Transciever */
#define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */
#define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */
#define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */
#define CORGI_GPIO_DISCHARGE_ON (42) /* Enable battery Discharge */
#define CORGI_GPIO_CHRG_UKN (43) /* Unknown Charging (Bypass Control?) */
#define CORGI_GPIO_HSYNC (44) /* LCD HSync Pulse */
#define CORGI_GPIO_USB_PULLUP (45) /* USB show presence to host */
/*
* Corgi Keyboard Definitions
*/
#define CORGI_KEY_STROBE_NUM (12)
#define CORGI_KEY_SENSE_NUM (8)
#define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc)
#define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000)
#define CORGI_GPIO_HIGH_SENSE_RSHIFT (26)
#define CORGI_GPIO_LOW_SENSE_BIT (0x00000003)
#define CORGI_GPIO_LOW_SENSE_LSHIFT (6)
#define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a))
#define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a))
#define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0)
#define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000)
#define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f)
#define CORGI_GPIO_KEY_SENSE(a) (58+(a))
#define CORGI_GPIO_KEY_STROBE(a) (66+(a))
/*
* Corgi Interrupts
*/
#define CORGI_IRQ_GPIO_KEY_INT IRQ_GPIO(0)
#define CORGI_IRQ_GPIO_AC_IN IRQ_GPIO(1)
#define CORGI_IRQ_GPIO_WAKEUP IRQ_GPIO(3)
#define CORGI_IRQ_GPIO_AK_INT IRQ_GPIO(4)
#define CORGI_IRQ_GPIO_TP_INT IRQ_GPIO(5)
#define CORGI_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9)
#define CORGI_IRQ_GPIO_nSD_INT IRQ_GPIO(10)
#define CORGI_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(11)
#define CORGI_IRQ_GPIO_CF_CD IRQ_GPIO(14)
#define CORGI_IRQ_GPIO_CHRG_FULL IRQ_GPIO(16) /* Battery fully charged */
#define CORGI_IRQ_GPIO_CF_IRQ IRQ_GPIO(17)
#define CORGI_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(58+(a)) /* Keyboard Sense lines */
/*
* Corgi SCOOP GPIOs and Config
*/
#define CORGI_SCP_LED_GREEN SCOOP_GPCR_PA11
#define CORGI_SCP_SWA SCOOP_GPCR_PA12 /* Hinge Switch A */
#define CORGI_SCP_SWB SCOOP_GPCR_PA13 /* Hinge Switch B */
#define CORGI_SCP_MUTE_L SCOOP_GPCR_PA14
#define CORGI_SCP_MUTE_R SCOOP_GPCR_PA15
#define CORGI_SCP_AKIN_PULLUP SCOOP_GPCR_PA16
#define CORGI_SCP_APM_ON SCOOP_GPCR_PA17
#define CORGI_SCP_BACKLIGHT_CONT SCOOP_GPCR_PA18
#define CORGI_SCP_MIC_BIAS SCOOP_GPCR_PA19
#define CORGI_SCOOP_IO_DIR ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \
CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \
CORGI_SCP_MIC_BIAS )
#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
/*
* Shared data structures
*/
extern struct platform_device corgiscoop_device;
extern struct platform_device corgissp_device;
extern struct platform_device corgifb_device;
#endif /* __ASM_ARCH_CORGI_H */

25
include/asm-arm/arch-pxa/debug-macro.S Normal file
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/* linux/include/asm-arm/arch-pxa/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include "hardware.h"
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x40000000 @ physical
movne \rx, #io_p2v(0x40000000) @ virtual
orr \rx, \rx, #0x00100000
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

64
include/asm-arm/arch-pxa/dma.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/dma.h
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
/*
* Descriptor structure for PXA's DMA engine
* Note: this structure must always be aligned to a 16-byte boundary.
*/
typedef struct pxa_dma_desc {
volatile u32 ddadr; /* Points to the next descriptor + flags */
volatile u32 dsadr; /* DSADR value for the current transfer */
volatile u32 dtadr; /* DTADR value for the current transfer */
volatile u32 dcmd; /* DCMD value for the current transfer */
} pxa_dma_desc;
typedef enum {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 1,
DMA_PRIO_LOW = 2
} pxa_dma_prio;
#if defined(CONFIG_PXA27x)
#define PXA_DMA_CHANNELS 32
#define pxa_for_each_dma_prio(ch, prio) \
for ( \
ch = prio * 4; \
ch != (4 << prio) + 16; \
ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \
)
#elif defined(CONFIG_PXA25x)
#define PXA_DMA_CHANNELS 16
#define pxa_for_each_dma_prio(ch, prio) \
for (ch = prio * 4; ch != (4 << prio); ch++)
#endif
/*
* DMA registration
*/
int pxa_request_dma (char *name,
pxa_dma_prio prio,
void (*irq_handler)(int, void *),
void *data);
void pxa_free_dma (int dma_ch);
#endif /* _ASM_ARCH_DMA_H */

39
include/asm-arm/arch-pxa/entry-macro.S Normal file
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/*
* include/asm-arm/arch-pxa/entry-macro.S
*
* Low-level IRQ helper macros for PXA-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware.h>
#include <asm/arch/irqs.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#ifdef CONFIG_PXA27x
mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
#else
mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
add \base, \base, #0x00d00000
ldr \irqstat, [\base, #0] @ ICIP
ldr \irqnr, [\base, #4] @ ICMR
#endif
ands \irqnr, \irqstat, \irqnr
beq 1001f
rsb \irqstat, \irqnr, #0
and \irqstat, \irqstat, \irqnr
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP)
1001:
.endm

80
include/asm-arm/arch-pxa/gpio.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/gpio.h
*
* PXA GPIO wrappers for arch-neutral GPIO calls
*
* Written by Philipp Zabel <philipp.zabel@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __ASM_ARCH_PXA_GPIO_H
#define __ASM_ARCH_PXA_GPIO_H
#include <asm/arch/pxa-regs.h>
#include <asm/irq.h>
#include <asm/hardware.h>
static inline int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
static inline void gpio_free(unsigned gpio)
{
return;
}
static inline int gpio_direction_input(unsigned gpio)
{
return pxa_gpio_mode(gpio | GPIO_IN);
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
return pxa_gpio_mode(gpio | GPIO_OUT | (value ? 0 : GPIO_DFLT_LOW));
}
static inline int __gpio_get_value(unsigned gpio)
{
return GPLR(gpio) & GPIO_bit(gpio);
}
#define gpio_get_value(gpio) \
(__builtin_constant_p(gpio) ? \
__gpio_get_value(gpio) : \
pxa_gpio_get_value(gpio))
static inline void __gpio_set_value(unsigned gpio, int value)
{
if (value)
GPSR(gpio) = GPIO_bit(gpio);
else
GPCR(gpio) = GPIO_bit(gpio);
}
#define gpio_set_value(gpio,value) \
(__builtin_constant_p(gpio) ? \
__gpio_set_value(gpio, value) : \
pxa_gpio_set_value(gpio, value))
#include <asm-generic/gpio.h> /* cansleep wrappers */
#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
#define irq_to_gpio(irq) IRQ_TO_GPIO(irq)
#endif

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include/asm-arm/arch-pxa/hardware.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/hardware.h
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/*
* We requires absolute addresses.
*/
#define PCIO_BASE 0
/*
* Workarounds for at least 2 errata so far require this.
* The mapping is set in mach-pxa/generic.c.
*/
#define UNCACHED_PHYS_0 0xff000000
#define UNCACHED_ADDR UNCACHED_PHYS_0
/*
* Intel PXA2xx internal register mapping:
*
* 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
* 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
* 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
* 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
* 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
* 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
* 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
*
* Note that not all PXA2xx chips implement all those addresses, and the
* kernel only maps the minimum needed range of this mapping.
*/
#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
#ifndef __ASSEMBLY__
# define __REG(x) (*((volatile u32 *)io_p2v(x)))
/* With indexed regs we don't want to feed the index through io_p2v()
especially if it is a variable, otherwise horrible code will result. */
# define __REG2(x,y) \
(*(volatile u32 *)((u32)&__REG(x) + (y)))
# define __PREG(x) (io_v2p((u32)&(x)))
#else
# define __REG(x) io_p2v(x)
# define __PREG(x) io_v2p(x)
#endif
#ifndef __ASSEMBLY__
/*
* Handy routine to set GPIO alternate functions
*/
extern int pxa_gpio_mode( int gpio_mode );
/*
* Return GPIO level, nonzero means high, zero is low
*/
extern int pxa_gpio_get_value(unsigned gpio);
/*
* Set output GPIO level
*/
extern void pxa_gpio_set_value(unsigned gpio, int value);
/*
* Routine to enable or disable CKEN
*/
extern void pxa_set_cken(int clock, int enable);
/*
* return current memory and LCD clock frequency in units of 10kHz
*/
extern unsigned int get_memclk_frequency_10khz(void);
extern unsigned int get_lcdclk_frequency_10khz(void);
#endif
#endif /* _ASM_ARCH_HARDWARE_H */

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include/asm-arm/arch-pxa/i2c.h Normal file
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/*
* i2c_pxa.h
*
* Copyright (C) 2002 Intrinsyc Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _I2C_PXA_H_
#define _I2C_PXA_H_
#if 0
#define DEF_TIMEOUT 3
#else
/* need a longer timeout if we're dealing with the fact we may well be
* looking at a multi-master environment
*/
#define DEF_TIMEOUT 32
#endif
#define BUS_ERROR (-EREMOTEIO)
#define XFER_NAKED (-ECONNREFUSED)
#define I2C_RETRY (-2000) /* an error has occurred retry transmit */
/* ICR initialize bit values
*
* 15. FM 0 (100 Khz operation)
* 14. UR 0 (No unit reset)
* 13. SADIE 0 (Disables the unit from interrupting on slave addresses
* matching its slave address)
* 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration
* in master mode)
* 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
* 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
* 9. IRFIE 1 (Enable interrupts from full buffer received)
* 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
* 7. GCD 1 (Disables i2c unit response to general call messages as a slave)
* 6. IUE 0 (Disable unit until we change settings)
* 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
* 4. MA 0 (Only send stop with the ICR stop bit)
* 3. TB 0 (We are not transmitting a byte initially)
* 2. ACKNAK 0 (Send an ACK after the unit receives a byte)
* 1. STOP 0 (Do not send a STOP)
* 0. START 0 (Do not send a START)
*
*/
#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
/* I2C status register init values
*
* 10. BED 1 (Clear bus error detected)
* 9. SAD 1 (Clear slave address detected)
* 7. IRF 1 (Clear IDBR Receive Full)
* 6. ITE 1 (Clear IDBR Transmit Empty)
* 5. ALD 1 (Clear Arbitration Loss Detected)
* 4. SSD 1 (Clear Slave Stop Detected)
*/
#define I2C_ISR_INIT 0x7FF /* status register init */
struct i2c_slave_client;
struct i2c_pxa_platform_data {
unsigned int slave_addr;
struct i2c_slave_client *slave;
};
extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
#endif

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include/asm-arm/arch-pxa/idp.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/idp.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
*
* 2001-09-13: Cliff Brake <cbrake@accelent.com>
* Initial code
*
* 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
* <http://www.vibren.com> <http://bec-systems.com>
* Changes for 2.6 kernel.
*/
/*
* Note: this file must be safe to include in assembly files
*
* Support for the Vibren PXA255 IDP requires rev04 or later
* IDP hardware.
*/
#define IDP_FLASH_PHYS (PXA_CS0_PHYS)
#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS)
#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
/*
* virtual memory map
*/
#define IDP_COREVOLT_VIRT (0xf0000000)
#define IDP_COREVOLT_SIZE (1*1024*1024)
#define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
#define IDP_CPLD_SIZE (1*1024*1024)
#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
#error Your custom IO space is getting a bit large !!
#endif
#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
#define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
#ifndef __ASSEMBLY__
# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x)))
#else
# define __CPLD_REG(x) CPLD_P2V(x)
#endif
/* board level registers in the CPLD: (offsets from CPLD_VIRT) */
#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00)
#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08)
#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28)
#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C)
#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30)
#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34)
#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50)
#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54)
#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58)
#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C)
/* FPGA register virtual addresses */
#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV)
#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL)
#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN)
#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL)
#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD)
#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE)
#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW)
#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS)
/*
* Bit masks for various registers
*/
// IDP_CPLD_PCCARD_PWR
#define PCC0_PWR0 (1 << 0)
#define PCC0_PWR1 (1 << 1)
#define PCC0_PWR2 (1 << 2)
#define PCC0_PWR3 (1 << 3)
#define PCC1_PWR0 (1 << 4)
#define PCC1_PWR1 (1 << 5)
#define PCC1_PWR2 (1 << 6)
#define PCC1_PWR3 (1 << 7)
// IDP_CPLD_PCCARD_EN
#define PCC0_RESET (1 << 6)
#define PCC1_RESET (1 << 7)
#define PCC0_ENABLE (1 << 0)
#define PCC1_ENABLE (1 << 1)
// IDP_CPLD_PCCARDx_STATUS
#define _PCC_WRPROT (1 << 7) // 7-4 read as low true
#define _PCC_RESET (1 << 6)
#define _PCC_IRQ (1 << 5)
#define _PCC_INPACK (1 << 4)
#define PCC_BVD2 (1 << 3)
#define PCC_BVD1 (1 << 2)
#define PCC_VS2 (1 << 1)
#define PCC_VS1 (1 << 0)
#define PCC_DETECT(x) (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
/* A listing of interrupts used by external hardware devices */
#define TOUCH_PANEL_IRQ IRQ_GPIO(5)
#define IDE_IRQ IRQ_GPIO(21)
#define TOUCH_PANEL_IRQ_EDGE IRQT_FALLING
#define ETHERNET_IRQ IRQ_GPIO(4)
#define ETHERNET_IRQ_EDGE IRQT_RISING
#define IDE_IRQ_EDGE IRQT_RISING
#define PCMCIA_S0_CD_VALID IRQ_GPIO(7)
#define PCMCIA_S0_CD_VALID_EDGE IRQT_BOTHEDGE
#define PCMCIA_S1_CD_VALID IRQ_GPIO(8)
#define PCMCIA_S1_CD_VALID_EDGE IRQT_BOTHEDGE
#define PCMCIA_S0_RDYINT IRQ_GPIO(19)
#define PCMCIA_S1_RDYINT IRQ_GPIO(22)
/*
* Macros for LED Driver
*/
/* leds 0 = ON */
#define IDP_HB_LED (1<<5)
#define IDP_BUSY_LED (1<<6)
#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED)
/*
* macros for MTD driver
*/
#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1))
#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1))
/*
* macros for matrix keyboard driver
*/
#define KEYBD_MATRIX_NUMBER_INPUTS 7
#define KEYBD_MATRIX_NUMBER_OUTPUTS 14
#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE
#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE
#define KEYBD_MATRIX_SETTLING_TIME_US 100
#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2
#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
{\
IDP_CPLD_KB_COL_LOW = outputs;\
IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
}
#define KEYBD_MATRIX_GET_INPUTS(inputs) \
{\
inputs = (IDP_CPLD_KB_ROW & 0x7f);\
}

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include/asm-arm/arch-pxa/io.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/io.h
*
* Copied from asm/arch/sa1100/io.h
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#endif

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#ifndef ASMARM_ARCH_IRDA_H
#define ASMARM_ARCH_IRDA_H
/* board specific transceiver capabilities */
#define IR_OFF 1
#define IR_SIRMODE 2
#define IR_FIRMODE 4
struct pxaficp_platform_data {
int transceiver_cap;
void (*transceiver_mode)(struct device *dev, int mode);
};
extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
#endif

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include/asm-arm/arch-pxa/irqs.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/irqs.h
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifdef CONFIG_PXA27x
#define PXA_IRQ_SKIP 0
#else
#define PXA_IRQ_SKIP 7
#endif
#define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP)
#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */
#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */
#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */
#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */
#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
#define IRQ_USB PXA_IRQ(11) /* USB Service */
#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */
#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */
#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */
#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */
#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */
#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */
#define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */
#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */
#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */
#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */
#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */
#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/
#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */
#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */
#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */
#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */
#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */
#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */
#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */
#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
#ifdef CONFIG_PXA27x
#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
#define PXA_INTERNAL_IRQS 34
#else
#define PXA_INTERNAL_IRQS 32
#endif
#define GPIO_2_x_TO_IRQ(x) \
PXA_IRQ((x) - 2 + PXA_INTERNAL_IRQS)
#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
#define IRQ_TO_GPIO_2_x(i) \
((i) - IRQ_GPIO(2) + 2)
#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
#if defined(CONFIG_PXA25x)
#define PXA_LAST_GPIO 84
#elif defined(CONFIG_PXA27x)
#define PXA_LAST_GPIO 127
#endif
/*
* The next 16 interrupts are for board specific purposes. Since
* the kernel can only run on one machine at a time, we can re-use
* these. If you need more, increase IRQ_BOARD_END, but keep it
* within sensible limits.
*/
#define IRQ_BOARD_START (IRQ_GPIO(PXA_LAST_GPIO) + 1)
#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
#define IRQ_SA1111_START (IRQ_BOARD_END)
#define IRQ_GPAIN0 (IRQ_BOARD_END + 0)
#define IRQ_GPAIN1 (IRQ_BOARD_END + 1)
#define IRQ_GPAIN2 (IRQ_BOARD_END + 2)
#define IRQ_GPAIN3 (IRQ_BOARD_END + 3)
#define IRQ_GPBIN0 (IRQ_BOARD_END + 4)
#define IRQ_GPBIN1 (IRQ_BOARD_END + 5)
#define IRQ_GPBIN2 (IRQ_BOARD_END + 6)
#define IRQ_GPBIN3 (IRQ_BOARD_END + 7)
#define IRQ_GPBIN4 (IRQ_BOARD_END + 8)
#define IRQ_GPBIN5 (IRQ_BOARD_END + 9)
#define IRQ_GPCIN0 (IRQ_BOARD_END + 10)
#define IRQ_GPCIN1 (IRQ_BOARD_END + 11)
#define IRQ_GPCIN2 (IRQ_BOARD_END + 12)
#define IRQ_GPCIN3 (IRQ_BOARD_END + 13)
#define IRQ_GPCIN4 (IRQ_BOARD_END + 14)
#define IRQ_GPCIN5 (IRQ_BOARD_END + 15)
#define IRQ_GPCIN6 (IRQ_BOARD_END + 16)
#define IRQ_GPCIN7 (IRQ_BOARD_END + 17)
#define IRQ_MSTXINT (IRQ_BOARD_END + 18)
#define IRQ_MSRXINT (IRQ_BOARD_END + 19)
#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20)
#define IRQ_TPTXINT (IRQ_BOARD_END + 21)
#define IRQ_TPRXINT (IRQ_BOARD_END + 22)
#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23)
#define SSPXMTINT (IRQ_BOARD_END + 24)
#define SSPRCVINT (IRQ_BOARD_END + 25)
#define SSPROR (IRQ_BOARD_END + 26)
#define AUDXMTDMADONEA (IRQ_BOARD_END + 32)
#define AUDRCVDMADONEA (IRQ_BOARD_END + 33)
#define AUDXMTDMADONEB (IRQ_BOARD_END + 34)
#define AUDRCVDMADONEB (IRQ_BOARD_END + 35)
#define AUDTFSR (IRQ_BOARD_END + 36)
#define AUDRFSR (IRQ_BOARD_END + 37)
#define AUDTUR (IRQ_BOARD_END + 38)
#define AUDROR (IRQ_BOARD_END + 39)
#define AUDDTS (IRQ_BOARD_END + 40)
#define AUDRDD (IRQ_BOARD_END + 41)
#define AUDSTO (IRQ_BOARD_END + 42)
#define IRQ_USBPWR (IRQ_BOARD_END + 43)
#define IRQ_HCIM (IRQ_BOARD_END + 44)
#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45)
#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46)
#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47)
#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48)
#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49)
#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50)
#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51)
#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52)
#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53)
#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54)
#define IRQ_LOCOMO_START (IRQ_BOARD_END)
#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0)
#define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1)
#define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2)
#define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3)
#define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4)
#define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5)
#define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6)
#define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7)
#define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8)
#define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9)
#define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10)
#define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11)
#define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12)
#define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13)
#define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14)
#define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15)
#define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16)
#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17)
#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18)
#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19)
#define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20)
#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21)
/*
* Figure out the MAX IRQ number.
*
* If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
* If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
* Otherwise, we have the standard IRQs only.
*/
#ifdef CONFIG_SA1111
#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1)
#elif defined(CONFIG_SHARP_LOCOMO)
#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
#elif defined(CONFIG_ARCH_LUBBOCK) || \
defined(CONFIG_MACH_LOGICPD_PXA270) || \
defined(CONFIG_MACH_MAINSTONE)
#define NR_IRQS (IRQ_BOARD_END)
#else
#define NR_IRQS (IRQ_BOARD_START)
#endif
/*
* Board specific IRQs. Define them here.
* Do not surround them with ifdefs.
*/
#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x))
#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */
#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3)
#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4)
#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5)
#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
#define LPD270_IRQ(x) (IRQ_BOARD_START + (x))
#define LPD270_USBC_IRQ LPD270_IRQ(2)
#define LPD270_ETHERNET_IRQ LPD270_IRQ(3)
#define LPD270_AC97_IRQ LPD270_IRQ(4)
#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x))
#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3)
#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4)
#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5)
#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6)
#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7)
#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9)
#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10)
#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11)
#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13)
#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0)
#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1)
#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)

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include/asm-arm/arch-pxa/lpd270.h Normal file
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/*
* include/asm-arm/arch-pxa/lpd270.h
*
* Author: Lennert Buytenhek
* Created: Feb 10, 2006
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_LPD270_H
#define __ASM_ARCH_LPD270_H
#define LPD270_CPLD_PHYS PXA_CS2_PHYS
#define LPD270_CPLD_VIRT 0xf0000000
#define LPD270_CPLD_SIZE 0x00100000
#define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000)
/* CPLD registers */
#define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x)))
#define LPD270_CONTROL LPD270_CPLD_REG(0x00)
#define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04)
#define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08)
#define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14)
#define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20)
#define LPD270_MODE_PINS LPD270_CPLD_REG(0x24)
#define LPD270_EGPIO LPD270_CPLD_REG(0x30)
#define LPD270_INT_MASK LPD270_CPLD_REG(0x40)
#define LPD270_INT_STATUS LPD270_CPLD_REG(0x50)
#define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */
#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */
#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */
#endif

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include/asm-arm/arch-pxa/lubbock.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/lubbock.h
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define LUBBOCK_ETH_PHYS PXA_CS3_PHYS
#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS
#define LUBBOCK_FPGA_VIRT (0xf0000000)
#define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
#define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)
#ifndef __ASSEMBLY__
# define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x)))
#else
# define __LUB_REG(x) LUB_P2V(x)
#endif
/* FPGA register virtual addresses */
#define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
#define LUB_HEXLED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)
#define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
#define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
#define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
#define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
#define LUB_MISC_RD __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090)
#define LUB_IRQ_MASK_EN __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0)
#define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0)
#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
#ifndef __ASSEMBLY__
extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
#endif

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/*
* linux/include/asm-arm/arch-pxa/mainstone.h
*
* Author: Nicolas Pitre
* Created: Nov 14, 2002
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ASM_ARCH_MAINSTONE_H
#define ASM_ARCH_MAINSTONE_H
#define MST_ETH_PHYS PXA_CS4_PHYS
#define MST_FPGA_PHYS PXA_CS2_PHYS
#define MST_FPGA_VIRT (0xf0000000)
#define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT)
#define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS)
#ifndef __ASSEMBLY__
# define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x)))
#else
# define __MST_REG(x) MST_P2V(x)
#endif
/* board level registers in the FPGA */
#define MST_LEDDAT1 __MST_REG(0x08000010)
#define MST_LEDDAT2 __MST_REG(0x08000014)
#define MST_LEDCTRL __MST_REG(0x08000040)
#define MST_GPSWR __MST_REG(0x08000060)
#define MST_MSCWR1 __MST_REG(0x08000080)
#define MST_MSCWR2 __MST_REG(0x08000084)
#define MST_MSCWR3 __MST_REG(0x08000088)
#define MST_MSCRD __MST_REG(0x08000090)
#define MST_INTMSKENA __MST_REG(0x080000c0)
#define MST_INTSETCLR __MST_REG(0x080000d0)
#define MST_PCMCIA0 __MST_REG(0x080000e0)
#define MST_PCMCIA1 __MST_REG(0x080000e4)
#define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */
#define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */
#define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */
#define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */
#define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */
#define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */
#define MST_MSCWR1_BB_SEL (1 << 9) /* PCMCIA/Baseband multiplexer */
#define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */
#define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */
#define MST_MSCWR1_IRDA_MASK (3 << 5) /* IrDA transceiver mode */
#define MST_MSCWR1_IRDA_FULL (0 << 5) /* full distance power */
#define MST_MSCWR1_IRDA_OFF (1 << 5) /* shutdown */
#define MST_MSCWR1_IRDA_MED (2 << 5) /* 2/3 distance power */
#define MST_MSCWR1_IRDA_LOW (3 << 5) /* 1/3 distance power */
#define MST_MSCWR1_IRDA_FIR (1 << 4) /* IrDA transceiver SIR/FIR */
#define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */
#define MST_MSCWR1_PDC_CTL (1 << 2) /* reserved */
#define MST_MSCWR1_MTR_ON (1 << 1) /* Silent alert motor */
#define MST_MSCWR1_SYSRESET (1 << 0) /* System reset */
#define MST_MSCWR2_USB_OTG_RST (1 << 6) /* USB On The Go reset */
#define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */
#define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */
#define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */
#define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */
#define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */
#define MST_MSCWR2_RADIO_WAKE (1 << 0) /* Radio module wake-up signal */
#define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */
#define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */
#define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */
#define MST_MSCRD_nPENIRQ (1 << 9) /* ADI7873* nPENIRQ signal */
#define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */
#define MST_MSCRD_nMMC_CD (1 << 7) /* SD/MMC card detection signal */
#define MST_MSCRD_nUSIM_CD (1 << 6) /* USIM card detection signal */
#define MST_MSCRD_USB_CBL (1 << 5) /* USB client cable status */
#define MST_MSCRD_TS_BUSY (1 << 4) /* ADI7873 busy */
#define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */
#define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */
#define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */
#define MST_MSCRD_nMMC_WP (1 << 0) /* SD/MMC write-protect status */
#define MST_INT_S1_IRQ (1 << 15) /* PCMCIA socket 1 IRQ */
#define MST_INT_S1_STSCHG (1 << 14) /* PCMCIA socket 1 status changed */
#define MST_INT_S1_CD (1 << 13) /* PCMCIA socket 1 card detection */
#define MST_INT_S0_IRQ (1 << 11) /* PCMCIA socket 0 IRQ */
#define MST_INT_S0_STSCHG (1 << 10) /* PCMCIA socket 0 status changed */
#define MST_INT_S0_CD (1 << 9) /* PCMCIA socket 0 card detection */
#define MST_INT_nEXBRD_INT (1 << 7) /* Expansion board IRQ */
#define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */
#define MST_INT_PENIRQ (1 << 5) /* ADI7873* touch-screen IRQ */
#define MST_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */
#define MST_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */
#define MST_INT_USBC (1 << 2) /* USB client cable detection IRQ */
#define MST_INT_USIM (1 << 1) /* USIM card detection IRQ */
#define MST_INT_MMC (1 << 0) /* MMC/SD card detection IRQ */
#define MST_PCMCIA_nIRQ (1 << 10) /* IRQ / ready signal */
#define MST_PCMCIA_nSPKR_BVD2 (1 << 9) /* VDD sense / digital speaker */
#define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8) /* VDD sense / card status changed */
#define MST_PCMCIA_nVS2 (1 << 7) /* VSS voltage sense */
#define MST_PCMCIA_nVS1 (1 << 6) /* VSS voltage sense */
#define MST_PCMCIA_nCD (1 << 5) /* Card detection signal */
#define MST_PCMCIA_RESET (1 << 4) /* Card reset signal */
#define MST_PCMCIA_PWR_MASK (0x000f) /* MAX1602 power-supply controls */
#define MST_PCMCIA_PWR_VPP_0 0x0 /* voltage VPP = 0V */
#define MST_PCMCIA_PWR_VPP_120 0x2 /* voltage VPP = 12V*/
#define MST_PCMCIA_PWR_VPP_VCC 0x1 /* voltage VPP = VCC */
#define MST_PCMCIA_PWR_VCC_0 0x0 /* voltage VCC = 0V */
#define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */
#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */
#endif

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include/asm-arm/arch-pxa/memory.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/memory.h
*
* Author: Nicolas Pitre
* Copyright: (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0xa0000000)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
/*
* The nodes are matched with the physical SDRAM banks as follows:
*
* node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff
* node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff
* node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff
* node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff
*
* This needs a node mem size of 26 bits.
*/
#define NODE_MEM_SIZE_BITS 26
#endif

21
include/asm-arm/arch-pxa/mmc.h Normal file
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#ifndef ASMARM_ARCH_MMC_H
#define ASMARM_ARCH_MMC_H
#include <linux/mmc/protocol.h>
#include <linux/interrupt.h>
struct device;
struct mmc_host;
struct pxamci_platform_data {
unsigned int ocr_mask; /* available voltages */
unsigned long detect_delay; /* delay in jiffies before detecting cards after interrupt */
int (*init)(struct device *, irq_handler_t , void *);
int (*get_ro)(struct device *);
void (*setpower)(struct device *, unsigned int);
void (*exit)(struct device *, void *);
};
extern void pxa_set_mci_info(struct pxamci_platform_data *info);
#endif

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include/asm-arm/arch-pxa/mtd-xip.h Normal file
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/*
* MTD primitives for XIP support. Architecture specific functions
*
* Do not include this file directly. It's included from linux/mtd/xip.h
*
* Author: Nicolas Pitre
* Created: Nov 2, 2004
* Copyright: (C) 2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* $Id: mtd-xip.h,v 1.1.1.1 2007/06/12 07:27:14 eyryu Exp $
*/
#ifndef __ARCH_PXA_MTD_XIP_H__
#define __ARCH_PXA_MTD_XIP_H__
#include <asm/arch/pxa-regs.h>
#define xip_irqpending() (ICIP & ICMR)
/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
#define xip_currtime() (OSCR)
#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
/*
* xip_cpu_idle() is used when waiting for a delay equal or larger than
* the system timer tick period. This should put the CPU into idle mode
* to save power and to be woken up only when some interrupts are pending.
* As above, this should not rely upon standard kernel code.
*/
#define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
#endif /* __ARCH_PXA_MTD_XIP_H__ */

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include/asm-arm/arch-pxa/ohci.h Normal file
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#ifndef ASMARM_ARCH_OHCI_H
#define ASMARM_ARCH_OHCI_H
struct device;
struct pxaohci_platform_data {
int (*init)(struct device *);
void (*exit)(struct device *);
int port_mode;
#define PMM_NPS_MODE 1
#define PMM_GLOBAL_MODE 2
#define PMM_PERPORT_MODE 3
int power_budget;
};
extern void pxa_set_ohci_info(struct pxaohci_platform_data *info);
#endif

12
include/asm-arm/arch-pxa/pm.h Normal file
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/*
* Copyright (c) 2005 Richard Purdie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
extern int pxa_pm_prepare(suspend_state_t state);
extern int pxa_pm_enter(suspend_state_t state);
extern int pxa_pm_finish(suspend_state_t state);

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include/asm-arm/arch-pxa/poodle.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/poodle.h
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Based on:
* linux/include/asm-arm/arch-sa1100/collie.h
*
* ChangeLog:
* 04-06-2001 Lineo Japan, Inc.
* 04-16-2001 SHARP Corporation
* Update to 2.6 John Lenz
*/
#ifndef __ASM_ARCH_POODLE_H
#define __ASM_ARCH_POODLE_H 1
/*
* GPIOs
*/
/* PXA GPIOs */
#define POODLE_GPIO_ON_KEY (0)
#define POODLE_GPIO_AC_IN (1)
#define POODLE_GPIO_CO 16
#define POODLE_GPIO_TP_INT (5)
#define POODLE_GPIO_WAKEUP (11) /* change battery */
#define POODLE_GPIO_GA_INT (10)
#define POODLE_GPIO_IR_ON (22)
#define POODLE_GPIO_HP_IN (4)
#define POODLE_GPIO_CF_IRQ (17)
#define POODLE_GPIO_CF_CD (14)
#define POODLE_GPIO_CF_STSCHG (14)
#define POODLE_GPIO_SD_PWR (33)
#define POODLE_GPIO_SD_PWR1 (3)
#define POODLE_GPIO_nSD_CLK (6)
#define POODLE_GPIO_nSD_WP (7)
#define POODLE_GPIO_nSD_INT (8)
#define POODLE_GPIO_nSD_DETECT (9)
#define POODLE_GPIO_MAIN_BAT_LOW (13)
#define POODLE_GPIO_BAT_COVER (13)
#define POODLE_GPIO_USB_PULLUP (20)
#define POODLE_GPIO_ADC_TEMP_ON (21)
#define POODLE_GPIO_BYPASS_ON (36)
#define POODLE_GPIO_CHRG_ON (38)
#define POODLE_GPIO_CHRG_FULL (16)
#define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */
/* PXA GPIOs */
#define POODLE_IRQ_GPIO_ON_KEY IRQ_GPIO(0)
#define POODLE_IRQ_GPIO_AC_IN IRQ_GPIO(1)
#define POODLE_IRQ_GPIO_HP_IN IRQ_GPIO(4)
#define POODLE_IRQ_GPIO_CO IRQ_GPIO(16)
#define POODLE_IRQ_GPIO_TP_INT IRQ_GPIO(5)
#define POODLE_IRQ_GPIO_WAKEUP IRQ_GPIO(11)
#define POODLE_IRQ_GPIO_GA_INT IRQ_GPIO(10)
#define POODLE_IRQ_GPIO_CF_IRQ IRQ_GPIO(17)
#define POODLE_IRQ_GPIO_CF_CD IRQ_GPIO(14)
#define POODLE_IRQ_GPIO_nSD_INT IRQ_GPIO(8)
#define POODLE_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9)
#define POODLE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(13)
/* SCOOP GPIOs */
#define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11
#define POODLE_SCOOP_CP401 SCOOP_GPCR_PA13
#define POODLE_SCOOP_VPEN SCOOP_GPCR_PA18
#define POODLE_SCOOP_L_PCLK SCOOP_GPCR_PA20
#define POODLE_SCOOP_L_LCLK SCOOP_GPCR_PA21
#define POODLE_SCOOP_HS_OUT SCOOP_GPCR_PA22
#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
#define POODLE_SCOOP_IO_OUT ( 0 )
extern struct platform_device poodle_locomo_device;
#endif /* __ASM_ARCH_POODLE_H */

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include/asm-arm/arch-pxa/pxa-regs.h Normal file
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68
include/asm-arm/arch-pxa/pxa2xx_spi.h Normal file
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/*
* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef PXA2XX_SPI_H_
#define PXA2XX_SPI_H_
#define PXA2XX_CS_ASSERT (0x01)
#define PXA2XX_CS_DEASSERT (0x02)
#if defined(CONFIG_PXA25x)
#define CLOCK_SPEED_HZ 3686400
#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#elif defined(CONFIG_PXA27x)
#define CLOCK_SPEED_HZ 13000000
#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#endif
#define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
#define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
#define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
enum pxa_ssp_type {
SSP_UNDEFINED = 0,
PXA25x_SSP, /* pxa 210, 250, 255, 26x */
PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
PXA27x_SSP,
};
/* device.platform_data for SSP controller devices */
struct pxa2xx_spi_master {
enum pxa_ssp_type ssp_type;
u32 clock_enable;
u16 num_chipselect;
u8 enable_dma;
};
/* spi_board_info.controller_data for SPI slave devices,
* copied to spi_device.platform_data ... mostly for dma tuning
*/
struct pxa2xx_spi_chip {
u8 tx_threshold;
u8 rx_threshold;
u8 dma_burst_size;
u32 timeout;
u8 enable_loopback;
void (*cs_control)(u32 command);
};
#endif /*PXA2XX_SPI_H_*/

80
include/asm-arm/arch-pxa/pxafb.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/pxafb.h
*
* Support for the xscale frame buffer.
*
* Author: Jean-Frederic Clere
* Created: Sep 22, 2003
* Copyright: jfclere@sinix.net
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/fb.h>
/*
* This structure describes the machine which we are running on.
* It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
* of linux/drivers/video/pxafb.c
*/
struct pxafb_mode_info {
u_long pixclock;
u_short xres;
u_short yres;
u_char bpp;
u_char hsync_len;
u_char left_margin;
u_char right_margin;
u_char vsync_len;
u_char upper_margin;
u_char lower_margin;
u_char sync;
u_int cmap_greyscale:1,
unused:31;
};
struct pxafb_mach_info {
struct pxafb_mode_info *modes;
unsigned int num_modes;
u_int fixed_modes:1,
cmap_inverse:1,
cmap_static:1,
unused:29;
/* The following should be defined in LCCR0
* LCCR0_Act or LCCR0_Pas Active or Passive
* LCCR0_Sngl or LCCR0_Dual Single/Dual panel
* LCCR0_Mono or LCCR0_Color Mono/Color
* LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
* LCCR0_DMADel(Tcpu) (optional) DMA request delay
*
* The following should not be defined in LCCR0:
* LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
* LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
*/
u_int lccr0;
/* The following should be defined in LCCR3
* LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
* LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
* LCCR3_Acb(X) AB Bias pin frequency
* LCCR3_DPC (optional) Double Pixel Clock mode (untested)
*
* The following should not be defined in LCCR3
* LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
*/
u_int lccr3;
void (*pxafb_backlight_power)(int);
void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
};
void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
void set_pxa_fb_parent(struct device *parent_dev);
unsigned long pxafb_get_hsync_time(struct device *dev);

40
include/asm-arm/arch-pxa/sharpsl.h Normal file
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/*
* SharpSL SSP Driver
*/
unsigned long corgi_ssp_ads7846_putget(unsigned long);
unsigned long corgi_ssp_ads7846_get(void);
void corgi_ssp_ads7846_put(unsigned long data);
void corgi_ssp_ads7846_lock(void);
void corgi_ssp_ads7846_unlock(void);
void corgi_ssp_lcdtg_send (unsigned char adrs, unsigned char data);
void corgi_ssp_blduty_set(int duty);
int corgi_ssp_max1111_get(unsigned long data);
/*
* SharpSL Touchscreen Driver
*/
struct corgits_machinfo {
unsigned long (*get_hsync_len)(void);
void (*put_hsync)(void);
void (*wait_hsync)(void);
};
/*
* SharpSL Backlight
*/
struct corgibl_machinfo {
int max_intensity;
int default_intensity;
int limit_mask;
void (*set_bl_intensity)(int intensity);
};
extern void corgibl_limit_intensity(int limit);
/*
* SharpSL Battery/PM Driver
*/
extern void sharpsl_battery_kick(void);

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include/asm-arm/arch-pxa/spitz.h Normal file
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/*
* Hardware specific definitions for SL-Cx000 series of PDAs
*
* Copyright (c) 2005 Alexander Wykes
* Copyright (c) 2005 Richard Purdie
*
* Based on Sharp's 2.4 kernel patches
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_SPITZ_H
#define __ASM_ARCH_SPITZ_H 1
#endif
#include <linux/fb.h>
/* Spitz/Akita GPIOs */
#define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */
#define SPITZ_GPIO_RESET (1)
#define SPITZ_GPIO_nSD_DETECT (9)
#define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */
#define SPITZ_GPIO_AK_INT (13) /* Remote Control */
#define SPITZ_GPIO_ADS7846_CS (14)
#define SPITZ_GPIO_SYNC (16)
#define SPITZ_GPIO_MAX1111_CS (20)
#define SPITZ_GPIO_FATAL_BAT (21)
#define SPITZ_GPIO_HSYNC (22)
#define SPITZ_GPIO_nSD_CLK (32)
#define SPITZ_GPIO_USB_DEVICE (35)
#define SPITZ_GPIO_USB_HOST (37)
#define SPITZ_GPIO_USB_CONNECT (41)
#define SPITZ_GPIO_LCDCON_CS (53)
#define SPITZ_GPIO_nPCE (54)
#define SPITZ_GPIO_nSD_WP (81)
#define SPITZ_GPIO_ON_RESET (89)
#define SPITZ_GPIO_BAT_COVER (90)
#define SPITZ_GPIO_CF_CD (94)
#define SPITZ_GPIO_ON_KEY (95)
#define SPITZ_GPIO_SWA (97)
#define SPITZ_GPIO_SWB (96)
#define SPITZ_GPIO_CHRG_FULL (101)
#define SPITZ_GPIO_CO (101)
#define SPITZ_GPIO_CF_IRQ (105)
#define SPITZ_GPIO_AC_IN (115)
#define SPITZ_GPIO_HP_IN (116)
/* Spitz Only GPIOs */
#define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */
#define SPITZ_GPIO_CF2_CD (93)
/* Spitz/Akita Keyboard Definitions */
#define SPITZ_KEY_STROBE_NUM (11)
#define SPITZ_KEY_SENSE_NUM (7)
#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000
#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000
#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000
#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880
#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000
#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4
#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000
#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000
#define SPITZ_GPIO_KEY_STROBE0 88
#define SPITZ_GPIO_KEY_STROBE1 23
#define SPITZ_GPIO_KEY_STROBE2 24
#define SPITZ_GPIO_KEY_STROBE3 25
#define SPITZ_GPIO_KEY_STROBE4 26
#define SPITZ_GPIO_KEY_STROBE5 27
#define SPITZ_GPIO_KEY_STROBE6 52
#define SPITZ_GPIO_KEY_STROBE7 103
#define SPITZ_GPIO_KEY_STROBE8 107
#define SPITZ_GPIO_KEY_STROBE9 108
#define SPITZ_GPIO_KEY_STROBE10 114
#define SPITZ_GPIO_KEY_SENSE0 12
#define SPITZ_GPIO_KEY_SENSE1 17
#define SPITZ_GPIO_KEY_SENSE2 91
#define SPITZ_GPIO_KEY_SENSE3 34
#define SPITZ_GPIO_KEY_SENSE4 36
#define SPITZ_GPIO_KEY_SENSE5 38
#define SPITZ_GPIO_KEY_SENSE6 39
/* Spitz Scoop Device (No. 1) GPIOs */
/* Suspend States in comments */
#define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */
#define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */
#define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */
#define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */
#define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */
#define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */
#define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */
#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */
#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */
#define SPITZ_SCP_IO_DIR (SPITZ_SCP_LED_GREEN | SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_LED_ORANGE | \
SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R)
#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
#define SPITZ_SCP_SUS_SET 0
/* Spitz Scoop Device (No. 2) GPIOs */
/* Suspend States in comments */
#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */
#define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */
#define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */
#define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */
#define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */
#define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */
#define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */
#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */
#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */
#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
/* Spitz IRQ Definitions */
#define SPITZ_IRQ_GPIO_KEY_INT IRQ_GPIO(SPITZ_GPIO_KEY_INT)
#define SPITZ_IRQ_GPIO_AC_IN IRQ_GPIO(SPITZ_GPIO_AC_IN)
#define SPITZ_IRQ_GPIO_AK_INT IRQ_GPIO(SPITZ_GPIO_AK_INT)
#define SPITZ_IRQ_GPIO_HP_IN IRQ_GPIO(SPITZ_GPIO_HP_IN)
#define SPITZ_IRQ_GPIO_TP_INT IRQ_GPIO(SPITZ_GPIO_TP_INT)
#define SPITZ_IRQ_GPIO_SYNC IRQ_GPIO(SPITZ_GPIO_SYNC)
#define SPITZ_IRQ_GPIO_ON_KEY IRQ_GPIO(SPITZ_GPIO_ON_KEY)
#define SPITZ_IRQ_GPIO_SWA IRQ_GPIO(SPITZ_GPIO_SWA)
#define SPITZ_IRQ_GPIO_SWB IRQ_GPIO(SPITZ_GPIO_SWB)
#define SPITZ_IRQ_GPIO_BAT_COVER IRQ_GPIO(SPITZ_GPIO_BAT_COVER)
#define SPITZ_IRQ_GPIO_FATAL_BAT IRQ_GPIO(SPITZ_GPIO_FATAL_BAT)
#define SPITZ_IRQ_GPIO_CO IRQ_GPIO(SPITZ_GPIO_CO)
#define SPITZ_IRQ_GPIO_CF_IRQ IRQ_GPIO(SPITZ_GPIO_CF_IRQ)
#define SPITZ_IRQ_GPIO_CF_CD IRQ_GPIO(SPITZ_GPIO_CF_CD)
#define SPITZ_IRQ_GPIO_CF2_IRQ IRQ_GPIO(SPITZ_GPIO_CF2_IRQ)
#define SPITZ_IRQ_GPIO_nSD_INT IRQ_GPIO(SPITZ_GPIO_nSD_INT)
#define SPITZ_IRQ_GPIO_nSD_DETECT IRQ_GPIO(SPITZ_GPIO_nSD_DETECT)
/*
* Shared data structures
*/
extern struct platform_device spitzscoop_device;
extern struct platform_device spitzscoop2_device;
extern struct platform_device spitzssp_device;
extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
extern void spitz_lcd_power(int on, struct fb_var_screeninfo *var);

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include/asm-arm/arch-pxa/ssp.h Normal file
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/*
* ssp.h
*
* Copyright (C) 2003 Russell King, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This driver supports the following PXA CPU/SSP ports:-
*
* PXA250 SSP
* PXA255 SSP, NSSP
* PXA26x SSP, NSSP, ASSP
* PXA27x SSP1, SSP2, SSP3
*/
#ifndef SSP_H
#define SSP_H
/*
* SSP initialisation flags
*/
#define SSP_NO_IRQ 0x1 /* don't register an irq handler in SSP driver */
struct ssp_state {
u32 cr0;
u32 cr1;
u32 to;
u32 psp;
};
struct ssp_dev {
u32 port;
u32 mode;
u32 flags;
u32 psp_flags;
u32 speed;
int irq;
};
int ssp_write_word(struct ssp_dev *dev, u32 data);
int ssp_read_word(struct ssp_dev *dev, u32 *data);
int ssp_flush(struct ssp_dev *dev);
void ssp_enable(struct ssp_dev *dev);
void ssp_disable(struct ssp_dev *dev);
void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp);
void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp);
int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
void ssp_exit(struct ssp_dev *dev);
#endif

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include/asm-arm/arch-pxa/system.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/system.h
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/proc-fns.h>
#include "hardware.h"
#include "pxa-regs.h"
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
if (mode == 's') {
/* Jump into ROM at address 0 */
cpu_reset(0);
} else {
/* Initialize the watchdog and let it fire */
OWER = OWER_WME;
OSSR = OSSR_M3;
OSMR3 = OSCR + 368640; /* ... in 100 ms */
}
}

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include/asm-arm/arch-pxa/timex.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/timex.h
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#if defined(CONFIG_PXA25x)
/* PXA250/210 timer base */
#define CLOCK_TICK_RATE 3686400
#elif defined(CONFIG_PXA27x)
/* PXA27x timer base */
#ifdef CONFIG_MACH_MAINSTONE
#define CLOCK_TICK_RATE 3249600
#else
#define CLOCK_TICK_RATE 3250000
#endif
#endif

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include/asm-arm/arch-pxa/tosa.h Normal file
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/*
* Hardware specific definitions for Sharp SL-C6000x series of PDAs
*
* Copyright (c) 2005 Dirk Opfer
*
* Based on Sharp's 2.4 kernel patches
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _ASM_ARCH_TOSA_H_
#define _ASM_ARCH_TOSA_H_ 1
/* TOSA Chip selects */
#define TOSA_LCDC_PHYS PXA_CS4_PHYS
/* Internel Scoop */
#define TOSA_CF_PHYS (PXA_CS2_PHYS + 0x00800000)
/* Jacket Scoop */
#define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000)
/*
* SCOOP2 internal GPIOs
*/
#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11
#define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12
#define TOSA_SCOOP_IR_POWERDWN SCOOP_GPCR_PA13
#define TOSA_SCOOP_SD_WP SCOOP_GPCR_PA14
#define TOSA_SCOOP_PWR_ON SCOOP_GPCR_PA15
#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16
#define TOSA_SCOOP_BT_RESET SCOOP_GPCR_PA17
#define TOSA_SCOOP_BT_PWR_EN SCOOP_GPCR_PA18
#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19
/* GPIO Direction 1 : output mode / 0:input mode */
#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \
TOSA_SCOOP_IR_POWERDWN | TOSA_SCOOP_PWR_ON | TOSA_SCOOP_AUD_PWR_ON |\
TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN )
/* GPIO out put level when init 1: Hi */
#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN )
/*
* SCOOP2 jacket GPIOs
*/
#define TOSA_SCOOP_JC_BT_LED SCOOP_GPCR_PA11
#define TOSA_SCOOP_JC_NOTE_LED SCOOP_GPCR_PA12
#define TOSA_SCOOP_JC_CHRG_ERR_LED SCOOP_GPCR_PA13
#define TOSA_SCOOP_JC_USB_PULLUP SCOOP_GPCR_PA14
#define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15
#define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16
#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17
#define TOSA_SCOOP_JC_WLAN_LED SCOOP_GPCR_PA18
#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19
/* GPIO Direction 1 : output mode / 0:input mode */
#define TOSA_SCOOP_JC_IO_DIR ( TOSA_SCOOP_JC_BT_LED | TOSA_SCOOP_JC_NOTE_LED | \
TOSA_SCOOP_JC_CHRG_ERR_LED | TOSA_SCOOP_JC_USB_PULLUP | \
TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \
TOSA_SCOOP_JC_WLAN_LED | TOSA_SCOOP_JC_CARD_LIMIT_SEL )
/* GPIO out put level when init 1: Hi */
#define TOSA_SCOOP_JC_IO_OUT ( 0 )
/*
* Timing Generator
*/
#define TG_PNLCTL 0x00
#define TG_TPOSCTL 0x01
#define TG_DUTYCTL 0x02
#define TG_GPOSR 0x03
#define TG_GPODR1 0x04
#define TG_GPODR2 0x05
#define TG_PINICTL 0x06
#define TG_HPOSCTL 0x07
/*
* LED
*/
#define TOSA_SCOOP_LED_BLUE TOSA_SCOOP_GPCR_PA11
#define TOSA_SCOOP_LED_GREEN TOSA_SCOOP_GPCR_PA12
#define TOSA_SCOOP_LED_ORANGE TOSA_SCOOP_GPCR_PA13
#define TOSA_SCOOP_LED_WLAN TOSA_SCOOP_GPCR_PA18
/*
* PXA GPIOs
*/
#define TOSA_GPIO_POWERON (0)
#define TOSA_GPIO_RESET (1)
#define TOSA_GPIO_AC_IN (2)
#define TOSA_GPIO_RECORD_BTN (3)
#define TOSA_GPIO_SYNC (4) /* Cradle SYNC Button */
#define TOSA_GPIO_USB_IN (5)
#define TOSA_GPIO_JACKET_DETECT (7)
#define TOSA_GPIO_nSD_DETECT (9)
#define TOSA_GPIO_nSD_INT (10)
#define TOSA_GPIO_TC6393_CLK (11)
#define TOSA_GPIO_BAT1_CRG (12)
#define TOSA_GPIO_CF_CD (13)
#define TOSA_GPIO_BAT0_CRG (14)
#define TOSA_GPIO_TC6393_INT (15)
#define TOSA_GPIO_BAT0_LOW (17)
#define TOSA_GPIO_TC6393_RDY (18)
#define TOSA_GPIO_ON_RESET (19)
#define TOSA_GPIO_EAR_IN (20)
#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */
#define TOSA_GPIO_ON_KEY (22)
#define TOSA_GPIO_VGA_LINE (27)
#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */
#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */
#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */
#define TOSA_GPIO_TG_SPI_SCLK (81)
#define TOSA_GPIO_TG_SPI_CS (82)
#define TOSA_GPIO_TG_SPI_MOSI (83)
#define TOSA_GPIO_BAT1_LOW (84)
#define TOSA_GPIO_HP_IN GPIO_EAR_IN
#define TOSA_GPIO_MAIN_BAT_LOW GPIO_BAT0_LOW
#define TOSA_KEY_STROBE_NUM (11)
#define TOSA_KEY_SENSE_NUM (7)
#define TOSA_GPIO_HIGH_STROBE_BIT (0xfc000000)
#define TOSA_GPIO_LOW_STROBE_BIT (0x0000001f)
#define TOSA_GPIO_ALL_SENSE_BIT (0x00000fe0)
#define TOSA_GPIO_ALL_SENSE_RSHIFT (5)
#define TOSA_GPIO_STROBE_BIT(a) GPIO_bit(58+(a))
#define TOSA_GPIO_SENSE_BIT(a) GPIO_bit(69+(a))
#define TOSA_GAFR_HIGH_STROBE_BIT (0xfff00000)
#define TOSA_GAFR_LOW_STROBE_BIT (0x000003ff)
#define TOSA_GAFR_ALL_SENSE_BIT (0x00fffc00)
#define TOSA_GPIO_KEY_SENSE(a) (69+(a))
#define TOSA_GPIO_KEY_STROBE(a) (58+(a))
/*
* Interrupts
*/
#define TOSA_IRQ_GPIO_WAKEUP IRQ_GPIO(TOSA_GPIO_WAKEUP)
#define TOSA_IRQ_GPIO_AC_IN IRQ_GPIO(TOSA_GPIO_AC_IN)
#define TOSA_IRQ_GPIO_RECORD_BTN IRQ_GPIO(TOSA_GPIO_RECORD_BTN)
#define TOSA_IRQ_GPIO_SYNC IRQ_GPIO(TOSA_GPIO_SYNC)
#define TOSA_IRQ_GPIO_USB_IN IRQ_GPIO(TOSA_GPIO_USB_IN)
#define TOSA_IRQ_GPIO_JACKET_DETECT IRQ_GPIO(TOSA_GPIO_JACKET_DETECT)
#define TOSA_IRQ_GPIO_nSD_INT IRQ_GPIO(TOSA_GPIO_nSD_INT)
#define TOSA_IRQ_GPIO_nSD_DETECT IRQ_GPIO(TOSA_GPIO_nSD_DETECT)
#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG)
#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD)
#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG)
#define TOSA_IRQ_GPIO_TC6393_INT IRQ_GPIO(TOSA_GPIO_TC6393_INT)
#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW)
#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN)
#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ)
#define TOSA_IRQ_GPIO_ON_KEY IRQ_GPIO(TOSA_GPIO_ON_KEY)
#define TOSA_IRQ_GPIO_VGA_LINE IRQ_GPIO(TOSA_GPIO_VGA_LINE)
#define TOSA_IRQ_GPIO_TP_INT IRQ_GPIO(TOSA_GPIO_TP_INT)
#define TOSA_IRQ_GPIO_JC_CF_IRQ IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ)
#define TOSA_IRQ_GPIO_BAT_LOCKED IRQ_GPIO(TOSA_GPIO_BAT_LOCKED)
#define TOSA_IRQ_GPIO_BAT1_LOW IRQ_GPIO(TOSA_GPIO_BAT1_LOW)
#define TOSA_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(69+(a))
#define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW)
extern struct platform_device tosascoop_jc_device;
extern struct platform_device tosascoop_device;
#endif /* _ASM_ARCH_TOSA_H_ */

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include/asm-arm/arch-pxa/trizeps4.h Normal file
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/************************************************************************
* Include file for TRIZEPS4 SoM and ConXS eval-board
* Copyright (c) Jürgen Schindele
* 2006
************************************************************************/
/*
* Includes/Defines
*/
#ifndef _TRIPEPS4_H_
#define _TRIPEPS4_H_
/* physical memory regions */
#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */
#define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */
#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board CSFR register */
#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic chip on ConXS-Board BOCR register */
#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic chip on ConXS-Board IRCR register*/
#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic chip on ConXS-Board UPSR register*/
#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* Logic chip on ConXS-Board DICR register*/
/* virtual memory regions */
#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
#define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */
#define TRIZEPS4_CFSR_VIRT 0xF0100000
#define TRIZEPS4_BOCR_VIRT 0xF0200000
#define TRIZEPS4_DICR_VIRT 0xF0300000
#define TRIZEPS4_IRCR_VIRT 0xF0400000
#define TRIZEPS4_UPSR_VIRT 0xF0500000
/* size of flash */
#define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
/* Ethernet Controller Davicom DM9000 */
#define GPIO_DM9000 101
#define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
/* UCB1400 audio / TS-controller */
#define GPIO_UCB1400 1
#define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400)
/* PCMCIA socket Compact Flash */
#define GPIO_PCD 11 /* PCMCIA Card Detect */
#define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD)
#define GPIO_PRDY 13 /* READY / nINT */
#define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY)
/* MMC socket */
#define GPIO_MMC_DET 12
#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET)
/* LEDS using tx2 / rx2 */
#define GPIO_SYS_BUSY_LED 46
#define GPIO_HEARTBEAT_LED 47
/* Off-module PIC on ConXS board */
#define GPIO_PIC 0
#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC)
#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
#ifndef __ASSEMBLY__
#define ConXS_CFSR (*((volatile unsigned short *)CFSR_P2V(0x0C000000)))
#define ConXS_BCR (*((volatile unsigned short *)BCR_P2V(0x0E000000)))
#define ConXS_DCR (*((volatile unsigned short *)DCR_P2V(0x0F800000)))
#else
#define ConXS_CFSR CFSR_P2V(0x0C000000)
#define ConXS_BCR BCR_P2V(0x0E000000)
#define ConXS_DCR DCR_P2V(0x0F800000)
#endif
#define ConXS_CFSR_BVD_MASK 0x0003
#define ConXS_CFSR_BVD1 (1 << 0)
#define ConXS_CFSR_BVD2 (1 << 1)
#define ConXS_CFSR_VS_MASK 0x000C
#define ConXS_CFSR_VS1 (1 << 2)
#define ConXS_CFSR_VS2 (1 << 3)
#define ConXS_CFSR_VS_5V (0x3 << 2)
#define ConXS_CFSR_VS_3V3 0x0
#define ConXS_BCR_S0_POW_EN0 (1 << 0)
#define ConXS_BCR_S0_POW_EN1 (1 << 1)
#define ConXS_BCR_L_DISP (1 << 4)
#define ConXS_BCR_CF_BUF_EN (1 << 5)
#define ConXS_BCR_CF_RESET (1 << 7)
#define ConXS_BCR_S0_VCC_3V3 0x1
#define ConXS_BCR_S0_VCC_5V0 0x2
#define ConXS_BCR_S0_VPP_12V 0x4
#define ConXS_BCR_S0_VPP_3V3 0x8
#define ConXS_IRCR_MODE (1 << 0)
#define ConXS_IRCR_SD (1 << 1)
#endif /* _TRIPEPS4_H_ */

41
include/asm-arm/arch-pxa/udc.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/udc.h
*
* This supports machine-specific differences in how the PXA2xx
* USB Device Controller (UDC) is wired.
*
*/
#include <asm/mach/udc_pxa2xx.h>
extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info);
static inline int udc_gpio_to_irq(unsigned gpio)
{
return IRQ_GPIO(gpio & GPIO_MD_MASK_NR);
}
static inline void udc_gpio_init_vbus(unsigned gpio)
{
pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_IN);
}
static inline void udc_gpio_init_pullup(unsigned gpio)
{
pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_OUT | GPIO_DFLT_LOW);
}
static inline int udc_gpio_get(unsigned gpio)
{
return (GPLR(gpio) & GPIO_bit(gpio)) != 0;
}
static inline void udc_gpio_set(unsigned gpio, int is_on)
{
int mask = GPIO_bit(gpio);
if (is_on)
GPSR(gpio) = mask;
else
GPCR(gpio) = mask;
}

38
include/asm-arm/arch-pxa/uncompress.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/uncompress.h
*
* Author: Nicolas Pitre
* Copyright: (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define FFUART ((volatile unsigned long *)0x40100000)
#define BTUART ((volatile unsigned long *)0x40200000)
#define STUART ((volatile unsigned long *)0x40700000)
#define HWUART ((volatile unsigned long *)0x41600000)
#define UART FFUART
static inline void putc(char c)
{
while (!(UART[5] & 0x20))
barrier();
UART[0] = c;
}
/*
* This does not append a newline
*/
static inline void flush(void)
{
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()

11
include/asm-arm/arch-pxa/vmalloc.h Normal file
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/*
* linux/include/asm-arm/arch-pxa/vmalloc.h
*
* Author: Nicolas Pitre
* Copyright: (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define VMALLOC_END (0xe8000000)