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Creation of Cybook 2416 (actually Gen4) repository

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This commit is contained in:
mlt
2009-12-18 17:10:00 +00:00
committed by godzil
commit 76f20f4d40
13791 changed files with 6812321 additions and 0 deletions
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15
include/asm-arm/hardware/arm_scu.h Normal file
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#ifndef ASMARM_HARDWARE_ARM_SCU_H
#define ASMARM_HARDWARE_ARM_SCU_H
#include <asm/arch/scu.h>
/*
* SCU registers
*/
#define SCU_CTRL 0x00
#define SCU_CONFIG 0x04
#define SCU_CPU_STATUS 0x08
#define SCU_INVALIDATE 0x0c
#define SCU_FPGA_REVISION 0x10
#endif

21
include/asm-arm/hardware/arm_timer.h Normal file
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#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H
#define __ASM_ARM_HARDWARE_ARM_TIMER_H
#define TIMER_LOAD 0x00
#define TIMER_VALUE 0x04
#define TIMER_CTRL 0x08
#define TIMER_CTRL_ONESHOT (1 << 0)
#define TIMER_CTRL_32BIT (1 << 1)
#define TIMER_CTRL_DIV1 (0 << 2)
#define TIMER_CTRL_DIV16 (1 << 2)
#define TIMER_CTRL_DIV256 (2 << 2)
#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
#define TIMER_CTRL_PERIODIC (1 << 6)
#define TIMER_CTRL_ENABLE (1 << 7)
#define TIMER_INTCLR 0x0c
#define TIMER_RIS 0x10
#define TIMER_MIS 0x14
#define TIMER_BGLOAD 0x18
#endif

16
include/asm-arm/hardware/arm_twd.h Normal file
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#ifndef __ASM_HARDWARE_TWD_H
#define __ASM_HARDWARE_TWD_H
#define TWD_TIMER_LOAD 0x00
#define TWD_TIMER_COUNTER 0x04
#define TWD_TIMER_CONTROL 0x08
#define TWD_TIMER_INTSTAT 0x0C
#define TWD_WDOG_LOAD 0x20
#define TWD_WDOG_COUNTER 0x24
#define TWD_WDOG_CONTROL 0x28
#define TWD_WDOG_INTSTAT 0x2C
#define TWD_WDOG_RESETSTAT 0x30
#define TWD_WDOG_DISABLE 0x34
#endif

56
include/asm-arm/hardware/cache-l2x0.h Normal file
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/*
* include/asm-arm/hardware/cache-l2x0.h
*
* Copyright (C) 2007 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_HARDWARE_L2X0_H
#define __ASM_ARM_HARDWARE_L2X0_H
#define L2X0_CACHE_ID 0x000
#define L2X0_CACHE_TYPE 0x004
#define L2X0_CTRL 0x100
#define L2X0_AUX_CTRL 0x104
#define L2X0_EVENT_CNT_CTRL 0x200
#define L2X0_EVENT_CNT1_CFG 0x204
#define L2X0_EVENT_CNT0_CFG 0x208
#define L2X0_EVENT_CNT1_VAL 0x20C
#define L2X0_EVENT_CNT0_VAL 0x210
#define L2X0_INTR_MASK 0x214
#define L2X0_MASKED_INTR_STAT 0x218
#define L2X0_RAW_INTR_STAT 0x21C
#define L2X0_INTR_CLEAR 0x220
#define L2X0_CACHE_SYNC 0x730
#define L2X0_INV_LINE_PA 0x770
#define L2X0_INV_WAY 0x77C
#define L2X0_CLEAN_LINE_PA 0x7B0
#define L2X0_CLEAN_LINE_IDX 0x7B8
#define L2X0_CLEAN_WAY 0x7BC
#define L2X0_CLEAN_INV_LINE_PA 0x7F0
#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
#define L2X0_CLEAN_INV_WAY 0x7FC
#define L2X0_LOCKDOWN_WAY_D 0x900
#define L2X0_LOCKDOWN_WAY_I 0x904
#define L2X0_TEST_OPERATION 0xF00
#define L2X0_LINE_DATA 0xF10
#define L2X0_LINE_TAG 0xF30
#define L2X0_DEBUG_CTRL 0xF40
#ifndef __ASSEMBLY__
extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
#endif
#endif

184
include/asm-arm/hardware/clps7111.h Normal file
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/*
* linux/include/asm-arm/hardware/clps7111.h
*
* This file contains the hardware definitions of the CLPS7111 internal
* registers.
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_HARDWARE_CLPS7111_H
#define __ASM_HARDWARE_CLPS7111_H
#define CLPS7111_PHYS_BASE (0x80000000)
#ifndef __ASSEMBLY__
#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off))
#define clps_readw(off) __raw_readw(CLPS7111_BASE + (off))
#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off))
#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off))
#define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off))
#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off))
#endif
#define PADR (0x0000)
#define PBDR (0x0001)
#define PDDR (0x0003)
#define PADDR (0x0040)
#define PBDDR (0x0041)
#define PDDDR (0x0043)
#define PEDR (0x0080)
#define PEDDR (0x00c0)
#define SYSCON1 (0x0100)
#define SYSFLG1 (0x0140)
#define MEMCFG1 (0x0180)
#define MEMCFG2 (0x01c0)
#define DRFPR (0x0200)
#define INTSR1 (0x0240)
#define INTMR1 (0x0280)
#define LCDCON (0x02c0)
#define TC1D (0x0300)
#define TC2D (0x0340)
#define RTCDR (0x0380)
#define RTCMR (0x03c0)
#define PMPCON (0x0400)
#define CODR (0x0440)
#define UARTDR1 (0x0480)
#define UBRLCR1 (0x04c0)
#define SYNCIO (0x0500)
#define PALLSW (0x0540)
#define PALMSW (0x0580)
#define STFCLR (0x05c0)
#define BLEOI (0x0600)
#define MCEOI (0x0640)
#define TEOI (0x0680)
#define TC1EOI (0x06c0)
#define TC2EOI (0x0700)
#define RTCEOI (0x0740)
#define UMSEOI (0x0780)
#define COEOI (0x07c0)
#define HALT (0x0800)
#define STDBY (0x0840)
#define FBADDR (0x1000)
#define SYSCON2 (0x1100)
#define SYSFLG2 (0x1140)
#define INTSR2 (0x1240)
#define INTMR2 (0x1280)
#define UARTDR2 (0x1480)
#define UBRLCR2 (0x14c0)
#define SS2DR (0x1500)
#define SRXEOF (0x1600)
#define SS2POP (0x16c0)
#define KBDEOI (0x1700)
/* common bits: SYSCON1 / SYSCON2 */
#define SYSCON_UARTEN (1 << 8)
#define SYSCON1_KBDSCAN(x) ((x) & 15)
#define SYSCON1_KBDSCANMASK (15)
#define SYSCON1_TC1M (1 << 4)
#define SYSCON1_TC1S (1 << 5)
#define SYSCON1_TC2M (1 << 6)
#define SYSCON1_TC2S (1 << 7)
#define SYSCON1_UART1EN SYSCON_UARTEN
#define SYSCON1_BZTOG (1 << 9)
#define SYSCON1_BZMOD (1 << 10)
#define SYSCON1_DBGEN (1 << 11)
#define SYSCON1_LCDEN (1 << 12)
#define SYSCON1_CDENTX (1 << 13)
#define SYSCON1_CDENRX (1 << 14)
#define SYSCON1_SIREN (1 << 15)
#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
#define SYSCON1_ADCKSEL_MASK (3 << 16)
#define SYSCON1_EXCKEN (1 << 18)
#define SYSCON1_WAKEDIS (1 << 19)
#define SYSCON1_IRTXM (1 << 20)
/* common bits: SYSFLG1 / SYSFLG2 */
#define SYSFLG_UBUSY (1 << 11)
#define SYSFLG_URXFE (1 << 22)
#define SYSFLG_UTXFF (1 << 23)
#define SYSFLG1_MCDR (1 << 0)
#define SYSFLG1_DCDET (1 << 1)
#define SYSFLG1_WUDR (1 << 2)
#define SYSFLG1_WUON (1 << 3)
#define SYSFLG1_CTS (1 << 8)
#define SYSFLG1_DSR (1 << 9)
#define SYSFLG1_DCD (1 << 10)
#define SYSFLG1_UBUSY SYSFLG_UBUSY
#define SYSFLG1_NBFLG (1 << 12)
#define SYSFLG1_RSTFLG (1 << 13)
#define SYSFLG1_PFFLG (1 << 14)
#define SYSFLG1_CLDFLG (1 << 15)
#define SYSFLG1_URXFE SYSFLG_URXFE
#define SYSFLG1_UTXFF SYSFLG_UTXFF
#define SYSFLG1_CRXFE (1 << 24)
#define SYSFLG1_CTXFF (1 << 25)
#define SYSFLG1_SSIBUSY (1 << 26)
#define SYSFLG1_ID (1 << 29)
#define SYSFLG2_SSRXOF (1 << 0)
#define SYSFLG2_RESVAL (1 << 1)
#define SYSFLG2_RESFRM (1 << 2)
#define SYSFLG2_SS2RXFE (1 << 3)
#define SYSFLG2_SS2TXFF (1 << 4)
#define SYSFLG2_SS2TXUF (1 << 5)
#define SYSFLG2_CKMODE (1 << 6)
#define SYSFLG2_UBUSY SYSFLG_UBUSY
#define SYSFLG2_URXFE SYSFLG_URXFE
#define SYSFLG2_UTXFF SYSFLG_UTXFF
#define LCDCON_GSEN (1 << 30)
#define LCDCON_GSMD (1 << 31)
#define SYSCON2_SERSEL (1 << 0)
#define SYSCON2_KBD6 (1 << 1)
#define SYSCON2_DRAMZ (1 << 2)
#define SYSCON2_KBWEN (1 << 3)
#define SYSCON2_SS2TXEN (1 << 4)
#define SYSCON2_PCCARD1 (1 << 5)
#define SYSCON2_PCCARD2 (1 << 6)
#define SYSCON2_SS2RXEN (1 << 7)
#define SYSCON2_UART2EN SYSCON_UARTEN
#define SYSCON2_SS2MAEN (1 << 9)
#define SYSCON2_OSTB (1 << 12)
#define SYSCON2_CLKENSL (1 << 13)
#define SYSCON2_BUZFREQ (1 << 14)
/* common bits: UARTDR1 / UARTDR2 */
#define UARTDR_FRMERR (1 << 8)
#define UARTDR_PARERR (1 << 9)
#define UARTDR_OVERR (1 << 10)
/* common bits: UBRLCR1 / UBRLCR2 */
#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
#define UBRLCR_BREAK (1 << 12)
#define UBRLCR_PRTEN (1 << 13)
#define UBRLCR_EVENPRT (1 << 14)
#define UBRLCR_XSTOP (1 << 15)
#define UBRLCR_FIFOEN (1 << 16)
#define UBRLCR_WRDLEN5 (0 << 17)
#define UBRLCR_WRDLEN6 (1 << 17)
#define UBRLCR_WRDLEN7 (2 << 17)
#define UBRLCR_WRDLEN8 (3 << 17)
#define UBRLCR_WRDLEN_MASK (3 << 17)
#define SYNCIO_SMCKEN (1 << 13)
#define SYNCIO_TXFRMEN (1 << 14)
#endif /* __ASM_HARDWARE_CLPS7111_H */

49
include/asm-arm/hardware/cs89712.h Normal file
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/*
* linux/include/asm-arm/hardware/cs89712.h
*
* This file contains the hardware definitions of the CS89712
* additional internal registers.
*
* Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_HARDWARE_CS89712_H
#define __ASM_HARDWARE_CS89712_H
/*
* CS89712 additional registers
*/
#define PCDR 0x0002 /* Port C Data register ---------------------------- */
#define PCDDR 0x0042 /* Port C Data Direction register ------------------ */
#define SDCONF 0x2300 /* SDRAM Configuration register ---------------------*/
#define SDRFPR 0x2340 /* SDRAM Refresh period register --------------------*/
#define SDCONF_ACTIVE (1 << 10)
#define SDCONF_CLKCTL (1 << 9)
#define SDCONF_WIDTH_4 (0 << 7)
#define SDCONF_WIDTH_8 (1 << 7)
#define SDCONF_WIDTH_16 (2 << 7)
#define SDCONF_WIDTH_32 (3 << 7)
#define SDCONF_SIZE_16 (0 << 5)
#define SDCONF_SIZE_64 (1 << 5)
#define SDCONF_SIZE_128 (2 << 5)
#define SDCONF_SIZE_256 (3 << 5)
#define SDCONF_CASLAT_2 (2)
#define SDCONF_CASLAT_3 (3)
#endif /* __ASM_HARDWARE_CS89712_H */

29
include/asm-arm/hardware/debug-8250.S Normal file
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/*
* linux/include/asm-arm/hardware/debug-8250.S
*
* Copyright (C) 1994-1999 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/serial_reg.h>
.macro senduart,rd,rx
strb \rd, [\rx, #UART_TX << UART_SHIFT]
.endm
.macro busyuart,rd,rx
1002: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
bne 1002b
.endm
.macro waituart,rd,rx
#ifdef FLOW_CONTROL
1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
tst \rd, #UART_MSR_CTS
beq 1001b
#endif
.endm

29
include/asm-arm/hardware/debug-pl01x.S Normal file
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/* linux/include/asm-arm/hardware/debug-pl01x.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/amba/serial.h>
.macro senduart,rd,rx
strb \rd, [\rx, #UART01x_DR]
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #UART01x_FR]
tst \rd, #UART01x_FR_TXFF
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #UART01x_FR]
tst \rd, #UART01x_FR_BUSY
bne 1001b
.endm

147
include/asm-arm/hardware/dec21285.h Normal file
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/*
* linux/include/asm-arm/hardware/dec21285.h
*
* Copyright (C) 1998 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* DC21285 registers
*/
#define DC21285_PCI_IACK 0x79000000
#define DC21285_ARMCSR_BASE 0x42000000
#define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
#define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
#define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
#define DC21285_FLASH 0x41000000
#define DC21285_PCI_IO 0x7c000000
#define DC21285_PCI_MEM 0x80000000
#ifndef __ASSEMBLY__
#include <asm/hardware.h>
#define DC21285_IO(x) ((volatile unsigned long *)(ARMCSR_BASE+(x)))
#else
#define DC21285_IO(x) (x)
#endif
#define CSR_PCICMD DC21285_IO(0x0004)
#define CSR_CLASSREV DC21285_IO(0x0008)
#define CSR_PCICACHELINESIZE DC21285_IO(0x000c)
#define CSR_PCICSRBASE DC21285_IO(0x0010)
#define CSR_PCICSRIOBASE DC21285_IO(0x0014)
#define CSR_PCISDRAMBASE DC21285_IO(0x0018)
#define CSR_PCIROMBASE DC21285_IO(0x0030)
#define CSR_MBOX0 DC21285_IO(0x0050)
#define CSR_MBOX1 DC21285_IO(0x0054)
#define CSR_MBOX2 DC21285_IO(0x0058)
#define CSR_MBOX3 DC21285_IO(0x005c)
#define CSR_DOORBELL DC21285_IO(0x0060)
#define CSR_DOORBELL_SETUP DC21285_IO(0x0064)
#define CSR_ROMWRITEREG DC21285_IO(0x0068)
#define CSR_CSRBASEMASK DC21285_IO(0x00f8)
#define CSR_CSRBASEOFFSET DC21285_IO(0x00fc)
#define CSR_SDRAMBASEMASK DC21285_IO(0x0100)
#define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104)
#define CSR_ROMBASEMASK DC21285_IO(0x0108)
#define CSR_SDRAMTIMING DC21285_IO(0x010c)
#define CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110)
#define CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114)
#define CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118)
#define CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c)
#define CSR_I2O_INFREEHEAD DC21285_IO(0x0120)
#define CSR_I2O_INPOSTTAIL DC21285_IO(0x0124)
#define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128)
#define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c)
#define CSR_I2O_INFREECOUNT DC21285_IO(0x0130)
#define CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134)
#define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138)
#define CSR_SA110_CNTL DC21285_IO(0x013c)
#define SA110_CNTL_INITCMPLETE (1 << 0)
#define SA110_CNTL_ASSERTSERR (1 << 1)
#define SA110_CNTL_RXSERR (1 << 3)
#define SA110_CNTL_SA110DRAMPARITY (1 << 4)
#define SA110_CNTL_PCISDRAMPARITY (1 << 5)
#define SA110_CNTL_DMASDRAMPARITY (1 << 6)
#define SA110_CNTL_DISCARDTIMER (1 << 8)
#define SA110_CNTL_PCINRESET (1 << 9)
#define SA110_CNTL_I2O_256 (0 << 10)
#define SA110_CNTL_I20_512 (1 << 10)
#define SA110_CNTL_I2O_1024 (2 << 10)
#define SA110_CNTL_I2O_2048 (3 << 10)
#define SA110_CNTL_I2O_4096 (4 << 10)
#define SA110_CNTL_I2O_8192 (5 << 10)
#define SA110_CNTL_I2O_16384 (6 << 10)
#define SA110_CNTL_I2O_32768 (7 << 10)
#define SA110_CNTL_WATCHDOG (1 << 13)
#define SA110_CNTL_ROMWIDTH_UNDEF (0 << 14)
#define SA110_CNTL_ROMWIDTH_16 (1 << 14)
#define SA110_CNTL_ROMWIDTH_32 (2 << 14)
#define SA110_CNTL_ROMWIDTH_8 (3 << 14)
#define SA110_CNTL_ROMACCESSTIME(x) ((x)<<16)
#define SA110_CNTL_ROMBURSTTIME(x) ((x)<<20)
#define SA110_CNTL_ROMTRISTATETIME(x) ((x)<<24)
#define SA110_CNTL_XCSDIR(x) ((x)<<28)
#define SA110_CNTL_PCICFN (1 << 31)
/*
* footbridge_cfn_mode() is used when we want
* to check whether we are the central function
*/
#define __footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN)
#if defined(CONFIG_FOOTBRIDGE_HOST) && defined(CONFIG_FOOTBRIDGE_ADDIN)
#define footbridge_cfn_mode() __footbridge_cfn_mode()
#elif defined(CONFIG_FOOTBRIDGE_HOST)
#define footbridge_cfn_mode() (1)
#else
#define footbridge_cfn_mode() (0)
#endif
#define CSR_PCIADDR_EXTN DC21285_IO(0x0140)
#define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)
#define CSR_XBUS_CYCLE DC21285_IO(0x0148)
#define CSR_XBUS_IOSTROBE DC21285_IO(0x014c)
#define CSR_DOORBELL_PCI DC21285_IO(0x0150)
#define CSR_DOORBELL_SA110 DC21285_IO(0x0154)
#define CSR_UARTDR DC21285_IO(0x0160)
#define CSR_RXSTAT DC21285_IO(0x0164)
#define CSR_H_UBRLCR DC21285_IO(0x0168)
#define CSR_M_UBRLCR DC21285_IO(0x016c)
#define CSR_L_UBRLCR DC21285_IO(0x0170)
#define CSR_UARTCON DC21285_IO(0x0174)
#define CSR_UARTFLG DC21285_IO(0x0178)
#define CSR_IRQ_STATUS DC21285_IO(0x0180)
#define CSR_IRQ_RAWSTATUS DC21285_IO(0x0184)
#define CSR_IRQ_ENABLE DC21285_IO(0x0188)
#define CSR_IRQ_DISABLE DC21285_IO(0x018c)
#define CSR_IRQ_SOFT DC21285_IO(0x0190)
#define CSR_FIQ_STATUS DC21285_IO(0x0280)
#define CSR_FIQ_RAWSTATUS DC21285_IO(0x0284)
#define CSR_FIQ_ENABLE DC21285_IO(0x0288)
#define CSR_FIQ_DISABLE DC21285_IO(0x028c)
#define CSR_FIQ_SOFT DC21285_IO(0x0290)
#define CSR_TIMER1_LOAD DC21285_IO(0x0300)
#define CSR_TIMER1_VALUE DC21285_IO(0x0304)
#define CSR_TIMER1_CNTL DC21285_IO(0x0308)
#define CSR_TIMER1_CLR DC21285_IO(0x030c)
#define CSR_TIMER2_LOAD DC21285_IO(0x0320)
#define CSR_TIMER2_VALUE DC21285_IO(0x0324)
#define CSR_TIMER2_CNTL DC21285_IO(0x0328)
#define CSR_TIMER2_CLR DC21285_IO(0x032c)
#define CSR_TIMER3_LOAD DC21285_IO(0x0340)
#define CSR_TIMER3_VALUE DC21285_IO(0x0344)
#define CSR_TIMER3_CNTL DC21285_IO(0x0348)
#define CSR_TIMER3_CLR DC21285_IO(0x034c)
#define CSR_TIMER4_LOAD DC21285_IO(0x0360)
#define CSR_TIMER4_VALUE DC21285_IO(0x0364)
#define CSR_TIMER4_CNTL DC21285_IO(0x0368)
#define CSR_TIMER4_CLR DC21285_IO(0x036c)
#define TIMER_CNTL_ENABLE (1 << 7)
#define TIMER_CNTL_AUTORELOAD (1 << 6)
#define TIMER_CNTL_DIV1 (0)
#define TIMER_CNTL_DIV16 (1 << 2)
#define TIMER_CNTL_DIV256 (2 << 2)
#define TIMER_CNTL_CNTEXT (3 << 2)

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/*
* include/asm-arm/hardware/entry-macro-iomd.S
*
* Low-level IRQ helper macros for IOC/IOMD based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/* IOC / IOMD based hardware */
#include <asm/hardware/iomd.h>
.equ ioc_base_high, IOC_BASE & 0xff000000
.equ ioc_base_low, IOC_BASE & 0x00ff0000
.macro disable_fiq
mov r12, #ioc_base_high
.if ioc_base_low
orr r12, r12, #ioc_base_low
.endif
strb r12, [r12, #0x38] @ Disable FIQ register
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #ioc_base_high @ point at IOC
.if ioc_base_low
orr r4, r4, #ioc_base_low
.endif
ldrb \irqstat, [r4, #IOMD_IRQREQB] @ get high priority first
ldr \base, =irq_prio_h
teq \irqstat, #0
#ifdef IOMD_BASE
ldreqb \irqstat, [r4, #IOMD_DMAREQ] @ get dma
addeq \base, \base, #256 @ irq_prio_h table size
teqeq \irqstat, #0
bne 2406f
#endif
ldreqb \irqstat, [r4, #IOMD_IRQREQA] @ get low priority
addeq \base, \base, #256 @ irq_prio_d table size
teqeq \irqstat, #0
#ifdef IOMD_IRQREQC
ldreqb \irqstat, [r4, #IOMD_IRQREQC]
addeq \base, \base, #256 @ irq_prio_l table size
teqeq \irqstat, #0
#endif
#ifdef IOMD_IRQREQD
ldreqb \irqstat, [r4, #IOMD_IRQREQD]
addeq \base, \base, #256 @ irq_prio_lc table size
teqeq \irqstat, #0
#endif
2406: ldrneb \irqnr, [\base, \irqstat] @ get IRQ number
.endm
/*
* Interrupt table (incorporates priority). Please note that we
* rely on the order of these tables (see above code).
*/
.align 5
irq_prio_h: .byte 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
.byte 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
.byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
#ifdef IOMD_BASE
irq_prio_d: .byte 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
#endif
irq_prio_l: .byte 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
.byte 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
.byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
#ifdef IOMD_IRQREQC
irq_prio_lc: .byte 24,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
.byte 28,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
.byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
#endif
#ifdef IOMD_IRQREQD
irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
.byte 44,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
.byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
#endif

40
include/asm-arm/hardware/ep7211.h Normal file
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/*
* linux/include/asm-arm/hardware/ep7211.h
*
* This file contains the hardware definitions of the EP7211 internal
* registers.
*
* Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_HARDWARE_EP7211_H
#define __ASM_HARDWARE_EP7211_H
#include <asm/hardware/clps7111.h>
/*
* define EP7211_BASE to be the base address of the region
* you want to access.
*/
#define EP7211_PHYS_BASE (0x80000000)
/*
* XXX miket@bluemug.com: need to introduce EP7211 registers (those not
* present in 7212) here.
*/
#endif /* __ASM_HARDWARE_EP7211_H */

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include/asm-arm/hardware/ep7212.h Normal file
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/*
* linux/include/asm-arm/hardware/ep7212.h
*
* This file contains the hardware definitions of the EP7212 internal
* registers.
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_HARDWARE_EP7212_H
#define __ASM_HARDWARE_EP7212_H
/*
* define EP7212_BASE to be the base address of the region
* you want to access.
*/
#define EP7212_PHYS_BASE (0x80000000)
#ifndef __ASSEMBLY__
#define ep_readl(off) __raw_readl(EP7212_BASE + (off))
#define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off))
#endif
/*
* These registers are specific to the EP7212 only
*/
#define DAIR 0x2000
#define DAIR0 0x2040
#define DAIDR1 0x2080
#define DAIDR2 0x20c0
#define DAISR 0x2100
#define SYSCON3 0x2200
#define INTSR3 0x2240
#define INTMR3 0x2280
#define LEDFLSH 0x22c0
#define DAIR_DAIEN (1 << 16)
#define DAIR_ECS (1 << 17)
#define DAIR_LCTM (1 << 19)
#define DAIR_LCRM (1 << 20)
#define DAIR_RCTM (1 << 21)
#define DAIR_RCRM (1 << 22)
#define DAIR_LBM (1 << 23)
#define DAIDR2_FIFOEN (1 << 15)
#define DAIDR2_FIFOLEFT (0x0d << 16)
#define DAIDR2_FIFORIGHT (0x11 << 16)
#define DAISR_RCTS (1 << 0)
#define DAISR_RCRS (1 << 1)
#define DAISR_LCTS (1 << 2)
#define DAISR_LCRS (1 << 3)
#define DAISR_RCTU (1 << 4)
#define DAISR_RCRO (1 << 5)
#define DAISR_LCTU (1 << 6)
#define DAISR_LCRO (1 << 7)
#define DAISR_RCNF (1 << 8)
#define DAISR_RCNE (1 << 9)
#define DAISR_LCNF (1 << 10)
#define DAISR_LCNE (1 << 11)
#define DAISR_FIFO (1 << 12)
#define SYSCON3_ADCCON (1 << 0)
#define SYSCON3_DAISEL (1 << 3)
#define SYSCON3_ADCCKNSEN (1 << 4)
#define SYSCON3_FASTWAKE (1 << 8)
#define SYSCON3_DAIEN (1 << 9)
#endif /* __ASM_HARDWARE_EP7212_H */

42
include/asm-arm/hardware/gic.h Normal file
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/*
* linux/include/asm-arm/hardware/gic.h
*
* Copyright (C) 2002 ARM Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_HARDWARE_GIC_H
#define __ASM_ARM_HARDWARE_GIC_H
#include <linux/compiler.h>
#define GIC_CPU_CTRL 0x00
#define GIC_CPU_PRIMASK 0x04
#define GIC_CPU_BINPOINT 0x08
#define GIC_CPU_INTACK 0x0c
#define GIC_CPU_EOI 0x10
#define GIC_CPU_RUNNINGPRI 0x14
#define GIC_CPU_HIGHPRI 0x18
#define GIC_DIST_CTRL 0x000
#define GIC_DIST_CTR 0x004
#define GIC_DIST_ENABLE_SET 0x100
#define GIC_DIST_ENABLE_CLEAR 0x180
#define GIC_DIST_PENDING_SET 0x200
#define GIC_DIST_PENDING_CLEAR 0x280
#define GIC_DIST_ACTIVE_BIT 0x300
#define GIC_DIST_PRI 0x400
#define GIC_DIST_TARGET 0x800
#define GIC_DIST_CONFIG 0xc00
#define GIC_DIST_SOFTINT 0xf00
#ifndef __ASSEMBLY__
void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start);
void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
#endif
#endif

38
include/asm-arm/hardware/icst307.h Normal file
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/*
* linux/include/asm-arm/hardware/icst307.h
*
* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Support functions for calculating clocks/divisors for the ICS307
* clock generators. See http://www.icst.com/ for more information
* on these devices.
*
* This file is similar to the icst525.h file
*/
#ifndef ASMARM_HARDWARE_ICST307_H
#define ASMARM_HARDWARE_ICST307_H
struct icst307_params {
unsigned long ref;
unsigned long vco_max; /* inclusive */
unsigned short vd_min; /* inclusive */
unsigned short vd_max; /* inclusive */
unsigned char rd_min; /* inclusive */
unsigned char rd_max; /* inclusive */
};
struct icst307_vco {
unsigned short v;
unsigned char r;
unsigned char s;
};
unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco);
struct icst307_vco icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq);
struct icst307_vco icst307_ps_to_vco(const struct icst307_params *p, unsigned long period);
#endif

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include/asm-arm/hardware/icst525.h Normal file
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/*
* linux/include/asm-arm/hardware/icst525.h
*
* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Support functions for calculating clocks/divisors for the ICST525
* clock generators. See http://www.icst.com/ for more information
* on these devices.
*/
#ifndef ASMARM_HARDWARE_ICST525_H
#define ASMARM_HARDWARE_ICST525_H
struct icst525_params {
unsigned long ref;
unsigned long vco_max; /* inclusive */
unsigned short vd_min; /* inclusive */
unsigned short vd_max; /* inclusive */
unsigned char rd_min; /* inclusive */
unsigned char rd_max; /* inclusive */
};
struct icst525_vco {
unsigned short v;
unsigned char r;
unsigned char s;
};
unsigned long icst525_khz(const struct icst525_params *p, struct icst525_vco vco);
struct icst525_vco icst525_khz_to_vco(const struct icst525_params *p, unsigned long freq);
struct icst525_vco icst525_ps_to_vco(const struct icst525_params *p, unsigned long period);
#endif

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include/asm-arm/hardware/ioc.h Normal file
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/*
* linux/include/asm-arm/hardware/ioc.h
*
* Copyright (C) Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Use these macros to read/write the IOC. All it does is perform the actual
* read/write.
*/
#ifndef __ASMARM_HARDWARE_IOC_H
#define __ASMARM_HARDWARE_IOC_H
#ifndef __ASSEMBLY__
/*
* We use __raw_base variants here so that we give the compiler the
* chance to keep IOC_BASE in a register.
*/
#define ioc_readb(off) __raw_readb(IOC_BASE + (off))
#define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off))
#endif
#define IOC_CONTROL (0x00)
#define IOC_KARTTX (0x04)
#define IOC_KARTRX (0x04)
#define IOC_IRQSTATA (0x10)
#define IOC_IRQREQA (0x14)
#define IOC_IRQCLRA (0x14)
#define IOC_IRQMASKA (0x18)
#define IOC_IRQSTATB (0x20)
#define IOC_IRQREQB (0x24)
#define IOC_IRQMASKB (0x28)
#define IOC_FIQSTAT (0x30)
#define IOC_FIQREQ (0x34)
#define IOC_FIQMASK (0x38)
#define IOC_T0CNTL (0x40)
#define IOC_T0LTCHL (0x40)
#define IOC_T0CNTH (0x44)
#define IOC_T0LTCHH (0x44)
#define IOC_T0GO (0x48)
#define IOC_T0LATCH (0x4c)
#define IOC_T1CNTL (0x50)
#define IOC_T1LTCHL (0x50)
#define IOC_T1CNTH (0x54)
#define IOC_T1LTCHH (0x54)
#define IOC_T1GO (0x58)
#define IOC_T1LATCH (0x5c)
#define IOC_T2CNTL (0x60)
#define IOC_T2LTCHL (0x60)
#define IOC_T2CNTH (0x64)
#define IOC_T2LTCHH (0x64)
#define IOC_T2GO (0x68)
#define IOC_T2LATCH (0x6c)
#define IOC_T3CNTL (0x70)
#define IOC_T3LTCHL (0x70)
#define IOC_T3CNTH (0x74)
#define IOC_T3LTCHH (0x74)
#define IOC_T3GO (0x78)
#define IOC_T3LATCH (0x7c)
#endif

226
include/asm-arm/hardware/iomd.h Normal file
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/*
* linux/include/asm-arm/hardware/iomd.h
*
* Copyright (C) 1999 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This file contains information out the IOMD ASIC used in the
* Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
*/
#ifndef __ASMARM_HARDWARE_IOMD_H
#define __ASMARM_HARDWARE_IOMD_H
#ifndef __ASSEMBLY__
/*
* We use __raw_base variants here so that we give the compiler the
* chance to keep IOC_BASE in a register.
*/
#define iomd_readb(off) __raw_readb(IOMD_BASE + (off))
#define iomd_readl(off) __raw_readl(IOMD_BASE + (off))
#define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off))
#define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off))
#endif
#define IOMD_CONTROL (0x000)
#define IOMD_KARTTX (0x004)
#define IOMD_KARTRX (0x004)
#define IOMD_KCTRL (0x008)
#ifdef CONFIG_ARCH_CLPS7500
#define IOMD_IOLINES (0x00C)
#endif
#define IOMD_IRQSTATA (0x010)
#define IOMD_IRQREQA (0x014)
#define IOMD_IRQCLRA (0x014)
#define IOMD_IRQMASKA (0x018)
#ifdef CONFIG_ARCH_CLPS7500
#define IOMD_SUSMODE (0x01C)
#endif
#define IOMD_IRQSTATB (0x020)
#define IOMD_IRQREQB (0x024)
#define IOMD_IRQMASKB (0x028)
#define IOMD_FIQSTAT (0x030)
#define IOMD_FIQREQ (0x034)
#define IOMD_FIQMASK (0x038)
#ifdef CONFIG_ARCH_CLPS7500
#define IOMD_CLKCTL (0x03C)
#endif
#define IOMD_T0CNTL (0x040)
#define IOMD_T0LTCHL (0x040)
#define IOMD_T0CNTH (0x044)
#define IOMD_T0LTCHH (0x044)
#define IOMD_T0GO (0x048)
#define IOMD_T0LATCH (0x04c)
#define IOMD_T1CNTL (0x050)
#define IOMD_T1LTCHL (0x050)
#define IOMD_T1CNTH (0x054)
#define IOMD_T1LTCHH (0x054)
#define IOMD_T1GO (0x058)
#define IOMD_T1LATCH (0x05c)
#ifdef CONFIG_ARCH_CLPS7500
#define IOMD_IRQSTATC (0x060)
#define IOMD_IRQREQC (0x064)
#define IOMD_IRQMASKC (0x068)
#define IOMD_VIDMUX (0x06c)
#define IOMD_IRQSTATD (0x070)
#define IOMD_IRQREQD (0x074)
#define IOMD_IRQMASKD (0x078)
#endif
#define IOMD_ROMCR0 (0x080)
#define IOMD_ROMCR1 (0x084)
#ifdef CONFIG_ARCH_RPC
#define IOMD_DRAMCR (0x088)
#endif
#define IOMD_REFCR (0x08C)
#define IOMD_FSIZE (0x090)
#define IOMD_ID0 (0x094)
#define IOMD_ID1 (0x098)
#define IOMD_VERSION (0x09C)
#ifdef CONFIG_ARCH_RPC
#define IOMD_MOUSEX (0x0A0)
#define IOMD_MOUSEY (0x0A4)
#endif
#ifdef CONFIG_ARCH_CLPS7500
#define IOMD_MSEDAT (0x0A8)
#define IOMD_MSECTL (0x0Ac)
#endif
#ifdef CONFIG_ARCH_RPC
#define IOMD_DMATCR (0x0C0)
#endif
#define IOMD_IOTCR (0x0C4)
#define IOMD_ECTCR (0x0C8)
#ifdef CONFIG_ARCH_RPC
#define IOMD_DMAEXT (0x0CC)
#endif
#ifdef CONFIG_ARCH_CLPS7500
#define IOMD_ASTCR (0x0CC)
#define IOMD_DRAMCR (0x0D0)
#define IOMD_SELFREF (0x0D4)
#define IOMD_ATODICR (0x0E0)
#define IOMD_ATODSR (0x0E4)
#define IOMD_ATODCC (0x0E8)
#define IOMD_ATODCNT1 (0x0EC)
#define IOMD_ATODCNT2 (0x0F0)
#define IOMD_ATODCNT3 (0x0F4)
#define IOMD_ATODCNT4 (0x0F8)
#endif
#ifdef CONFIG_ARCH_RPC
#define DMA_EXT_IO0 1
#define DMA_EXT_IO1 2
#define DMA_EXT_IO2 4
#define DMA_EXT_IO3 8
#define IOMD_IO0CURA (0x100)
#define IOMD_IO0ENDA (0x104)
#define IOMD_IO0CURB (0x108)
#define IOMD_IO0ENDB (0x10C)
#define IOMD_IO0CR (0x110)
#define IOMD_IO0ST (0x114)
#define IOMD_IO1CURA (0x120)
#define IOMD_IO1ENDA (0x124)
#define IOMD_IO1CURB (0x128)
#define IOMD_IO1ENDB (0x12C)
#define IOMD_IO1CR (0x130)
#define IOMD_IO1ST (0x134)
#define IOMD_IO2CURA (0x140)
#define IOMD_IO2ENDA (0x144)
#define IOMD_IO2CURB (0x148)
#define IOMD_IO2ENDB (0x14C)
#define IOMD_IO2CR (0x150)
#define IOMD_IO2ST (0x154)
#define IOMD_IO3CURA (0x160)
#define IOMD_IO3ENDA (0x164)
#define IOMD_IO3CURB (0x168)
#define IOMD_IO3ENDB (0x16C)
#define IOMD_IO3CR (0x170)
#define IOMD_IO3ST (0x174)
#endif
#define IOMD_SD0CURA (0x180)
#define IOMD_SD0ENDA (0x184)
#define IOMD_SD0CURB (0x188)
#define IOMD_SD0ENDB (0x18C)
#define IOMD_SD0CR (0x190)
#define IOMD_SD0ST (0x194)
#ifdef CONFIG_ARCH_RPC
#define IOMD_SD1CURA (0x1A0)
#define IOMD_SD1ENDA (0x1A4)
#define IOMD_SD1CURB (0x1A8)
#define IOMD_SD1ENDB (0x1AC)
#define IOMD_SD1CR (0x1B0)
#define IOMD_SD1ST (0x1B4)
#endif
#define IOMD_CURSCUR (0x1C0)
#define IOMD_CURSINIT (0x1C4)
#define IOMD_VIDCUR (0x1D0)
#define IOMD_VIDEND (0x1D4)
#define IOMD_VIDSTART (0x1D8)
#define IOMD_VIDINIT (0x1DC)
#define IOMD_VIDCR (0x1E0)
#define IOMD_DMASTAT (0x1F0)
#define IOMD_DMAREQ (0x1F4)
#define IOMD_DMAMASK (0x1F8)
#define DMA_END_S (1 << 31)
#define DMA_END_L (1 << 30)
#define DMA_CR_C 0x80
#define DMA_CR_D 0x40
#define DMA_CR_E 0x20
#define DMA_ST_OFL 4
#define DMA_ST_INT 2
#define DMA_ST_AB 1
/*
* DMA (MEMC) compatibility
*/
#define HALF_SAM vram_half_sam
#define VDMA_ALIGNMENT (HALF_SAM * 2)
#define VDMA_XFERSIZE (HALF_SAM)
#define VDMA_INIT IOMD_VIDINIT
#define VDMA_START IOMD_VIDSTART
#define VDMA_END IOMD_VIDEND
#ifndef __ASSEMBLY__
extern unsigned int vram_half_sam;
#define video_set_dma(start,end,offset) \
do { \
outl (SCREEN_START + start, VDMA_START); \
outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \
if (offset >= end - VDMA_XFERSIZE) \
offset |= 0x40000000; \
outl (SCREEN_START + offset, VDMA_INIT); \
} while (0)
#endif
#endif

324
include/asm-arm/hardware/iop3xx.h Normal file
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@@ -0,0 +1,324 @@
/*
* include/asm-arm/hardware/iop3xx.h
*
* Intel IOP32X and IOP33X register definitions
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __IOP3XX_H
#define __IOP3XX_H
/*
* IOP3XX GPIO handling
*/
#define GPIO_IN 0
#define GPIO_OUT 1
#define GPIO_LOW 0
#define GPIO_HIGH 1
#define IOP3XX_GPIO_LINE(x) (x)
#ifndef __ASSEMBLY__
extern void gpio_line_config(int line, int direction);
extern int gpio_line_get(int line);
extern void gpio_line_set(int line, int value);
#endif
/*
* IOP3XX processor registers
*/
#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
#define IOP3XX_PERIPHERAL_SIZE 0x00002000
#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
IOP3XX_PERIPHERAL_SIZE - 1)
#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
IOP3XX_PERIPHERAL_SIZE - 1)
#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
(IOP3XX_PERIPHERAL_PHYS_BASE\
- IOP3XX_PERIPHERAL_VIRT_BASE))
#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
/* Address Translation Unit */
#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
/* Messaging Unit */
#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
/* DMA Controller */
#define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400)
#define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404)
#define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c)
#define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410)
#define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414)
#define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418)
#define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c)
#define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420)
#define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424)
#define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440)
#define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444)
#define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c)
#define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450)
#define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454)
#define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458)
#define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c)
#define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460)
#define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464)
/* Peripheral bus interface */
#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
/* Peripheral performance monitoring unit */
#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
/* PERCR0 DOESN'T EXIST - index from 1! */
#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
/* General Purpose I/O */
#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0000)
#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
/* Timers */
#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
#define IOP_TMR_EN 0x02
#define IOP_TMR_RELOAD 0x04
#define IOP_TMR_PRIVILEGED 0x08
#define IOP_TMR_RATIO_1_1 0x00
/* Application accelerator unit */
#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800)
#define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804)
#define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808)
#define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c)
#define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810)
#define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814)
#define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818)
#define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c)
#define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820)
#define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824)
#define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828)
#define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c)
#define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830)
#define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834)
#define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838)
#define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c)
#define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840)
#define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844)
#define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848)
#define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c)
#define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850)
#define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854)
#define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858)
#define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c)
#define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860)
#define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864)
#define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868)
#define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c)
#define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870)
#define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874)
#define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878)
#define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c)
#define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880)
#define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884)
#define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888)
#define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c)
#define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890)
#define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894)
#define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898)
#define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c)
#define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0)
#define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4)
/* I2C bus interface unit */
#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
/*
* IOP3XX I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000
#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0)
#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR)
#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\
IOP3XX_PCI_IO_WINDOW_SIZE - 1)
#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\
IOP3XX_PCI_IO_WINDOW_SIZE - 1)
#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) addr -\
IOP3XX_PCI_LOWER_IO_PA) +\
IOP3XX_PCI_LOWER_IO_VA)
#ifndef __ASSEMBLY__
void iop3xx_map_io(void);
void iop_init_cp6_handler(void);
void iop_init_time(unsigned long tickrate);
unsigned long iop_gettimeoffset(void);
static inline void write_tmr0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
}
static inline void write_tmr1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
}
static inline u32 read_tcr0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
return val;
}
static inline u32 read_tcr1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
return val;
}
static inline void write_trr0(u32 val)
{
asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
}
static inline void write_trr1(u32 val)
{
asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
}
static inline void write_tisr(u32 val)
{
asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
}
extern struct platform_device iop3xx_i2c0_device;
extern struct platform_device iop3xx_i2c1_device;
#endif
#endif

48
include/asm-arm/hardware/linkup-l1110.h Normal file
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/*
*
* Definitions for H3600 Handheld Computer
*
* Copyright 2001 Compaq Computer Corporation.
*
* Use consistent with the GNU GPL is permitted,
* provided that this copyright notice is
* preserved in its entirety in all copies and derived works.
*
* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
* FITNESS FOR ANY PARTICULAR PURPOSE.
*
* Author: Jamey Hicks.
*
*/
/* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */
/* PC Card Status Register */
#define LINKUP_PRS_S1 (1 << 0) /* voltage control bits S1-S4 */
#define LINKUP_PRS_S2 (1 << 1)
#define LINKUP_PRS_S3 (1 << 2)
#define LINKUP_PRS_S4 (1 << 3)
#define LINKUP_PRS_BVD1 (1 << 4)
#define LINKUP_PRS_BVD2 (1 << 5)
#define LINKUP_PRS_VS1 (1 << 6)
#define LINKUP_PRS_VS2 (1 << 7)
#define LINKUP_PRS_RDY (1 << 8)
#define LINKUP_PRS_CD1 (1 << 9)
#define LINKUP_PRS_CD2 (1 << 10)
/* PC Card Command Register */
#define LINKUP_PRC_S1 (1 << 0)
#define LINKUP_PRC_S2 (1 << 1)
#define LINKUP_PRC_S3 (1 << 2)
#define LINKUP_PRC_S4 (1 << 3)
#define LINKUP_PRC_RESET (1 << 4)
#define LINKUP_PRC_APOE (1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */
#define LINKUP_PRC_CFE (1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */
#define LINKUP_PRC_SOE (1 << 7) /* signal output driver enable */
#define LINKUP_PRC_SSP (1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */
#define LINKUP_PRC_MBZ (1 << 15) /* must be zero */
struct linkup_l1110 {
volatile short prc;
};

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include/asm-arm/hardware/locomo.h Normal file
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/*
* linux/include/asm-arm/hardware/locomo.h
*
* This file contains the definitions for the LoCoMo G/A Chip
*
* (C) Copyright 2004 John Lenz
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Based on sa1111.h
*/
#ifndef _ASM_ARCH_LOCOMO
#define _ASM_ARCH_LOCOMO
#define locomo_writel(val,addr) ({ *(volatile u16 *)(addr) = (val); })
#define locomo_readl(addr) (*(volatile u16 *)(addr))
/* LOCOMO version */
#define LOCOMO_VER 0x00
/* Pin status */
#define LOCOMO_ST 0x04
/* Pin status */
#define LOCOMO_C32K 0x08
/* Interrupt controller */
#define LOCOMO_ICR 0x0C
/* MCS decoder for boot selecting */
#define LOCOMO_MCSX0 0x10
#define LOCOMO_MCSX1 0x14
#define LOCOMO_MCSX2 0x18
#define LOCOMO_MCSX3 0x1c
/* Touch panel controller */
#define LOCOMO_ASD 0x20 /* AD start delay */
#define LOCOMO_HSD 0x28 /* HSYS delay */
#define LOCOMO_HSC 0x2c /* HSYS period */
#define LOCOMO_TADC 0x30 /* tablet ADC clock */
/* Long time timer */
#define LOCOMO_LTC 0xd8 /* LTC interrupt setting */
#define LOCOMO_LTINT 0xdc /* LTC interrupt */
/* DAC control signal for LCD (COMADJ ) */
#define LOCOMO_DAC 0xe0
/* DAC control */
#define LOCOMO_DAC_SCLOEB 0x08 /* SCL pin output data */
#define LOCOMO_DAC_TEST 0x04 /* Test bit */
#define LOCOMO_DAC_SDA 0x02 /* SDA pin level (read-only) */
#define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */
/* SPI interface */
#define LOCOMO_SPI 0x60
#define LOCOMO_SPIMD 0x00 /* SPI mode setting */
#define LOCOMO_SPICT 0x04 /* SPI mode control */
#define LOCOMO_SPIST 0x08 /* SPI status */
#define LOCOMO_SPIIS 0x10 /* SPI interrupt status */
#define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */
#define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */
#define LOCOMO_SPIIR 0x1c /* SPI interrupt request */
#define LOCOMO_SPITD 0x20 /* SPI transfer data write */
#define LOCOMO_SPIRD 0x24 /* SPI receive data read */
#define LOCOMO_SPITS 0x28 /* SPI transfer data shift */
#define LOCOMO_SPIRS 0x2C /* SPI receive data shift */
#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
#define LOCOMO_SPI_OVRN (1 << 2) /* Over Run bit */
#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
#define LOCOMO_SPI_RFR (1) /* read buffer bit */
/* GPIO */
#define LOCOMO_GPD 0x90 /* GPIO direction */
#define LOCOMO_GPE 0x94 /* GPIO input enable */
#define LOCOMO_GPL 0x98 /* GPIO level */
#define LOCOMO_GPO 0x9c /* GPIO out data setteing */
#define LOCOMO_GRIE 0xa0 /* GPIO rise detection */
#define LOCOMO_GFIE 0xa4 /* GPIO fall detection */
#define LOCOMO_GIS 0xa8 /* GPIO edge detection status */
#define LOCOMO_GWE 0xac /* GPIO status write enable */
#define LOCOMO_GIE 0xb0 /* GPIO interrupt enable */
#define LOCOMO_GIR 0xb4 /* GPIO interrupt request */
#define LOCOMO_GPIO(Nb) (0x01 << (Nb))
#define LOCOMO_GPIO_RTS LOCOMO_GPIO(0)
#define LOCOMO_GPIO_CTS LOCOMO_GPIO(1)
#define LOCOMO_GPIO_DSR LOCOMO_GPIO(2)
#define LOCOMO_GPIO_DTR LOCOMO_GPIO(3)
#define LOCOMO_GPIO_LCD_VSHA_ON LOCOMO_GPIO(4)
#define LOCOMO_GPIO_LCD_VSHD_ON LOCOMO_GPIO(5)
#define LOCOMO_GPIO_LCD_VEE_ON LOCOMO_GPIO(6)
#define LOCOMO_GPIO_LCD_MOD LOCOMO_GPIO(7)
#define LOCOMO_GPIO_DAC_ON LOCOMO_GPIO(8)
#define LOCOMO_GPIO_FL_VR LOCOMO_GPIO(9)
#define LOCOMO_GPIO_DAC_SDATA LOCOMO_GPIO(10)
#define LOCOMO_GPIO_DAC_SCK LOCOMO_GPIO(11)
#define LOCOMO_GPIO_DAC_SLOAD LOCOMO_GPIO(12)
/* Start the definitions of the devices. Each device has an initial
* base address and a series of offsets from that base address. */
/* Keyboard controller */
#define LOCOMO_KEYBOARD 0x40
#define LOCOMO_KIB 0x00 /* KIB level */
#define LOCOMO_KSC 0x04 /* KSTRB control */
#define LOCOMO_KCMD 0x08 /* KSTRB command */
#define LOCOMO_KIC 0x0c /* Key interrupt */
/* Front light adjustment controller */
#define LOCOMO_FRONTLIGHT 0xc8
#define LOCOMO_ALS 0x00 /* Adjust light cycle */
#define LOCOMO_ALD 0x04 /* Adjust light duty */
#define LOCOMO_ALC_EN 0x8000
/* Backlight controller: TFT signal */
#define LOCOMO_BACKLIGHT 0x38
#define LOCOMO_TC 0x00 /* TFT control signal */
#define LOCOMO_CPSD 0x04 /* CPS delay */
/* Audio controller */
#define LOCOMO_AUDIO 0x54
#define LOCOMO_ACC 0x00 /* Audio clock */
#define LOCOMO_PAIF 0x7C /* PCM audio interface */
/* Audio clock */
#define LOCOMO_ACC_XON 0x80
#define LOCOMO_ACC_XEN 0x40
#define LOCOMO_ACC_XSEL0 0x00
#define LOCOMO_ACC_XSEL1 0x20
#define LOCOMO_ACC_MCLKEN 0x10
#define LOCOMO_ACC_64FSEN 0x08
#define LOCOMO_ACC_CLKSEL000 0x00 /* mclk 2 */
#define LOCOMO_ACC_CLKSEL001 0x01 /* mclk 3 */
#define LOCOMO_ACC_CLKSEL010 0x02 /* mclk 4 */
#define LOCOMO_ACC_CLKSEL011 0x03 /* mclk 6 */
#define LOCOMO_ACC_CLKSEL100 0x04 /* mclk 8 */
#define LOCOMO_ACC_CLKSEL101 0x05 /* mclk 12 */
/* PCM audio interface */
#define LOCOMO_PAIF_SCINV 0x20
#define LOCOMO_PAIF_SCEN 0x10
#define LOCOMO_PAIF_LRCRST 0x08
#define LOCOMO_PAIF_LRCEVE 0x04
#define LOCOMO_PAIF_LRCINV 0x02
#define LOCOMO_PAIF_LRCEN 0x01
/* LED controller */
#define LOCOMO_LED 0xe8
#define LOCOMO_LPT0 0x00
#define LOCOMO_LPT1 0x04
/* LED control */
#define LOCOMO_LPT_TOFH 0x80
#define LOCOMO_LPT_TOFL 0x08
#define LOCOMO_LPT_TOH(TOH) ((TOH & 0x7) << 4)
#define LOCOMO_LPT_TOL(TOL) ((TOL & 0x7))
extern struct bus_type locomo_bus_type;
#define LOCOMO_DEVID_KEYBOARD 0
#define LOCOMO_DEVID_FRONTLIGHT 1
#define LOCOMO_DEVID_BACKLIGHT 2
#define LOCOMO_DEVID_AUDIO 3
#define LOCOMO_DEVID_LED 4
#define LOCOMO_DEVID_UART 5
#define LOCOMO_DEVID_SPI 6
struct locomo_dev {
struct device dev;
unsigned int devid;
unsigned int irq[1];
void *mapbase;
unsigned long length;
u64 dma_mask;
};
#define LOCOMO_DEV(_d) container_of((_d), struct locomo_dev, dev)
#define locomo_get_drvdata(d) dev_get_drvdata(&(d)->dev)
#define locomo_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
struct locomo_driver {
struct device_driver drv;
unsigned int devid;
int (*probe)(struct locomo_dev *);
int (*remove)(struct locomo_dev *);
int (*suspend)(struct locomo_dev *, pm_message_t);
int (*resume)(struct locomo_dev *);
};
#define LOCOMO_DRV(_d) container_of((_d), struct locomo_driver, drv)
#define LOCOMO_DRIVER_NAME(_ldev) ((_ldev)->dev.driver->name)
void locomo_lcd_power(struct locomo_dev *, int, unsigned int);
int locomo_driver_register(struct locomo_driver *);
void locomo_driver_unregister(struct locomo_driver *);
/* GPIO control functions */
void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir);
int locomo_gpio_read_level(struct device *dev, unsigned int bits);
int locomo_gpio_read_output(struct device *dev, unsigned int bits);
void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set);
/* M62332 control function */
void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);
/* Frontlight control */
void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf);
#endif

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include/asm-arm/hardware/memc.h Normal file
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/*
* linux/include/asm-arm/hardware/memc.h
*
* Copyright (C) Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define VDMA_ALIGNMENT PAGE_SIZE
#define VDMA_XFERSIZE 16
#define VDMA_INIT 0
#define VDMA_START 1
#define VDMA_END 2
#ifndef __ASSEMBLY__
extern void memc_write(unsigned int reg, unsigned long val);
#define video_set_dma(start,end,offset) \
do { \
memc_write (VDMA_START, (start >> 2)); \
memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2); \
memc_write (VDMA_INIT, (offset >> 2)); \
} while (0)
#endif

186
include/asm-arm/hardware/pci_v3.h Normal file
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/*
* linux/include/asm-arm/hardware/pci_v3.h
*
* Internal header file PCI V3 chip
*
* Copyright (C) ARM Limited
* Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef ASM_ARM_HARDWARE_PCI_V3_H
#define ASM_ARM_HARDWARE_PCI_V3_H
/* -------------------------------------------------------------------------------
* V3 Local Bus to PCI Bridge definitions
* -------------------------------------------------------------------------------
* Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
* All V3 register names are prefaced by V3_ to avoid clashing with any other
* PCI definitions. Their names match the user's manual.
*
* I'm assuming that I20 is disabled.
*
*/
#define V3_PCI_VENDOR 0x00000000
#define V3_PCI_DEVICE 0x00000002
#define V3_PCI_CMD 0x00000004
#define V3_PCI_STAT 0x00000006
#define V3_PCI_CC_REV 0x00000008
#define V3_PCI_HDR_CFG 0x0000000C
#define V3_PCI_IO_BASE 0x00000010
#define V3_PCI_BASE0 0x00000014
#define V3_PCI_BASE1 0x00000018
#define V3_PCI_SUB_VENDOR 0x0000002C
#define V3_PCI_SUB_ID 0x0000002E
#define V3_PCI_ROM 0x00000030
#define V3_PCI_BPARAM 0x0000003C
#define V3_PCI_MAP0 0x00000040
#define V3_PCI_MAP1 0x00000044
#define V3_PCI_INT_STAT 0x00000048
#define V3_PCI_INT_CFG 0x0000004C
#define V3_LB_BASE0 0x00000054
#define V3_LB_BASE1 0x00000058
#define V3_LB_MAP0 0x0000005E
#define V3_LB_MAP1 0x00000062
#define V3_LB_BASE2 0x00000064
#define V3_LB_MAP2 0x00000066
#define V3_LB_SIZE 0x00000068
#define V3_LB_IO_BASE 0x0000006E
#define V3_FIFO_CFG 0x00000070
#define V3_FIFO_PRIORITY 0x00000072
#define V3_FIFO_STAT 0x00000074
#define V3_LB_ISTAT 0x00000076
#define V3_LB_IMASK 0x00000077
#define V3_SYSTEM 0x00000078
#define V3_LB_CFG 0x0000007A
#define V3_PCI_CFG 0x0000007C
#define V3_DMA_PCI_ADR0 0x00000080
#define V3_DMA_PCI_ADR1 0x00000090
#define V3_DMA_LOCAL_ADR0 0x00000084
#define V3_DMA_LOCAL_ADR1 0x00000094
#define V3_DMA_LENGTH0 0x00000088
#define V3_DMA_LENGTH1 0x00000098
#define V3_DMA_CSR0 0x0000008B
#define V3_DMA_CSR1 0x0000009B
#define V3_DMA_CTLB_ADR0 0x0000008C
#define V3_DMA_CTLB_ADR1 0x0000009C
#define V3_DMA_DELAY 0x000000E0
#define V3_MAIL_DATA 0x000000C0
#define V3_PCI_MAIL_IEWR 0x000000D0
#define V3_PCI_MAIL_IERD 0x000000D2
#define V3_LB_MAIL_IEWR 0x000000D4
#define V3_LB_MAIL_IERD 0x000000D6
#define V3_MAIL_WR_STAT 0x000000D8
#define V3_MAIL_RD_STAT 0x000000DA
#define V3_QBA_MAP 0x000000DC
/* PCI COMMAND REGISTER bits
*/
#define V3_COMMAND_M_FBB_EN (1 << 9)
#define V3_COMMAND_M_SERR_EN (1 << 8)
#define V3_COMMAND_M_PAR_EN (1 << 6)
#define V3_COMMAND_M_MASTER_EN (1 << 2)
#define V3_COMMAND_M_MEM_EN (1 << 1)
#define V3_COMMAND_M_IO_EN (1 << 0)
/* SYSTEM REGISTER bits
*/
#define V3_SYSTEM_M_RST_OUT (1 << 15)
#define V3_SYSTEM_M_LOCK (1 << 14)
/* PCI_CFG bits
*/
#define V3_PCI_CFG_M_I2O_EN (1 << 15)
#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
#define V3_PCI_CFG_M_IO_DIS (1 << 13)
#define V3_PCI_CFG_M_EN3V (1 << 12)
#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
/* PCI_BASE register bits (PCI -> Local Bus)
*/
#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
#define V3_PCI_BASE_M_PREFETCH (1 << 3)
#define V3_PCI_BASE_M_TYPE (3 << 1)
#define V3_PCI_BASE_M_IO (1 << 0)
/* PCI MAP register bits (PCI -> Local bus)
*/
#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
#define V3_PCI_MAP_M_SWAP (3 << 8)
#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
#define V3_PCI_MAP_M_REG_EN (1 << 1)
#define V3_PCI_MAP_M_ENABLE (1 << 0)
/*
* LB_BASE0,1 register bits (Local bus -> PCI)
*/
#define V3_LB_BASE_ADR_BASE 0xfff00000
#define V3_LB_BASE_SWAP (3 << 8)
#define V3_LB_BASE_ADR_SIZE (15 << 4)
#define V3_LB_BASE_PREFETCH (1 << 3)
#define V3_LB_BASE_ENABLE (1 << 0)
#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
/*
* LB_MAP0,1 register bits (Local bus -> PCI)
*/
#define V3_LB_MAP_MAP_ADR 0xfff0
#define V3_LB_MAP_TYPE (7 << 1)
#define V3_LB_MAP_AD_LOW_EN (1 << 0)
#define V3_LB_MAP_TYPE_IACK (0 << 1)
#define V3_LB_MAP_TYPE_IO (1 << 1)
#define V3_LB_MAP_TYPE_MEM (3 << 1)
#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
/*
* LB_BASE2 register bits (Local bus -> PCI IO)
*/
#define V3_LB_BASE2_ADR_BASE 0xff00
#define V3_LB_BASE2_SWAP (3 << 6)
#define V3_LB_BASE2_ENABLE (1 << 0)
#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
/*
* LB_MAP2 register bits (Local bus -> PCI IO)
*/
#define V3_LB_MAP2_MAP_ADR 0xff00
#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
#endif

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include/asm-arm/hardware/sa1111.h Normal file
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/*
* linux/include/asm-arm/hardware/sa1111.h
*
* Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
*
* This file contains definitions for the SA-1111 Companion Chip.
* (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
*
* Macro that calculates real address for registers in the SA-1111
*/
#ifndef _ASM_ARCH_SA1111
#define _ASM_ARCH_SA1111
#include <asm/arch/bitfield.h>
/*
* The SA1111 is always located at virtual 0xf4000000, and is always
* "native" endian.
*/
#define SA1111_VBASE 0xf4000000
/* Don't use these! */
#define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE)
#define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE)
#ifndef __ASSEMBLY__
#define _SA1111(x) ((x) + sa1111->resource.start)
#endif
#define sa1111_writel(val,addr) __raw_writel(val, addr)
#define sa1111_readl(addr) __raw_readl(addr)
/*
* 26 bits of the SA-1110 address bus are available to the SA-1111.
* Use these when feeding target addresses to the DMA engines.
*/
#define SA1111_ADDR_WIDTH (26)
#define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1)
#define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK)
/*
* Don't ask the (SAC) DMA engines to move less than this amount.
*/
#define SA1111_SAC_DMA_MIN_XFER (0x800)
/*
* System Bus Interface (SBI)
*
* Registers
* SKCR Control Register
* SMCR Shared Memory Controller Register
* SKID ID Register
*/
#define SA1111_SKCR 0x0000
#define SA1111_SMCR 0x0004
#define SA1111_SKID 0x0008
#define SKCR_PLL_BYPASS (1<<0)
#define SKCR_RCLKEN (1<<1)
#define SKCR_SLEEP (1<<2)
#define SKCR_DOZE (1<<3)
#define SKCR_VCO_OFF (1<<4)
#define SKCR_SCANTSTEN (1<<5)
#define SKCR_CLKTSTEN (1<<6)
#define SKCR_RDYEN (1<<7)
#define SKCR_SELAC (1<<8)
#define SKCR_OPPC (1<<9)
#define SKCR_PLLTSTEN (1<<10)
#define SKCR_USBIOTSTEN (1<<11)
/*
* Don't believe the specs! Take them, throw them outside. Leave them
* there for a week. Spit on them. Walk on them. Stamp on them.
* Pour gasoline over them and finally burn them. Now think about coding.
* - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
* - The Feb 2001 errata (278260-010) says that the previous errata
* (278260-009) is wrong, and its bit actually 12, fixed in spec
* 278242-003.
* - The SA1111 manual (278242) says bit 12, but 0 to enable.
* - Reality is bit 13, 1 to enable.
* -- rmk
*/
#define SKCR_OE_EN (1<<13)
#define SMCR_DTIM (1<<0)
#define SMCR_MBGE (1<<1)
#define SMCR_DRAC_0 (1<<2)
#define SMCR_DRAC_1 (1<<3)
#define SMCR_DRAC_2 (1<<4)
#define SMCR_DRAC Fld(3, 2)
#define SMCR_CLAT (1<<5)
#define SKID_SIREV_MASK (0x000000f0)
#define SKID_MTREV_MASK (0x0000000f)
#define SKID_ID_MASK (0xffffff00)
#define SKID_SA1111_ID (0x690cc200)
/*
* System Controller
*
* Registers
* SKPCR Power Control Register
* SKCDR Clock Divider Register
* SKAUD Audio Clock Divider Register
* SKPMC PS/2 Mouse Clock Divider Register
* SKPTC PS/2 Track Pad Clock Divider Register
* SKPEN0 PWM0 Enable Register
* SKPWM0 PWM0 Clock Register
* SKPEN1 PWM1 Enable Register
* SKPWM1 PWM1 Clock Register
*/
#define SA1111_SKPCR 0x0200
#define SA1111_SKCDR 0x0204
#define SA1111_SKAUD 0x0208
#define SA1111_SKPMC 0x020c
#define SA1111_SKPTC 0x0210
#define SA1111_SKPEN0 0x0214
#define SA1111_SKPWM0 0x0218
#define SA1111_SKPEN1 0x021c
#define SA1111_SKPWM1 0x0220
#define SKPCR_UCLKEN (1<<0)
#define SKPCR_ACCLKEN (1<<1)
#define SKPCR_I2SCLKEN (1<<2)
#define SKPCR_L3CLKEN (1<<3)
#define SKPCR_SCLKEN (1<<4)
#define SKPCR_PMCLKEN (1<<5)
#define SKPCR_PTCLKEN (1<<6)
#define SKPCR_DCLKEN (1<<7)
#define SKPCR_PWMCLKEN (1<<8)
/*
* USB Host controller
*/
#define SA1111_USB 0x0400
/*
* Offsets from SA1111_USB_BASE
*/
#define SA1111_USB_STATUS 0x0118
#define SA1111_USB_RESET 0x011c
#define SA1111_USB_IRQTEST 0x0120
#define USB_RESET_FORCEIFRESET (1 << 0)
#define USB_RESET_FORCEHCRESET (1 << 1)
#define USB_RESET_CLKGENRESET (1 << 2)
#define USB_RESET_SIMSCALEDOWN (1 << 3)
#define USB_RESET_USBINTTEST (1 << 4)
#define USB_RESET_SLEEPSTBYEN (1 << 5)
#define USB_RESET_PWRSENSELOW (1 << 6)
#define USB_RESET_PWRCTRLLOW (1 << 7)
#define USB_STATUS_IRQHCIRMTWKUP (1 << 7)
#define USB_STATUS_IRQHCIBUFFACC (1 << 8)
#define USB_STATUS_NIRQHCIM (1 << 9)
#define USB_STATUS_NHCIMFCLR (1 << 10)
#define USB_STATUS_USBPWRSENSE (1 << 11)
/*
* Serial Audio Controller
*
* Registers
* SACR0 Serial Audio Common Control Register
* SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
* SACR2 Serial Audio AC-link Control Register
* SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
* SASR1 Serial Audio AC-link Interface & FIFO Status Register
* SASCR Serial Audio Status Clear Register
* L3_CAR L3 Control Bus Address Register
* L3_CDR L3 Control Bus Data Register
* ACCAR AC-link Command Address Register
* ACCDR AC-link Command Data Register
* ACSAR AC-link Status Address Register
* ACSDR AC-link Status Data Register
* SADTCS Serial Audio DMA Transmit Control/Status Register
* SADTSA Serial Audio DMA Transmit Buffer Start Address A
* SADTCA Serial Audio DMA Transmit Buffer Count Register A
* SADTSB Serial Audio DMA Transmit Buffer Start Address B
* SADTCB Serial Audio DMA Transmit Buffer Count Register B
* SADRCS Serial Audio DMA Receive Control/Status Register
* SADRSA Serial Audio DMA Receive Buffer Start Address A
* SADRCA Serial Audio DMA Receive Buffer Count Register A
* SADRSB Serial Audio DMA Receive Buffer Start Address B
* SADRCB Serial Audio DMA Receive Buffer Count Register B
* SAITR Serial Audio Interrupt Test Register
* SADR Serial Audio Data Register (16 x 32-bit)
*/
#define SA1111_SERAUDIO 0x0600
/*
* These are offsets from the above base.
*/
#define SA1111_SACR0 0x00
#define SA1111_SACR1 0x04
#define SA1111_SACR2 0x08
#define SA1111_SASR0 0x0c
#define SA1111_SASR1 0x10
#define SA1111_SASCR 0x18
#define SA1111_L3_CAR 0x1c
#define SA1111_L3_CDR 0x20
#define SA1111_ACCAR 0x24
#define SA1111_ACCDR 0x28
#define SA1111_ACSAR 0x2c
#define SA1111_ACSDR 0x30
#define SA1111_SADTCS 0x34
#define SA1111_SADTSA 0x38
#define SA1111_SADTCA 0x3c
#define SA1111_SADTSB 0x40
#define SA1111_SADTCB 0x44
#define SA1111_SADRCS 0x48
#define SA1111_SADRSA 0x4c
#define SA1111_SADRCA 0x50
#define SA1111_SADRSB 0x54
#define SA1111_SADRCB 0x58
#define SA1111_SAITR 0x5c
#define SA1111_SADR 0x80
#ifndef CONFIG_ARCH_PXA
#define SACR0_ENB (1<<0)
#define SACR0_BCKD (1<<2)
#define SACR0_RST (1<<3)
#define SACR1_AMSL (1<<0)
#define SACR1_L3EN (1<<1)
#define SACR1_L3MB (1<<2)
#define SACR1_DREC (1<<3)
#define SACR1_DRPL (1<<4)
#define SACR1_ENLBF (1<<5)
#define SACR2_TS3V (1<<0)
#define SACR2_TS4V (1<<1)
#define SACR2_WKUP (1<<2)
#define SACR2_DREC (1<<3)
#define SACR2_DRPL (1<<4)
#define SACR2_ENLBF (1<<5)
#define SACR2_RESET (1<<6)
#define SASR0_TNF (1<<0)
#define SASR0_RNE (1<<1)
#define SASR0_BSY (1<<2)
#define SASR0_TFS (1<<3)
#define SASR0_RFS (1<<4)
#define SASR0_TUR (1<<5)
#define SASR0_ROR (1<<6)
#define SASR0_L3WD (1<<16)
#define SASR0_L3RD (1<<17)
#define SASR1_TNF (1<<0)
#define SASR1_RNE (1<<1)
#define SASR1_BSY (1<<2)
#define SASR1_TFS (1<<3)
#define SASR1_RFS (1<<4)
#define SASR1_TUR (1<<5)
#define SASR1_ROR (1<<6)
#define SASR1_CADT (1<<16)
#define SASR1_SADR (1<<17)
#define SASR1_RSTO (1<<18)
#define SASR1_CLPM (1<<19)
#define SASR1_CRDY (1<<20)
#define SASR1_RS3V (1<<21)
#define SASR1_RS4V (1<<22)
#define SASCR_TUR (1<<5)
#define SASCR_ROR (1<<6)
#define SASCR_DTS (1<<16)
#define SASCR_RDD (1<<17)
#define SASCR_STO (1<<18)
#define SADTCS_TDEN (1<<0)
#define SADTCS_TDIE (1<<1)
#define SADTCS_TDBDA (1<<3)
#define SADTCS_TDSTA (1<<4)
#define SADTCS_TDBDB (1<<5)
#define SADTCS_TDSTB (1<<6)
#define SADTCS_TBIU (1<<7)
#define SADRCS_RDEN (1<<0)
#define SADRCS_RDIE (1<<1)
#define SADRCS_RDBDA (1<<3)
#define SADRCS_RDSTA (1<<4)
#define SADRCS_RDBDB (1<<5)
#define SADRCS_RDSTB (1<<6)
#define SADRCS_RBIU (1<<7)
#define SAD_CS_DEN (1<<0)
#define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */
#define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */
#define SAD_CS_DSTA (1<<4)
#define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */
#define SAD_CS_DSTB (1<<6)
#define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */
#define SAITR_TFS (1<<0)
#define SAITR_RFS (1<<1)
#define SAITR_TUR (1<<2)
#define SAITR_ROR (1<<3)
#define SAITR_CADT (1<<4)
#define SAITR_SADR (1<<5)
#define SAITR_RSTO (1<<6)
#define SAITR_TDBDA (1<<8)
#define SAITR_TDBDB (1<<9)
#define SAITR_RDBDA (1<<10)
#define SAITR_RDBDB (1<<11)
#endif /* !CONFIG_ARCH_PXA */
/*
* General-Purpose I/O Interface
*
* Registers
* PA_DDR GPIO Block A Data Direction
* PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
* PA_SDR GPIO Block A Sleep Direction
* PA_SSR GPIO Block A Sleep State
* PB_DDR GPIO Block B Data Direction
* PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
* PB_SDR GPIO Block B Sleep Direction
* PB_SSR GPIO Block B Sleep State
* PC_DDR GPIO Block C Data Direction
* PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
* PC_SDR GPIO Block C Sleep Direction
* PC_SSR GPIO Block C Sleep State
*/
#define _PA_DDR _SA1111( 0x1000 )
#define _PA_DRR _SA1111( 0x1004 )
#define _PA_DWR _SA1111( 0x1004 )
#define _PA_SDR _SA1111( 0x1008 )
#define _PA_SSR _SA1111( 0x100c )
#define _PB_DDR _SA1111( 0x1010 )
#define _PB_DRR _SA1111( 0x1014 )
#define _PB_DWR _SA1111( 0x1014 )
#define _PB_SDR _SA1111( 0x1018 )
#define _PB_SSR _SA1111( 0x101c )
#define _PC_DDR _SA1111( 0x1020 )
#define _PC_DRR _SA1111( 0x1024 )
#define _PC_DWR _SA1111( 0x1024 )
#define _PC_SDR _SA1111( 0x1028 )
#define _PC_SSR _SA1111( 0x102c )
#define SA1111_GPIO 0x1000
#define SA1111_GPIO_PADDR (0x000)
#define SA1111_GPIO_PADRR (0x004)
#define SA1111_GPIO_PADWR (0x004)
#define SA1111_GPIO_PASDR (0x008)
#define SA1111_GPIO_PASSR (0x00c)
#define SA1111_GPIO_PBDDR (0x010)
#define SA1111_GPIO_PBDRR (0x014)
#define SA1111_GPIO_PBDWR (0x014)
#define SA1111_GPIO_PBSDR (0x018)
#define SA1111_GPIO_PBSSR (0x01c)
#define SA1111_GPIO_PCDDR (0x020)
#define SA1111_GPIO_PCDRR (0x024)
#define SA1111_GPIO_PCDWR (0x024)
#define SA1111_GPIO_PCSDR (0x028)
#define SA1111_GPIO_PCSSR (0x02c)
#define GPIO_A0 (1 << 0)
#define GPIO_A1 (1 << 1)
#define GPIO_A2 (1 << 2)
#define GPIO_A3 (1 << 3)
#define GPIO_B0 (1 << 8)
#define GPIO_B1 (1 << 9)
#define GPIO_B2 (1 << 10)
#define GPIO_B3 (1 << 11)
#define GPIO_B4 (1 << 12)
#define GPIO_B5 (1 << 13)
#define GPIO_B6 (1 << 14)
#define GPIO_B7 (1 << 15)
#define GPIO_C0 (1 << 16)
#define GPIO_C1 (1 << 17)
#define GPIO_C2 (1 << 18)
#define GPIO_C3 (1 << 19)
#define GPIO_C4 (1 << 20)
#define GPIO_C5 (1 << 21)
#define GPIO_C6 (1 << 22)
#define GPIO_C7 (1 << 23)
/*
* Interrupt Controller
*
* Registers
* INTTEST0 Test register 0
* INTTEST1 Test register 1
* INTEN0 Interrupt Enable register 0
* INTEN1 Interrupt Enable register 1
* INTPOL0 Interrupt Polarity selection 0
* INTPOL1 Interrupt Polarity selection 1
* INTTSTSEL Interrupt source selection
* INTSTATCLR0 Interrupt Status/Clear 0
* INTSTATCLR1 Interrupt Status/Clear 1
* INTSET0 Interrupt source set 0
* INTSET1 Interrupt source set 1
* WAKE_EN0 Wake-up source enable 0
* WAKE_EN1 Wake-up source enable 1
* WAKE_POL0 Wake-up polarity selection 0
* WAKE_POL1 Wake-up polarity selection 1
*/
#define SA1111_INTC 0x1600
/*
* These are offsets from the above base.
*/
#define SA1111_INTTEST0 0x0000
#define SA1111_INTTEST1 0x0004
#define SA1111_INTEN0 0x0008
#define SA1111_INTEN1 0x000c
#define SA1111_INTPOL0 0x0010
#define SA1111_INTPOL1 0x0014
#define SA1111_INTTSTSEL 0x0018
#define SA1111_INTSTATCLR0 0x001c
#define SA1111_INTSTATCLR1 0x0020
#define SA1111_INTSET0 0x0024
#define SA1111_INTSET1 0x0028
#define SA1111_WAKEEN0 0x002c
#define SA1111_WAKEEN1 0x0030
#define SA1111_WAKEPOL0 0x0034
#define SA1111_WAKEPOL1 0x0038
/*
* PS/2 Trackpad and Mouse Interfaces
*
* Registers
* PS2CR Control Register
* PS2STAT Status Register
* PS2DATA Transmit/Receive Data register
* PS2CLKDIV Clock Division Register
* PS2PRECNT Clock Precount Register
* PS2TEST1 Test register 1
* PS2TEST2 Test register 2
* PS2TEST3 Test register 3
* PS2TEST4 Test register 4
*/
#define SA1111_KBD 0x0a00
#define SA1111_MSE 0x0c00
/*
* These are offsets from the above bases.
*/
#define SA1111_PS2CR 0x0000
#define SA1111_PS2STAT 0x0004
#define SA1111_PS2DATA 0x0008
#define SA1111_PS2CLKDIV 0x000c
#define SA1111_PS2PRECNT 0x0010
#define PS2CR_ENA 0x08
#define PS2CR_FKD 0x02
#define PS2CR_FKC 0x01
#define PS2STAT_STP 0x0100
#define PS2STAT_TXE 0x0080
#define PS2STAT_TXB 0x0040
#define PS2STAT_RXF 0x0020
#define PS2STAT_RXB 0x0010
#define PS2STAT_ENA 0x0008
#define PS2STAT_RXP 0x0004
#define PS2STAT_KBD 0x0002
#define PS2STAT_KBC 0x0001
/*
* PCMCIA Interface
*
* Registers
* PCSR Status Register
* PCCR Control Register
* PCSSR Sleep State Register
*/
#define SA1111_PCMCIA 0x1600
/*
* These are offsets from the above base.
*/
#define SA1111_PCCR 0x0000
#define SA1111_PCSSR 0x0004
#define SA1111_PCSR 0x0008
#define PCSR_S0_READY (1<<0)
#define PCSR_S1_READY (1<<1)
#define PCSR_S0_DETECT (1<<2)
#define PCSR_S1_DETECT (1<<3)
#define PCSR_S0_VS1 (1<<4)
#define PCSR_S0_VS2 (1<<5)
#define PCSR_S1_VS1 (1<<6)
#define PCSR_S1_VS2 (1<<7)
#define PCSR_S0_WP (1<<8)
#define PCSR_S1_WP (1<<9)
#define PCSR_S0_BVD1 (1<<10)
#define PCSR_S0_BVD2 (1<<11)
#define PCSR_S1_BVD1 (1<<12)
#define PCSR_S1_BVD2 (1<<13)
#define PCCR_S0_RST (1<<0)
#define PCCR_S1_RST (1<<1)
#define PCCR_S0_FLT (1<<2)
#define PCCR_S1_FLT (1<<3)
#define PCCR_S0_PWAITEN (1<<4)
#define PCCR_S1_PWAITEN (1<<5)
#define PCCR_S0_PSE (1<<6)
#define PCCR_S1_PSE (1<<7)
#define PCSSR_S0_SLEEP (1<<0)
#define PCSSR_S1_SLEEP (1<<1)
extern struct bus_type sa1111_bus_type;
#define SA1111_DEVID_SBI 0
#define SA1111_DEVID_SK 1
#define SA1111_DEVID_USB 2
#define SA1111_DEVID_SAC 3
#define SA1111_DEVID_SSP 4
#define SA1111_DEVID_PS2 5
#define SA1111_DEVID_GPIO 6
#define SA1111_DEVID_INT 7
#define SA1111_DEVID_PCMCIA 8
struct sa1111_dev {
struct device dev;
unsigned int devid;
struct resource res;
void __iomem *mapbase;
unsigned int skpcr_mask;
unsigned int irq[6];
u64 dma_mask;
};
#define SA1111_DEV(_d) container_of((_d), struct sa1111_dev, dev)
#define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev)
#define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
struct sa1111_driver {
struct device_driver drv;
unsigned int devid;
int (*probe)(struct sa1111_dev *);
int (*remove)(struct sa1111_dev *);
int (*suspend)(struct sa1111_dev *, pm_message_t);
int (*resume)(struct sa1111_dev *);
};
#define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv)
#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
/*
* These frob the SKPCR register.
*/
void sa1111_enable_device(struct sa1111_dev *);
void sa1111_disable_device(struct sa1111_dev *);
unsigned int sa1111_pll_clock(struct sa1111_dev *);
#define SA1111_AUDIO_ACLINK 0
#define SA1111_AUDIO_I2S 1
void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
int sa1111_get_audio_rate(struct sa1111_dev *sadev);
int sa1111_check_dma_bug(dma_addr_t addr);
int sa1111_driver_register(struct sa1111_driver *);
void sa1111_driver_unregister(struct sa1111_driver *);
void sa1111_set_io_dir(struct sa1111_dev *sadev, unsigned int bits, unsigned int dir, unsigned int sleep_dir);
void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
#endif /* _ASM_ARCH_SA1111 */

68
include/asm-arm/hardware/scoop.h Normal file
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/*
* Definitions for the SCOOP interface found on various Sharp PDAs
*
* Copyright (c) 2004 Richard Purdie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#define SCOOP_MCR 0x00
#define SCOOP_CDR 0x04
#define SCOOP_CSR 0x08
#define SCOOP_CPR 0x0C
#define SCOOP_CCR 0x10
#define SCOOP_IRR 0x14
#define SCOOP_IRM 0x14
#define SCOOP_IMR 0x18
#define SCOOP_ISR 0x1C
#define SCOOP_GPCR 0x20
#define SCOOP_GPWR 0x24
#define SCOOP_GPRR 0x28
#define SCOOP_GPCR_PA22 ( 1 << 12 )
#define SCOOP_GPCR_PA21 ( 1 << 11 )
#define SCOOP_GPCR_PA20 ( 1 << 10 )
#define SCOOP_GPCR_PA19 ( 1 << 9 )
#define SCOOP_GPCR_PA18 ( 1 << 8 )
#define SCOOP_GPCR_PA17 ( 1 << 7 )
#define SCOOP_GPCR_PA16 ( 1 << 6 )
#define SCOOP_GPCR_PA15 ( 1 << 5 )
#define SCOOP_GPCR_PA14 ( 1 << 4 )
#define SCOOP_GPCR_PA13 ( 1 << 3 )
#define SCOOP_GPCR_PA12 ( 1 << 2 )
#define SCOOP_GPCR_PA11 ( 1 << 1 )
struct scoop_config {
unsigned short io_out;
unsigned short io_dir;
unsigned short suspend_clr;
unsigned short suspend_set;
};
/* Structure for linking scoop devices to PCMCIA sockets */
struct scoop_pcmcia_dev {
struct device *dev; /* Pointer to this socket's scoop device */
int irq; /* irq for socket */
int cd_irq;
const char *cd_irq_str;
unsigned char keep_vs;
unsigned char keep_rd;
};
struct scoop_pcmcia_config {
struct scoop_pcmcia_dev *devs;
int num_devs;
void (*pcmcia_init)(void);
void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr);
};
extern struct scoop_pcmcia_config *platform_scoop_config;
void reset_scoop(struct device *dev);
unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit);
unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);

106
include/asm-arm/hardware/sharpsl_pm.h Normal file
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/*
* SharpSL Battery/PM Driver
*
* Copyright (c) 2004-2005 Richard Purdie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/interrupt.h>
struct sharpsl_charger_machinfo {
void (*init)(void);
void (*exit)(void);
int gpio_acin;
int gpio_batfull;
int batfull_irq;
int gpio_batlock;
int gpio_fatal;
void (*discharge)(int);
void (*discharge1)(int);
void (*charge)(int);
void (*measure_temp)(int);
void (*presuspend)(void);
void (*postsuspend)(void);
void (*earlyresume)(void);
unsigned long (*read_devdata)(int);
#define SHARPSL_BATT_VOLT 1
#define SHARPSL_BATT_TEMP 2
#define SHARPSL_ACIN_VOLT 3
#define SHARPSL_STATUS_ACIN 4
#define SHARPSL_STATUS_LOCK 5
#define SHARPSL_STATUS_CHRGFULL 6
#define SHARPSL_STATUS_FATAL 7
unsigned long (*charger_wakeup)(void);
int (*should_wakeup)(unsigned int resume_on_alarm);
void (*backlight_limit)(int);
int (*backlight_get_status) (void);
int charge_on_volt;
int charge_on_temp;
int charge_acin_high;
int charge_acin_low;
int fatal_acin_volt;
int fatal_noacin_volt;
int bat_levels;
struct battery_thresh *bat_levels_noac;
struct battery_thresh *bat_levels_acin;
struct battery_thresh *bat_levels_noac_bl;
struct battery_thresh *bat_levels_acin_bl;
int status_high_acin;
int status_low_acin;
int status_high_noac;
int status_low_noac;
};
struct battery_thresh {
int voltage;
int percentage;
};
struct battery_stat {
int ac_status; /* APM AC Present/Not Present */
int mainbat_status; /* APM Main Battery Status */
int mainbat_percent; /* Main Battery Percentage Charge */
int mainbat_voltage; /* Main Battery Voltage */
};
struct sharpsl_pm_status {
struct device *dev;
struct timer_list ac_timer;
struct timer_list chrg_full_timer;
int charge_mode;
#define CHRG_ERROR (-1)
#define CHRG_OFF (0)
#define CHRG_ON (1)
#define CHRG_DONE (2)
unsigned int flags;
#define SHARPSL_SUSPENDED (1 << 0) /* Device is Suspended */
#define SHARPSL_ALARM_ACTIVE (1 << 1) /* Alarm is for charging event (not user) */
#define SHARPSL_BL_LIMIT (1 << 2) /* Backlight Intensity Limited */
#define SHARPSL_APM_QUEUED (1 << 3) /* APM Event Queued */
#define SHARPSL_DO_OFFLINE_CHRG (1 << 4) /* Trigger the offline charger */
int full_count;
unsigned long charge_start_time;
struct sharpsl_charger_machinfo *machinfo;
struct battery_stat battstat;
};
extern struct sharpsl_pm_status sharpsl_pm;
#define SHARPSL_LED_ERROR 2
#define SHARPSL_LED_ON 1
#define SHARPSL_LED_OFF 0
void sharpsl_battery_kick(void);
void sharpsl_pm_led(int val);
irqreturn_t sharpsl_ac_isr(int irq, void *dev_id);
irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id);
irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id);

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include/asm-arm/hardware/ssp.h Normal file
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/*
* ssp.h
*
* Copyright (C) 2003 Russell King, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef SSP_H
#define SSP_H
struct ssp_state {
unsigned int cr0;
unsigned int cr1;
};
int ssp_write_word(u16 data);
int ssp_read_word(u16 *data);
int ssp_flush(void);
void ssp_enable(void);
void ssp_disable(void);
void ssp_save_state(struct ssp_state *ssp);
void ssp_restore_state(struct ssp_state *ssp);
int ssp_init(void);
void ssp_exit(void);
#endif

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include/asm-arm/hardware/uengine.h Normal file
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/*
* Generic library functions for the microengines found on the Intel
* IXP2000 series of network processors.
*
* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
* Dedicated to Marija Kulikova.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of the
* License, or (at your option) any later version.
*/
#ifndef __IXP2000_UENGINE_H
#define __IXP2000_UENGINE_H
extern u32 ixp2000_uengine_mask;
struct ixp2000_uengine_code
{
u32 cpu_model_bitmask;
u8 cpu_min_revision;
u8 cpu_max_revision;
u32 uengine_parameters;
struct ixp2000_reg_value {
int reg;
u32 value;
} *initial_reg_values;
int num_insns;
u8 *insns;
};
u32 ixp2000_uengine_csr_read(int uengine, int offset);
void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
void ixp2000_uengine_reset(u32 uengine_mask);
void ixp2000_uengine_set_mode(int uengine, u32 mode);
void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
void ixp2000_uengine_init_context(int uengine, int context, int pc);
void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
#define IXP2000_UENGINE_8_CONTEXTS 0x00000000
#define IXP2000_UENGINE_4_CONTEXTS 0x80000000
#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000
#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000
#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000
#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000
#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000
#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000
#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000
#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000
#endif

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include/asm-arm/hardware/vic.h Normal file
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/*
* linux/include/asm-arm/hardware/vic.h
*
* Copyright (c) ARM Limited 2003. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_HARDWARE_VIC_H
#define __ASM_ARM_HARDWARE_VIC_H
#define VIC_IRQ_STATUS 0x00
#define VIC_FIQ_STATUS 0x04
#define VIC_RAW_STATUS 0x08
#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
#define VIC_INT_ENABLE_CLEAR 0x14
#define VIC_INT_SOFT 0x18
#define VIC_INT_SOFT_CLEAR 0x1c
#define VIC_PROTECT 0x20
#define VIC_VECT_ADDR 0x30
#define VIC_DEF_VECT_ADDR 0x34
#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
#define VIC_ITCR 0x300 /* VIC test control register */
#define VIC_VECT_CNTL_ENABLE (1 << 5)
#ifndef __ASSEMBLY__
void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
#endif
#endif