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Commit for backup purpose

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This commit is contained in:
mlt
2010-06-28 17:51:53 +00:00
committed by Godzil
parent 71062896b6
commit e3c7c1b8b5
17 changed files with 1809 additions and 261 deletions
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2
include/asm-arm/arch-s3c2410/hardware.h
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@@ -119,7 +119,7 @@ extern unsigned int s3c_gpio_getpin(unsigned int pin);
* s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
*/
extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);

84
include/asm-arm/arch-s3c2410/regs-gpio.h
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@@ -27,8 +27,12 @@
#define S3C2410_GPIO_BANKH (32*7)
#define S3C2410_GPIO_BANKJ (32*13)
#define S3C2410_GPIO_BANKK (32*14)
#define S3C2410_GPIO_BANKL (32*15)
#ifdef CONFIG_CPU_S3C2400
#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x)
#define S3C24XX_MISCCR S3C2400_MISCCR
@@ -1104,6 +1108,86 @@
#define S3C2410_GPL14_SS1 (0x02 << 28)
/* Port L consists of14 SPI1/Misc pins
*
* GPLCON has 2 bits for each of the input pins on port L
* 00 = 0 input, 1 output,
*
* pull up works like all other ports.
*/
#define S3C2410_GPLCON S3C2410_GPIOREG(0xf0)
#define S3C2410_GPLDAT S3C2410_GPIOREG(0xf4)
#define S3C2410_GPLUP S3C2410_GPIOREG(0xf8)
#define S3C2450_GPLSEL S3C2410_GPIOREG(0xfC)
#define S3C2410_GPK0 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 0)
#define S3C2410_GPK0_INP (0x00 << 0)
#define S3C2410_GPK0_OUTP (0x01 << 0)
#define S3C2410_GPK1 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 1)
#define S3C2410_GPK1_INP (0x00 << 2)
#define S3C2410_GPK1_OUTP (0x01 << 2)
#define S3C2410_GPK2 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 2)
#define S3C2410_GPK2_INP (0x00 << 4)
#define S3C2410_GPK2_OUTP (0x01 << 4)
#define S3C2410_GPK3 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 3)
#define S3C2410_GPK3_INP (0x00 << 6)
#define S3C2410_GPK3_OUTP (0x01 << 6)
#define S3C2410_GPK4 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 4)
#define S3C2410_GPK4_INP (0x00 << 8)
#define S3C2410_GPK4_OUTP (0x01 << 8)
#define S3C2410_GPK5 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 5)
#define S3C2410_GPK5_INP (0x00 << 10)
#define S3C2410_GPK5_OUTP (0x01 << 10)
#define S3C2410_GPK6 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 6)
#define S3C2410_GPK6_INP (0x00 << 12)
#define S3C2410_GPK6_OUTP (0x01 << 12)
#define S3C2410_GPK7 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 7)
#define S3C2410_GPK7_INP (0x00 << 14)
#define S3C2410_GPK7_OUTP (0x01 << 14)
#define S3C2410_GPK8 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 8)
#define S3C2410_GPK8_INP (0x00 << 16)
#define S3C2410_GPK8_OUTP (0x01 << 16)
#define S3C2410_GPK9 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 9)
#define S3C2410_GPK9_INP (0x00 << 18)
#define S3C2410_GPK9_OUTP (0x01 << 18)
#define S3C2410_GPK10 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 10)
#define S3C2410_GPK10_INP (0x00 << 20)
#define S3C2410_GPK10_OUTP (0x01 << 20)
#define S3C2410_GPK11 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 11)
#define S3C2410_GPK11_INP (0x00 << 22)
#define S3C2410_GPK11_OUTP (0x01 << 22)
#define S3C2410_GPK12 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 12)
#define S3C2410_GPK12_INP (0x00 << 24)
#define S3C2410_GPK12_OUTP (0x01 << 24)
#define S3C2410_GPK13 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 13)
#define S3C2410_GPK13_INP (0x00 << 26)
#define S3C2410_GPK13_OUTP (0x01 << 26)
#define S3C2410_GPK14 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 14)
#define S3C2410_GPK14_INP (0x00 << 28)
#define S3C2410_GPK14_OUTP (0x01 << 28)
#define S3C2410_GPK15 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 15)
#define S3C2410_GPK15_INP (0x00 << 30)
#define S3C2410_GPK15_OUTP (0x01 << 30)
/*2009/7/17,Qisda Leo SJ Yang Set GPK3 for enabling SD_POWER{*/
#define S3C2416_GPLCON S3C2410_GPIOREG(0xF0)
#define S3C2416_GPLDAT S3C2410_GPIOREG(0xF4)