/* ------------------------------------------------------------------------- */ /* */ /* spi-s3c6400.h - definitions of s3c6400 specific spi interface */ /* */ /* ------------------------------------------------------------------------- */ /* Copyright (C) 2006 Samsung Electronics Co. ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* ------------------------------------------------------------------------- */ #ifndef _S3C2443_SPI_H #define _S3C2443_SPI_H #include #include #define S3C_DCON_HANDSHAKE (1<<31) #define S3C_DCON_SYNC_PCLK (0<<30) //#define SPI_CHANNEL 1 #if(SPI_CHANNEL==0) /* SPI CHANNEL 0 */ #define S3C_SPI_TX_DATA_REG 0x52000018 //SPI TX data #define S3C_SPI_RX_DATA_REG 0x5200001C //SPI RX data #else /* SPI CHANNEL 1 */ #define S3C_SPI_TX_DATA_REG 0x59000018 //SPI TX data #define S3C_SPI_RX_DATA_REG 0x5900001C //SPI RX data #endif /* DMA channel to be used for the SPI interface. */ #define S3C_SPI_DMA 0 /* DMA transfer unit (byte). */ #define S3C_DMA_XFER_BYTE 1 #define S3C_DMA_XFER_WORD 4 /* DMA configuration setup byte. */ #define S3C_DCON_SPI1 (S3C_DCON_HANDSHAKE | S3C_DCON_SYNC_PCLK) /* DMA hardware configuration mode (DISRCC register). */ #define S3C_SPI1_DMA_HWCFG 3 #define S3C_SPI_DMA_HWCFG 3 #define DMA_BUFFER_SIZE 1500 /* spi controller state */ int req_dma_flag = 1; enum s3c_spi_state { STATE_IDLE, STATE_XFER_TX, STATE_XFER_RX, STATE_STOP }; /* vivek, 2009-05-14 11:01 Notes: define clients for dma read and write channels*/ //static struct s3c2410_dma_client s3c2443spi_dma_client = { // .name = "s3c2443-spi-dma", //}; static struct s3c2410_dma_client s3c2443spi_dma_clientw = { .name = "s3c2443-spi-dmaw", }; static struct s3c2410_dma_client s3c2443spi_dma_clientr = { .name = "s3c2443-spi-dmar", }; struct s3c_spi { spinlock_t lock; struct semaphore sem; int nr; int dma; /* vivek, 2009-05-14 10:45 Notes: define dmar and dmaw for both write and read channels*/ int dmar; int dmaw; u_int subchannel;/* user fragment index */ dma_addr_t dmabuf_addr; struct spi_msg *msg; unsigned int msg_num; unsigned int msg_idx; unsigned int msg_ptr; unsigned int msg_rd_ptr; enum s3c_spi_state state; void __iomem *regs; struct clk *clk; struct device *dev; struct resource *irq; struct resource *ioarea; struct spi_dev spidev; /* GeorgeKuo: */ struct completion comp; }; typedef unsigned char int8; typedef signed short int16; typedef signed int int32; typedef unsigned char uchar; //typedef unsigned short ushort; //typedef unsigned int uint; //typedef unsigned long ulong; typedef unsigned char uint8; typedef unsigned short uint16; typedef unsigned int uint32; #define BCM_MEM_FILENAME_LEN 24 typedef void (*pktfree_cb_fn_t)(void *ctx, void *pkt, unsigned int status); typedef struct { bool pkttag; uint pktalloced; bool mmbus; pktfree_cb_fn_t tx_fn; void *tx_ctx; } osl_pubinfo_t; typedef struct bcm_mem_link { struct bcm_mem_link *prev; struct bcm_mem_link *next; uint size; int line; char file[BCM_MEM_FILENAME_LEN]; } bcm_mem_link_t; struct osl_info { osl_pubinfo_t pub; uint magic; void *pdev; uint malloced; uint failed; uint bustype; bcm_mem_link_t *dbgmem_list; }; /* Maximum number of I/O funcs */ #define SPI_MAX_IOFUNCS 4 #define NUM_PREV_TRANSACTIONS 16 /* Error statistics for gSPI */ struct spierrstats_t { uint32 dna; /* The requested data is not available. */ uint32 rdunderflow; /* FIFO underflow happened due to current (F2, F3) rd command */ uint32 wroverflow; /* FIFO underflow happened due to current (F1, F2, F3) wr command */ uint32 f2interrupt; /* OR of all F2 related intr status bits. */ uint32 f3interrupt; /* OR of all F3 related intr status bits. */ uint32 f2rxnotready; /* F2 FIFO is not ready to receive data (FIFO empty) */ uint32 f3rxnotready; /* F3 FIFO is not ready to receive data (FIFO empty) */ uint32 hostcmddataerr; /* Error in command or host data, detected by CRC/checksum * (optional) */ uint32 f2pktavailable; /* Packet is available in F2 TX FIFO */ uint32 f3pktavailable; /* Packet is available in F2 TX FIFO */ uint32 dstatus[NUM_PREV_TRANSACTIONS]; /* dstatus bits of last 16 gSPI transactions */ uint32 spicmd[NUM_PREV_TRANSACTIONS]; }; typedef struct osl_info osl_t; typedef void (*sdioh_cb_fn_t)(void *); struct sdioh_info { uint cfg_bar; /* pci cfg address for bar */ uint32 caps; /* cached value of capabilities reg */ void *bar0; /* BAR0 for PCI Device */ osl_t *osh; /* osh handler */ void *controller; /* Pointer to SPI Controller's private data struct */ uint lockcount; /* nest count of spi_lock() calls */ bool client_intr_enabled; /* interrupt connnected flag */ bool intr_handler_valid; /* client driver interrupt handler valid */ sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ void *intr_handler_arg; /* argument to call interrupt handler */ bool initialized; /* card initialized */ uint32 target_dev; /* Target device ID */ uint32 intmask; /* Current active interrupts */ void *sdos_info; /* Pointer to per-OS private data */ uint32 controller_type; /* Host controller type */ uint8 version; /* Host Controller Spec Compliance Version */ uint irq; /* Client irq */ uint32 intrcount; /* Client interrupts */ uint32 local_intrcount; /* Controller interrupts */ bool host_init_done; /* Controller initted */ bool card_init_done; /* Client SDIO interface initted */ bool polled_mode; /* polling for command completion */ bool sd_use_dma; /* DMA on CMD53 */ bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */ /* Must be on for sd_multiblock to be effective */ bool use_client_ints; /* If this is false, make sure to restore */ /* polling hack in wl_linux.c:wl_timer() */ int adapter_slot; /* Maybe dealing with multiple slots/controllers */ int sd_mode; /* SD1/SD4/SPI */ int client_block_size[SPI_MAX_IOFUNCS]; /* Blocksize */ uint32 data_xfer_count; /* Current transfer */ uint16 card_rca; /* Current Address */ uint8 num_funcs; /* Supported funcs on client */ uint32 card_dstatus; /* 32bit device status */ uint32 com_cis_ptr; uint32 func_cis_ptr[SPI_MAX_IOFUNCS]; void *dma_buf; ulong dma_phys; int r_cnt; /* rx count */ int t_cnt; /* tx_count */ uint32 wordlen; /* host processor 16/32bits */ uint32 prev_fun; uint32 chip; uint32 chiprev; bool resp_delay_all; bool dwordmode; struct spierrstats_t spierrstats; }; typedef struct sdioh_info sdioh_info_t; void spi_sendrecv(sdioh_info_t *sd, uint8 *msg_out, uint8 *msg_in, int msglen); void ClearSourcePenging(void); void ClearIntrPenging(void); void S3cEnableIntr(void); void S3cDisableIntr(void); #endif /* _S3C6400_SPI_H */