435 lines
11 KiB
C
435 lines
11 KiB
C
/* linux/arch/arm/mach-s3c2416/mach-smdk2416.c
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*
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* Copyright (c) 2007 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* Ryu Euiyoul <ryu.real@gmail.com>
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*
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* http://www.fluff.org/ben/smdk2443/
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*
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* Thanks to Samsung for the loan of an SMDK2416
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/setup.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <asm/arch/regs-serial.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-gpioj.h>
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#include <asm/arch/regs-lcd.h>
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#include <asm/arch/regs-mem.h>
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#include <asm/arch/idle.h>
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#include <asm/arch/fb.h>
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#include <asm/plat-s3c24xx/s3c2410.h>
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#include <asm/plat-s3c24xx/s3c2440.h>
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#include <asm/plat-s3c24xx/clock.h>
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#include <asm/plat-s3c24xx/devs.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#include <asm/plat-s3c24xx/common-smdk.h>
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#include <asm/arch/nand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <asm/arch/hsmmc.h>
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static struct map_desc smdk2416_iodesc[] __initdata = {
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IODESC_ENT(CS8900),
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};
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#define UCON S3C2410_UCON_DEFAULT | S3C2440_UCON_FCLK
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#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
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#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
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static struct s3c24xx_uart_clksrc smdk2416_serial_clocks[] = {
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[0] = {
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.name = "pclk",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 0,
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},
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[1] = {
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.name = "esysclk",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 0,
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}
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};
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static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = 0x3c5,
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.ulcon = 0x03,
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.ufcon = 0x51,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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/* Use PCLK */
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.ucon = 0x3c5,
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//.ucon = 0xfc5,
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.ulcon = 0x03,
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.ufcon = 0x51,
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#ifndef CONFIG_QISDA_BK060B00
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.clocks = smdk2416_serial_clocks,
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.clocks_size = ARRAY_SIZE(smdk2416_serial_clocks),
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#endif
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},
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/* IR port */
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = 0x3c5,
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// .ucon = 0xfc5,
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.ulcon = 0x03,
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// .ulcon = 0x43,
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.ufcon = 0x51,
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.clocks = smdk2416_serial_clocks,
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.clocks_size = ARRAY_SIZE(smdk2416_serial_clocks),
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}
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};
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static struct platform_device *smdk2416_devices[] __initdata = {
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&s3c_device_spi0,
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&s3c_device_spi1,
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&s3c_device_wdt,
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&s3c_device_i2c,
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&s3c_device_lcd,
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&s3c_device_rtc,
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&s3c_device_adc,
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&s3c_device_iis,
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&s3c_device_usbgadget,
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&s3c_device_usb,
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&s3c_device_hsmmc0,
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&s3c_device_hsmmc1,
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//Qisda Tony 090324, add keypad [
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&s3c_device_keypad_qisda,
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//Qisda Tony 090324, add keypad ]
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//Qisda Tony 090406, add Auo touch i2c driver [
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&s3c_device_ts_iic,
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//Qisda Tony 090406, add Auo touch i2c driver ]
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};
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static struct s3c24xx_board smdk2416_board __initdata = {
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.devices = smdk2416_devices,
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.devices_count = ARRAY_SIZE(smdk2416_devices)
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};
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static void __init smdk2416_map_io(void)
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{
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s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
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s3c24xx_init_clocks(12000000);
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s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
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s3c24xx_set_board(&smdk2416_board);
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}
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static void smdk2416_cs89x0_set(void)
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{
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u32 val;
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val = readl(S3C_BANK_CFG);
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val &= ~((1<<8)|(1<<9)|(1<<10));
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writel(val, S3C_BANK_CFG);
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/* Bank1 Idle cycle ctrl. */
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writel(0xf, S3C_SSMC_SMBIDCYR1);
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/* Bank1 Read Wait State cont. = 14 clk Tacc? */
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writel(12, S3C_SSMC_SMBWSTRDR1);
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/* Bank1 Write Wait State ctrl. */
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writel(12, S3C_SSMC_SMBWSTWRR1);
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/* Bank1 Output Enable Assertion Delay ctrl. Tcho? */
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writel(2, S3C_SSMC_SMBWSTOENR1);
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/* Bank1 Write Enable Assertion Delay ctrl. */
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writel(2, S3C_SSMC_SMBWSTWENR1);
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/* SMWAIT active High, Read Byte Lane Enabl WS1? */
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val = readl(S3C_SSMC_SMBCR1);
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val |= ((1<<15)|(1<<7));
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writel(val, S3C_SSMC_SMBCR1);
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val = readl(S3C_SSMC_SMBCR1);
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val |= ((1<<2)|(1<<0));
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writel(val, S3C_SSMC_SMBCR1);
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val = readl(S3C_SSMC_SMBCR1);
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val &= ~((3<<20)|(3<<12));
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writel(val, S3C_SSMC_SMBCR1);
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val = readl(S3C_SSMC_SMBCR1);
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val &= ~(3<<4);
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writel(val, S3C_SSMC_SMBCR1);
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val = readl(S3C_SSMC_SMBCR1);
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val |= (1<<4);
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writel(val, S3C_SSMC_SMBCR1);
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}
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/* Qisda Mark Tsai, 2010/01/13 { */
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static void smdk2416_power_off(void)
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{
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printk("[smdk2416_power_off]T-CON Off\n");
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if(is_Epaper_Write_Ready())
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{
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//AUO T-CON Standby
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msleep(100);
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Epaper_Enter_Standby_Mode(1);
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msleep(100);
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//AUO T-CON Sleep
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Epaper_Enter_Sleep_Mode(1);
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msleep(5);
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//Shutdown T-CON Power
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Epaper_Power(0);
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//Shutdown i80 of s3c
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EPaper_CloseLcdPort();
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//msleep(1000);
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//u32PowerState = EN_EPD_DEVICE_POWER_STATE_D3;
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}
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printk("[smdk2416_power_off]Power Off\n");
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writeb(0x0, 0xc8a30029);
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msleep(100);
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#ifdef CONFIG_QISDA_BK060B00
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s3c2410_gpio_cfgpin(S3C2410_GPD14, S3C2410_GPG14_OUTP);
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s3c2410_gpio_setpin(S3C2410_GPG14, 0);
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#else
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s3c2410_gpio_cfgpin(S3C2410_GPG0, S3C2410_GPG0_OUTP);
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s3c2410_gpio_setpin(S3C2410_GPG0, 0);
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#endif
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}
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/* Qisda Mark Tsai, 2010/01/13 } */
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static void __init smdk2416_machine_init(void)
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{
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/* SROM init for NFS */
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smdk2416_cs89x0_set();
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smdk_machine_init();
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/* Qisda Mark Tsai, 2010/01/13 { */
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pm_power_off = smdk2416_power_off;
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/* Qisda Mark Tsai, 2010/01/13 } */
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}
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static void __init smdk2416_fixup (struct machine_desc *desc, struct tag *tags,
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char **cmdline, struct meminfo *mi)
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{
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/*
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* Bank start addresses are not present in the information
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* passed in from the boot loader. We could potentially
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* detect them, but instead we hard-code them.
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*/
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mi->bank[0].start = 0x30000000;
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#if defined(CONFIG_VIDEO_SAMSUNG)
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mi->bank[0].size = 49*1024*1024;
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#elif defined(CONFIG_PP_S3C2443)
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mi->bank[0].size = 60*1024*1024;
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#else
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/*Qisda Qube for 128MB*/
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#if defined(CONFIG_QISDA_E600_EVT2) || defined(CONFIG_QISDA_AS090B00_EVT1) || defined (CONFIG_QISDA_AS090B00_EVT1_1) || defined (CONFIG_QISDA_QD060N00_DVT1_1) ||defined (CONFIG_QISDA_L600) || defined (CONFIG_QISDA_QD090B00_EVT1)
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mi->bank[0].size = 128*1024*1024;
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#else
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mi->bank[0].size = 64*1024*1024;
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#endif
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/*Qisda Qube for 128MB*/
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#endif
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mi->bank[0].node = 0;
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mi->nr_banks = 1;
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}
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MACHINE_START(SMDK2416, "SMDK2416")
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/* Maintainer: Ben Dooks <ben@fluff.org> */
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.phys_io = S3C2410_PA_UART,
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.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
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.boot_params = S3C2410_SDRAM_PA + 0x100,
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.init_irq = s3c24xx_init_irq,
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.map_io = smdk2416_map_io,
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.fixup = smdk2416_fixup,
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.init_machine = smdk2416_machine_init,
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.timer = &s3c24xx_timer,
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MACHINE_END
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/*
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* HS-MMC GPIO Set function for S3C2416 SMDK board
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*/
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void hsmmc_set_gpio (uint channel, uint width)
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{
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switch (channel) {
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/* can supports 1 and 4 bit bus */
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case 0:
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/* GPIO E : Command, Clock */
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s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2450_GPE5_SD0_CLK);
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s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2450_GPE6_SD0_CMD);
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if (width == 1) {
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/* GPIO E : MMC DATA0[0] */
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s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
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}
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else if (width == 4) {
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/* GPIO E : MMC DATA0[0:3] */
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s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
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s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2450_GPE8_SD0_DAT1);
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s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2450_GPE9_SD0_DAT2);
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s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2450_GPE10_SD0_DAT3);
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}
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break;
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/* can supports 1, 4, and 8 bit bus */
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case 1:
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/* GPIO L : Command, Clock */
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s3c2410_gpio_cfgpin(S3C2443_GPL8, S3C2450_GPL8_SD1CMD);
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s3c2410_gpio_cfgpin(S3C2443_GPL9, S3C2450_GPL9_SD1CLK);
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/* GPIO J : Chip detect, LED, Write Protect */
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s3c2410_gpio_cfgpin(S3C2443_GPJ13, S3C2450_GPJ13_SD1LED);
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s3c2410_gpio_cfgpin(S3C2443_GPJ14, S3C2450_GPJ14_nSD1CD);
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s3c2410_gpio_cfgpin(S3C2443_GPJ15, S3C2450_GPJ15_nSD1WP); /* write protect enable */
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s3c2410_gpio_setpin(S3C2443_GPJ15, 1);
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if (width == 1) {
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/* GPIO L : MMC DATA1[0] */
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s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
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}
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else if (width == 4) {
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/* GPIO L : MMC DATA1[0:3] */
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s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
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s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
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s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
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s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
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}
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else if (width == 8) {
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/* GPIO L : MMC DATA1[0:7] */
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s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
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s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
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s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
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s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
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s3c2410_gpio_cfgpin(S3C2443_GPL4, S3C2450_GPL4_SD1DAT4);
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s3c2410_gpio_cfgpin(S3C2443_GPL5, S3C2450_GPL5_SD1DAT5);
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s3c2410_gpio_cfgpin(S3C2443_GPL6, S3C2450_GPL6_SD1DAT6);
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s3c2410_gpio_cfgpin(S3C2443_GPL7, S3C2450_GPL7_SD1DAT7);
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}
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break;
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default:
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break;
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}
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}
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EXPORT_SYMBOL_GPL(hsmmc_set_gpio);
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#define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | \
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MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
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/* Channel 0 : added HS-MMC channel */
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struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
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.hwport = 0,
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.enabled = 1,
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/* BAN 20090608 update for wifi driver fail*/
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//.host_caps = HOST_CAPS,
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.host_caps = 0xF ,
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/* BAN 20090608 update for wifi driver fail*/
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.bus_width = 4,
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.highspeed = 0,
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/* ctrl for mmc */
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.fd_ctrl[MMC_MODE_MMC] = {
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.ctrl2 = 0xC0000100, /* ctrl2 for mmc */
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.ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
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.ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
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.ctrl4 = 0x3,
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},
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/* ctrl for sd */
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.fd_ctrl[MMC_MODE_SD] = {
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.ctrl2 = 0xC0000100, /* ctrl2 for sd */
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.ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
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.ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
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.ctrl4 = 0x3,
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},
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.clk_name[0] = "hsmmc", /* 1st clock source */
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.clk_name[1] = "esysclk", /* 2nd clock source hsmmc-epll by Ben Dooks */
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.clk_name[2] = "hsmmc-ext", /* 3rd clock source */
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};
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/* Channel 1 : default HS-MMC channel */
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struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
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.hwport = 1,
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.enabled = 1,
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/* BAN 20090608 update for wifi driver fail*/
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//.host_caps = HOST_CAPS , /* GeorgeKuo_modify| MMC_CAP_8_BIT_DATA,*/
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.host_caps = 0xF ,
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/* BAN 20090608 update for wifi driver fail*/
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.bus_width = 8,
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.highspeed = 0,
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/* ctrl for mmc */
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.fd_ctrl[MMC_MODE_MMC] = {
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.ctrl2 = 0xC0000100, /* ctrl2 for mmc */
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.ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
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.ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
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.ctrl4 = 0x3,
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},
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/* ctrl for sd */
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.fd_ctrl[MMC_MODE_SD] = {
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.ctrl2 = 0xC0000100, /* ctrl2 for sd */
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.ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
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.ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
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.ctrl4 = 0x3,
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},
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.clk_name[0] = "hsmmc", /* 1st clock source */
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.clk_name[1] = "esysclk", /* 2nd clock source hsmmc-epll by Ben Dooks */
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.clk_name[2] = "hsmmc-ext", /* 3rd clock source */
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};
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