209 lines
4.6 KiB
C
209 lines
4.6 KiB
C
/* linux/arch/arm/mach-s3c2450/s3c2450.c
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*
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* Copyright (c) 2007 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* Ryu Euiyoul <ryu.real@gmail.com>
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*
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* Samsung S3C2450 Mobile CPU support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_core.h>
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#include <linux/sysdev.h>
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#include <linux/clk.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/proc-fns.h>
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#include <asm/arch/idle.h>
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#include <asm/arch/regs-s3c2450-clock.h>
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#include <asm/arch/reset.h>
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#include <asm/plat-s3c24xx/s3c2450.h>
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#include <asm/plat-s3c24xx/devs.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#include <asm/arch/regs-gpio.h>
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#undef DVS_IDLE
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static struct map_desc s3c2450_iodesc[] __initdata = {
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IODESC_ENT(WATCHDOG),
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IODESC_ENT(CLKPWR),
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IODESC_ENT(TIMER),
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IODESC_ENT(LCD),
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IODESC_ENT(USBDEV),
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IODESC_ENT(CAMIF),
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IODESC_ENT(EBI),
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IODESC_ENT(SROMC),
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};
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struct sysdev_class s3c2450_sysclass = {
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set_kset_name("s3c2450-core"),
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};
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static struct sys_device s3c2450_sysdev = {
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.cls = &s3c2450_sysclass,
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};
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static void s3c2450_hard_reset(void)
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{
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__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
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}
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int __init s3c2450_init(void)
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{
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printk("S3C2450: Initialising architecture\n");
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s3c24xx_reset_hook = s3c2450_hard_reset;
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s3c_device_nand.name = "s3c2412-nand";
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// For S3C nand
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s3c_device_nand.name = "s3c-nand";
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return sysdev_register(&s3c2450_sysdev);
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}
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#undef IDLE_PROBE
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static void s3c2450_idle(void)
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{
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unsigned long tmp;
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/*if you want to reduce CPU clock with idle */
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#ifdef DVS_IDLE
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tmp = __raw_readl(S3C2443_CLKDIV0);
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tmp &= ~(0x1<<13);
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tmp |= (0x1<<13);
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__raw_writel(tmp, S3C2443_CLKDIV0);
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#else
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/* ensure our idle mode is to go to idle */
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tmp = __raw_readl(S3C2443_PWRMODE);
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tmp &= ~(0x1<<17);
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tmp |= (0x1<<17);
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__raw_writel(tmp, S3C2443_PWRMODE);
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#endif
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/* in SMDK2450 you can probe the idle status through the TP11(GPB2) by Laputa*/
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#ifdef IDLE_PROBE
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tmp = __raw_readl(S3C2410_GPBDAT);
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tmp |= (0x1<<2);
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__raw_writel(tmp, S3C2410_GPBDAT);
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tmp &= ~(0x1<<2);
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__raw_writel(tmp, S3C2410_GPBDAT);
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#endif
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cpu_do_idle();
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}
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void __init s3c2450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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{
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s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
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/* rename devices that are s3c2413/s3c2443/s3c6400 specific */
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#if defined (CONFIG_S3C_SIR)
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s3c24xx_uart_src[2]->name = "s3c-irda";
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#endif
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s3c_device_lcd.name = "s3c-lcd";
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}
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/* s3c2443_map_io
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*
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* register the standard cpu IO areas, and any passed in from the
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* machine specific initialisation.
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*/
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void __init s3c2450_map_io(struct map_desc *mach_desc, int mach_size)
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{
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iotable_init(s3c2450_iodesc, ARRAY_SIZE(s3c2450_iodesc));
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iotable_init(mach_desc, mach_size);
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s3c24xx_idle = s3c2450_idle;
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}
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/* need to register class before we actually register the device, and
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* we also need to ensure that it has been initialised before any of the
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* drivers even try to use it (even if not on an s3c2443 based system)
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* as a driver which may support both 2443 and 2440 may try and use it.
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*/
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static int __init s3c2450_core_init(void)
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{
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return sysdev_class_register(&s3c2450_sysclass);
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}
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core_initcall(s3c2450_core_init);
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#define CAMDIV_val 26
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int s3c_camif_set_clock (unsigned int camclk)
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{
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unsigned int camclk_div, val, hclkcon;
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struct clk *src_clk = clk_get(NULL, "hclk");
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if (camclk == 4800000) {
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printk(KERN_INFO "External camera clock is set to 48MHz\n");
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}
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else if (camclk > 48000000) {
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printk(KERN_ERR "Invalid camera clock\n");
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}
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writel(readl(S3C2443_CLKSRC) | (1 << 20), S3C2443_CLKSRC);
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camclk_div = clk_get_rate(src_clk) / camclk;
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printk("Parent clock = %ld, CAMDIV = %d\n", clk_get_rate(src_clk), camclk_div);
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// CAMIF HCLK Enable
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hclkcon = __raw_readl(S3C2443_HCLKCON);
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hclkcon |= S3C2443_HCLKCON_CAMIF;
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__raw_writel(hclkcon, S3C2443_HCLKCON);
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/* CAMCLK Enable */
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val = readl(S3C2443_SCLKCON);
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val |= S3C2443_SCLKCON_CAMCLK;
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writel(val, S3C2443_SCLKCON);
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val = readl(S3C2443_CLKDIV1);
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val &= ~(0xf<<CAMDIV_val);
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writel(val, S3C2443_CLKDIV1);
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val |= ((camclk_div -1) << CAMDIV_val);
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writel(val, S3C2443_CLKDIV1);
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val = readl(S3C2443_CLKDIV1);
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return 0;
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}
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void s3c_camif_disable_clock (void)
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{
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unsigned int val;
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val = readl(S3C2443_SCLKCON);
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val &= ~S3C2443_SCLKCON_CAMCLK;
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writel(val, S3C2443_SCLKCON);
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}
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