717 lines
17 KiB
C
717 lines
17 KiB
C
/* linux/arch/arm/mach-s3c64xx/clock_s3c6400.c
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*
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* Copyright (c) 2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2412 Clock control support
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*
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* Based on, and code from linux/arch/arm/mach-versatile/clock.c
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**
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** Copyright (C) 2004 ARM Limited.
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** Written by Deep Blue Solutions Limited.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/sysdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <asm/mach/map.h>
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#include <asm/hardware.h>
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#include <asm/atomic.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/plat-s3c24xx/clock.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#include <asm/arch/regs-s3c6400-clock.h>
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#define HCLK_GATING_ON_LIST S3C_CLKCON_HCLK_BUS | S3C_CLKCON_HCLK_DDR1 | S3C_CLKCON_HCLK_DDR0 |\
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S3C_CLKCON_HCLK_MEM1 | S3C_CLKCON_HCLK_MEM0 | S3C_CLKCON_HCLK_DMA0 |\
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S3C_CLKCON_HCLK_DMA1 | S3C_CLKCON_HCLK_INTC | S3C_CLKCON_HCLK_LCD |\
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S3C_CLKCON_HCLK_DHOST | S3C_CLKCON_HCLK_POST0 | S3C_CLKCON_HCLK_MFC
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#define PCLK_GATING_ON_LIST S3C_CLKCON_PCLK_GPIO | S3C_CLKCON_PCLK_UART0 | S3C_CLKCON_PCLK_UART1 | S3C_CLKCON_PCLK_MFC
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#define SCLK_GATING_ON_LIST S3C_CLKCON_SCLK_UART | S3C_CLKCON_SCLK_LCD27 | S3C_CLKCON_SCLK_LCD | S3C_CLKCON_SCLK_POST1_27 | \
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S3C_CLKCON_SCLK_POST0_27 | S3C_CLKCON_SCLK_POST1 | S3C_CLKCON_SCLK_POST0 | S3C_CLKCON_SCLK_MFC
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/* Select the source clock of USB Host. 0:48MHz, 1:FoutEpll */
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#define S3C_USB_CLKSRC_EPLL 0
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/* old functions */
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void inline s3c_clk_enable (uint clocks, uint enable, ulong gate_reg)
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{
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unsigned long clkcon;
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unsigned long flags;
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local_irq_save(flags);
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clkcon = __raw_readl(gate_reg);
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clkcon &= ~clocks;
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if (enable)
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clkcon |= clocks;
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__raw_writel(clkcon, gate_reg);
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local_irq_restore(flags);
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}
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/*This function returns the virtual address of gating register*/
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ulong clk_get_gate_reg (struct clk *clk)
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{
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struct clk *parent_clk = clk_get_parent(clk) ;
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if (strcmp(parent_clk->name, "hclk") == 0)
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return (unsigned long) S3C_HCLK_GATE;
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else if (strcmp(parent_clk->name, "pclk") == 0)
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return (unsigned long) S3C_PCLK_GATE;
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else if (strcmp(parent_clk->name, "clk48m") == 0)
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return (unsigned long) S3C_OTHERS;
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else
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return (unsigned long) S3C_SCLK_GATE;
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}
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int s3c_clkcon_enable (struct clk *clk, int enable)
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{
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unsigned long gate_reg;
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gate_reg = clk_get_gate_reg(clk);
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s3c_clk_enable(clk->ctrlbit, enable, gate_reg);
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return 0;
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}
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static unsigned long s3c6400_clk_getrate(struct clk *clk)
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{
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/* set clock rate to use in drivers */
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if (!clk->rate) {
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if (clk->parent) {
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clk->rate = clk->parent->rate;
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}
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}
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return clk->rate;
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}
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#define CAMDIV_val 20
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static int s3c6400_setrate_camera(struct clk *clk, unsigned long rate)
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{
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unsigned int camclk_div, val;
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unsigned long src_clk = clk_get_rate(clk->parent);
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if (rate == 4800000) {
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printk(KERN_INFO "External camera clock is set to 48MHz\n");
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}
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else if (rate > 48000000) {
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printk(KERN_ERR "Invalid camera clock\n");
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}
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camclk_div = src_clk / rate;
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printk("Parent clock for Camera = %ld, CAMDIV = %d\n", src_clk, camclk_div);
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val = readl(S3C_CLK_DIV0);
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val &= ~(0xf<<CAMDIV_val);
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writel(val, S3C_CLK_DIV0);
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/* CAM CLK DIVider Ratio = (EPLL clk)/(camclk_div) */
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val |= ((camclk_div - 1) << CAMDIV_val);
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writel(val, S3C_CLK_DIV0);
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val = readl(S3C_CLK_DIV0);
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return 0;
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}
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static struct clk init_clocks_disable[] = {
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{
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.name = "nand",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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//.ctrlbit = S3C_CLKCON_HCLK_NAND,
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}, {
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.name = "adc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_TSADC,
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}, {
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.name = "i2c",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_IIC,
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}, {
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.name = "iis",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_IIS0,
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}, {
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.name = "iis",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_IIS1,
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}, {
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.name = "spi",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_SPI0,
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}, {
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.name = "spi",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_SPI1,
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}
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};
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/* standard clock definitions */
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static struct clk init_clocks[] = {
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/* AHB devices */
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{ .name = "dma 1",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_DMA1,
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},
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{ .name = "dma 0",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_DMA0,
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},
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{ .name = "lcd",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_LCD,
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},
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{ .name = "TZIC",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_TZIC,
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},
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{ .name = "INTC",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_INTC,
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},
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{ .name = "camif",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_CAMIF
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},
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{ .name = "otg",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_USB
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},
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{ .name = "hsmmc0",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.get_rate = s3c6400_clk_getrate,
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.ctrlbit = S3C_CLKCON_HCLK_HSMMC0
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},
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{ .name = "hsmmc1",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.get_rate = s3c6400_clk_getrate,
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.ctrlbit = S3C_CLKCON_HCLK_HSMMC1
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},
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{ .name = "hsmmc2",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.get_rate = s3c6400_clk_getrate,
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.ctrlbit = S3C_CLKCON_HCLK_HSMMC2
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},
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{ .name = "hclk_mfc",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_MFC
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},
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{ .name = "hclk_post0",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_POST0
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},
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{ .name = "hclk_jpeg",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_JPEG
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},
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{ .name = "tv_encoder",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_TV
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},
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{ .name = "tv_scaler",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_SCALER
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},
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/* register to use HS-MMC clock */
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{ .name = "sclk_48m",
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.id = -1,
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.parent = &clk_48m,
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.enable = s3c_clkcon_enable,
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.ctrlbit = 1<<16, /* USB SIG Mask */
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.usage = 0,
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.rate = 48*1000*1000,
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},
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{ .name = "sclk_48m_mmc0",
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.id = -1,
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.parent = &clk_s,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
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.usage = 0,
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.rate = 48*1000*1000,
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},
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{ .name = "sclk_48m_mmc1",
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.id = -1,
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.parent = &clk_s,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
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.usage = 0,
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.rate = 48*1000*1000,
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},
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{ .name = "sclk_48m_mmc2",
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.id = -1,
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.parent = &clk_s,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
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.usage = 0,
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.rate = 48*1000*1000,
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},
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{ .name = "sclk_mfc",
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.id = -1,
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.parent = &clk_s,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_SCLK_MFC,
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.usage = 0,
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.rate = 48*1000*1000,
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},
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{ .name = "sclk_jpeg",
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.id = -1,
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.parent = &clk_s,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_SCLK_JPEG,
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.usage = 0,
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.rate = 48*1000*1000,
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},
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{ .name = "cfata",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_IHOST
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},
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/* APB Devices */
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{ .name = "RTC",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_RTC,
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},
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{ .name = "GPIO",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_GPIO,
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},
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{ .name = "UART2",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_UART2,
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},
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{ .name = "UART1",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_UART1,
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},
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{ .name = "UART0",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_UART0,
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},
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{ .name = "timers",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_PWM,
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},
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{ .name = "watchdog",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_WDT,
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},
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{ .name = "i2c",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_IIC,
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},
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{ .name = "spi0",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_SPI0,
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},
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{ .name = "spi1",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_SPI1,
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},
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{ .name = "usb-host",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_HCLK_UHOST,
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},
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{ .name = "adc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_TSADC,
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},
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{ .name = "pclk_mfc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_PCLK_MFC,
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},
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{
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.name = "camera",
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.id = -1,
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.parent = &clk_hx2,
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.enable = s3c_clkcon_enable,
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.ctrlbit = S3C_CLKCON_SCLK_CAM,
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.set_rate = s3c6400_setrate_camera,
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},
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};
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/* boyko */
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int s3c_epll_clk_uart_enable (struct clk *clk, int enable)
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{
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unsigned long gate_reg;
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gate_reg = clk_get_gate_reg(clk);
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s3c_clk_enable(clk->ctrlbit, enable, gate_reg);
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/* MUXepll : FOUTepll */
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writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
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/* UARTsel : MOUTepll */
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writel((readl(S3C_CLK_SRC) & ~(0x1 << 13)) | (0 << 13), S3C_CLK_SRC);
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return 0;
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}
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static int s3c6400_setrate_epll_clk_192m(struct clk *clk, unsigned long rate)
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{
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writel(S3C_EPLL_EN|S3C_EPLLVAL(32,1,1), S3C_EPLL_CON0);
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writel(0, S3C_EPLL_CON1);
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mdelay(5);
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return 0;
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}
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static unsigned long s3c6400_getrate_epll_clk_192m(struct clk *clk)
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{
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s3c6400_setrate_epll_clk_192m(clk, 192000000);
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clk->rate = 192000000;
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return clk->rate;
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}
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static struct clk clk_epll_uart_192m = {
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.name = "epll_clk_uart_192m",
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.id = -1,
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.parent = &clk_epll,
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.enable = s3c_epll_clk_uart_enable,
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.ctrlbit = S3C_CLKCON_SCLK_UART,
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.set_rate = s3c6400_setrate_epll_clk_192m,
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.get_rate = s3c6400_getrate_epll_clk_192m,
|
|
};
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|
|
|
/* function for UART Clock with MPLL by boyko */
|
|
|
|
static unsigned long s3c6400_mpll_get_clk(struct clk *clk)
|
|
{
|
|
unsigned long mpll_con;
|
|
unsigned long m = 0;
|
|
unsigned long p = 0;
|
|
unsigned long s = 0;
|
|
unsigned long ret;
|
|
|
|
mpll_con = (readl(S3C_MPLL_CON));
|
|
|
|
m = (mpll_con >> 16) & 0x3ff;
|
|
p = (mpll_con >> 8) & 0x3f;
|
|
s = mpll_con & 0x3;
|
|
|
|
ret = (m * (12000000 / (p * (1 << s))));
|
|
|
|
return (((readl(S3C_CLK_DIV0) >> 13 ) & 0x1) ? (ret / 2) : ret );
|
|
|
|
}
|
|
|
|
static int s3c6400_mpll_clk_uart_enable (struct clk *clk, int enable)
|
|
{
|
|
unsigned long gate_reg;
|
|
|
|
gate_reg = clk_get_gate_reg(clk);
|
|
s3c_clk_enable(clk->ctrlbit, enable, gate_reg);
|
|
|
|
writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
|
|
|
|
writel((readl(S3C_CLK_SRC) & ~(0x1 << 13)) | (1 << 13), S3C_CLK_SRC);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int s3c6400_setrate_mpll_clk(struct clk *clk, unsigned long rate)
|
|
{
|
|
writel(readl(S3C_CLK_DIV2) & ~(0xf << 16) , S3C_CLK_DIV2);
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long s3c6400_getrate_mpll_clk(struct clk *clk)
|
|
{
|
|
s3c6400_setrate_mpll_clk(clk,0);
|
|
|
|
return s3c6400_mpll_get_clk(clk);
|
|
}
|
|
|
|
|
|
static struct clk clk_mpll_uart = {
|
|
.name = "mpll_clk_uart",
|
|
.id = -1,
|
|
.parent = &clk_mpll,
|
|
.enable = s3c6400_mpll_clk_uart_enable,
|
|
.ctrlbit = S3C_CLKCON_SCLK_UART,
|
|
.set_rate = s3c6400_setrate_mpll_clk,
|
|
.get_rate = s3c6400_getrate_mpll_clk,
|
|
};
|
|
|
|
/* clocks to add straight away */
|
|
|
|
static struct clk *clks[] __initdata = {
|
|
&clk_epll_uart_192m,
|
|
&clk_mpll_uart,
|
|
};
|
|
|
|
void __init s3c6400_init_clocks(int xtal)
|
|
{
|
|
unsigned long clkdiv0;
|
|
unsigned long fclk, fclk_org;
|
|
unsigned long hclkx2;
|
|
unsigned long hclk;
|
|
unsigned long pclk;
|
|
unsigned long epll_clk;
|
|
|
|
struct clk *clkp;
|
|
int ret;
|
|
int ptr;
|
|
|
|
clk_xtal.rate = xtal;
|
|
|
|
/* now we've got our machine bits initialised, work out what
|
|
* clocks we've got */
|
|
|
|
/* Changed below lines to support s3c6400 - JaeCheol Lee */
|
|
fclk = s3c6400_get_pll(__raw_readl(S3C_APLL_CON), xtal);
|
|
|
|
clkdiv0 = __raw_readl(S3C_CLK_DIV0);
|
|
|
|
fclk /= ((clkdiv0 & S3C_CLKDIVN_APLL_MASK)+1);
|
|
fclk_org = fclk;
|
|
|
|
if(!(__raw_readl(S3C_OTHERS) & 0x80)) {
|
|
fclk = s3c6400_get_pll(__raw_readl(S3C_MPLL_CON), xtal);
|
|
}
|
|
|
|
hclkx2 = fclk / (((clkdiv0 & S3C_CLKDIVN_HCLKX2_MASK)>>9)+1);
|
|
|
|
hclk = hclkx2 / (((clkdiv0 & S3C_CLKDIVN_HCLK_MASK)>>8)+1);
|
|
|
|
//it should get the divisor from register and then sets the pclk properly
|
|
pclk = hclkx2 / (((clkdiv0 & S3C_CLKDIVN_PCLK_MASK)>>12)+1);
|
|
/* print brief summary of clocks, etc */
|
|
|
|
printk("S3C6400: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
|
|
print_mhz(fclk_org), print_mhz(hclk),
|
|
print_mhz(pclk));
|
|
|
|
/* Default EPLL frequency : 192Mhz */
|
|
writel(S3C_EPLL_EN|S3C_EPLLVAL(32,1,1), S3C_EPLL_CON0);
|
|
writel(0, S3C_EPLL_CON1);
|
|
mdelay(50);
|
|
|
|
epll_clk = s3c6400_get_epll(xtal);
|
|
clk_epll.rate = epll_clk;
|
|
printk("S3C6400: EPLL %ld.%03ld MHz\n", print_mhz(epll_clk));
|
|
|
|
/* initialize hclkx2 by jsgood */
|
|
clk_hx2.rate = hclkx2;
|
|
|
|
/* initialise the clocks here, to allow other things like the
|
|
* console to use them, and to add new ones after the initialisation
|
|
*/
|
|
|
|
s3c24xx_setup_clocks(xtal, fclk_org, hclk, pclk);
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
|
|
clkp = clks[ptr];
|
|
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
}
|
|
|
|
/* register clocks from clock array */
|
|
clkp = init_clocks;
|
|
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
|
|
/* set clock rate to use in drivers */
|
|
if (!clkp->rate) {
|
|
if (clkp->parent) {
|
|
clkp->rate = clkp->parent->rate;
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_USB_OHCI_HCD
|
|
if (S3C_USB_CLKSRC_EPLL == 1) {
|
|
writel((readl(S3C_CLK_SRC)& ~S3C_CLKSRC_UHOST_MASK)
|
|
|S3C_CLKSRC_EPLL_CLKSEL|S3C_CLKSRC_UHOST_EPLL,
|
|
S3C_CLK_SRC);
|
|
|
|
/* USB host colock divider ratio is 2 */
|
|
writel((readl(S3C_CLK_DIV1)& ~S3C_CLKDIVN_UHOST_MASK)
|
|
|S3C_CLKDIV1_USBDIV2, S3C_CLK_DIV1);
|
|
} else { /* 48MHz */
|
|
writel(readl(S3C_CLK_SRC)& ~S3C_CLKSRC_UHOST_MASK, S3C_CLK_SRC);
|
|
writel(readl(S3C_OTHERS)|S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS);
|
|
|
|
/* USB host colock divider ratio is 1 */
|
|
writel(readl(S3C_CLK_DIV1)& ~S3C_CLKDIVN_UHOST_MASK, S3C_CLK_DIV1);
|
|
}
|
|
|
|
writel(readl(S3C_HCLK_GATE)|S3C_CLKCON_HCLK_UHOST|S3C_CLKCON_HCLK_SECUR,
|
|
S3C_HCLK_GATE);
|
|
writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_UHOST, S3C_SCLK_GATE);
|
|
|
|
#endif
|
|
|
|
|
|
/* We must be careful disabling the clocks we are not intending to
|
|
* be using at boot time, as subsytems such as the LCD which do
|
|
* their own DMA requests to the bus can cause the system to lockup
|
|
* if they where in the middle of requesting bus access.
|
|
*
|
|
* Disabling the LCD clock if the LCD is active is very dangerous,
|
|
* and therefore the bootloader should be careful to not enable
|
|
* the LCD clock if it is not needed.
|
|
*/
|
|
|
|
/* install (and disable) the clocks we do not need immediately */
|
|
|
|
clkp = init_clocks_disable;
|
|
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
|
|
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
|
|
(clkp->enable)(clkp, 0);
|
|
}
|
|
}
|
|
|
|
|
|
/* clocks that could be registered by external code */
|
|
struct clk s3c_dclk0 = {
|
|
.name = "dclk0",
|
|
.id = -1,
|
|
};
|
|
|
|
struct clk s3c_dclk1 = {
|
|
.name = "dclk1",
|
|
.id = -1,
|
|
};
|
|
|
|
struct clk s3c_clkout0 = {
|
|
.name = "clkout0",
|
|
.id = -1,
|
|
};
|
|
|
|
struct clk s3c_clkout1 = {
|
|
.name = "clkout1",
|
|
.id = -1,
|
|
};
|
|
|