496 lines
13 KiB
C
496 lines
13 KiB
C
/***********************************************************************
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*
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* linux/arch/arm/mach-s3c64xx/smdk6400.c
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*
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* $Id: mach-smdk6400.c,v 1.52 2008/07/17 01:51:09 yujiun Exp $
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*
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* Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* derived from linux/arch/arm/mach-s3c2410/devs.c, written by
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* Ben Dooks <ben@simtec.co.uk>
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*
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***********************************************************************/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <asm/setup.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/flash.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <asm/arch/regs-serial.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-mem.h>
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#include <asm/arch/nand.h>
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#include <asm/plat-s3c24xx/s3c6400.h>
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#include <asm/plat-s3c24xx/devs.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#include <asm/arch/hsmmc.h>
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#include <asm/plat-s3c24xx/common-smdk.h>
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#include <asm/arch-s3c2410/reserved_mem.h>
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#if defined(CONFIG_MACH_SANJOSE2)
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#include <asm/arch/regs-irq.h>
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#endif
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extern struct sys_timer s3c_timer;
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static struct map_desc smdk6400_iodesc[] __initdata = {
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IODESC_ENT(CS8900),
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};
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#define DEF_UCON S3C_UCON_DEFAULT
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#define DEF_ULCON S3C_LCON_CS8 | S3C_LCON_PNONE
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#define DEF_UFCON S3C_UFCON_RXTRIG8 | S3C_UFCON_FIFOMODE
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static struct s3c24xx_uart_clksrc smdk6400_serial_clocks[] = {
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/* UART Clock with MPLL by Boyko */
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[0] = {
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.name = "mpll_clk_uart",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 0,
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},
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#if 0 /* HS UART Source is changed from epll to mpll */
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[1] = {
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.name = "pclk",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 0,
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},
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#if defined (CONFIG_SERIAL_S3C64XX_HS_UART)
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[2] = {
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.name = "epll_clk_uart_192m",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 4000000,
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}
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#endif
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#endif
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};
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static struct s3c2410_uartcfg smdk6400_uartcfgs[] = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = DEF_UCON,
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.ulcon = DEF_ULCON,
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.ufcon = DEF_UFCON,
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.clocks = smdk6400_serial_clocks,
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.clocks_size = ARRAY_SIZE(smdk6400_serial_clocks),
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = DEF_UCON,
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.ulcon = DEF_ULCON,
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.ufcon = DEF_UFCON,
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.clocks = smdk6400_serial_clocks,
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.clocks_size = ARRAY_SIZE(smdk6400_serial_clocks),
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},
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = DEF_UCON,
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.ulcon = DEF_ULCON,
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.ufcon = DEF_UFCON,
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.clocks = smdk6400_serial_clocks,
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.clocks_size = ARRAY_SIZE(smdk6400_serial_clocks),
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},
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[3] = {
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.hwport = 3,
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.flags = 0,
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.ucon = DEF_UCON,
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.ulcon = DEF_ULCON,
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.ufcon = DEF_UFCON,
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.clocks = smdk6400_serial_clocks,
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.clocks_size = ARRAY_SIZE(smdk6400_serial_clocks),
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}
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};
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/*add devices as drivers are integrated*/
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static struct platform_device *smdk6400_devices[] __initdata = {
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&s3c_device_lcd,
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&s3c_device_rtc,
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&s3c_device_ac97,
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&s3c_device_iis,
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&s3c_device_adc,
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&s3c_device_i2c,
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&s3c_device_usb,
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&s3c_device_usbgadget,
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&s3c_device_tvenc,
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&s3c_device_tvscaler,
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&s3c_device_hsmmc0,
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&s3c_device_hsmmc1,
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&s3c_device_hsmmc2,
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&s3c_device_wdt,
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&s3c_device_jpeg,
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&s3c_device_vpp,
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&s3c_device_ide,
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&s3c_device_mfc,
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&s3c_device_spi0,
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&s3c_device_spi1,
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&s3c_device_2d,
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&s3c_device_keypad,
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&s3c_device_camif,
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};
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static struct s3c24xx_board smdk6400_board __initdata = {
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.devices = smdk6400_devices,
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.devices_count = ARRAY_SIZE(smdk6400_devices)
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};
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static void __init smdk6400_map_io(void)
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{
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s3c24xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
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s3c24xx_init_clocks(0);
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s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
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s3c24xx_set_board(&smdk6400_board);
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}
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void smdk6400_cs89x0_set(void)
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{
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unsigned int tmp;
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tmp = __raw_readl(S3C_SROM_BW);
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tmp &=~(0xF<<4);
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tmp |= (1<<7) | (1<<6) | (1<<4);
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__raw_writel(tmp, S3C_SROM_BW);
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__raw_writel((0x0<<28)|(0x4<<24)|(0xd<<16)|(0x1<<12)|(0x4<<8)|(0x6<<4)|(0x0<<0), S3C_SROM_BC1);
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#if defined(CONFIG_MACH_SANJOSE2)
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__raw_writel(0, S3C_GPPPU);
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__raw_writel((__raw_readl(S3C_GPPCON) & ~(0x3 << 14)) | (0x1 << 14), S3C_GPPCON);
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#endif
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}
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static void __init smdk6400_fixup (struct machine_desc *desc, struct tag *tags,
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char **cmdline, struct meminfo *mi)
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{
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/*
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* Bank start addresses are not present in the information
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* passed in from the boot loader. We could potentially
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* detect them, but instead we hard-code them.
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*/
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mi->bank[0].start = 0x50000000;
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#if defined(CONFIG_RESERVED_MEM_JPEG)
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mi->bank[0].size = 120*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_JPEG_POST)
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mi->bank[0].size = 112*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_MFC)
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mi->bank[0].size = 122*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_MFC_POST)
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mi->bank[0].size = 114*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_JPEG_MFC_POST)
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mi->bank[0].size = 106*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_JPEG_CAMERA)
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mi->bank[0].size = 105*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_JPEG_POST_CAMERA)
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mi->bank[0].size = 97*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_MFC_CAMERA)
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mi->bank[0].size = 107*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_MFC_POST_CAMERA)
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mi->bank[0].size = 99*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_JPEG_MFC_POST_CAMERA)
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mi->bank[0].size = 91*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_CMM_MFC_POST)
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mi->bank[0].size = 106*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_CMM_JPEG_MFC_POST_CAMERA)
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mi->bank[0].size = 83*1024*1024;
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#elif defined(CONFIG_RESERVED_MEM_TV_MFC_POST_CAMERA)
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mi->bank[0].size = 91*1024*1024;
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#elif defined(CONFIG_VIDEO_SAMSUNG)
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mi->bank[0].size = 113*1024*1024;
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#else
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mi->bank[0].size = 128*1024*1024;
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#endif
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mi->bank[0].node = 0;
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mi->nr_banks = 1;
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}
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static void smdk6400_hsmmc_init (void)
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{
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/* jsgood: hsmmc0/1 card detect pin should be high before setup gpio. (GPG6 to Input) */
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writel(readl(S3C_GPGCON) & 0xf0ffffff, S3C_GPGCON);
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#if defined(CONFIG_MACH_SANJOSE2)
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/* for hsmmc ch2 */
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writel(0, S3C_GPNPU);
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writel((readl(S3C_GPNCON) & ~(0x3 << 24)) | (0x2 << 24), S3C_GPNCON); /* GPN12 to EINT */
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writel(readl(S3C_EINT0CON0) | (0x3 << 25), S3C_EINT0CON0); /* EINT12 to both edge triggered */
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writel(readl(S3C_EINT0MASK) & ~(0x1 << 12), S3C_EINT0MASK); /* EINT12 unmask */
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writel(readl(S3C_VIC1INTENABLE) | (0x1 << 0), S3C_VIC1INTENABLE); /* EINT12 enable */
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#if 0
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/* smdk6400 */
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writel((readl(S3C_GPNCON) & ~(0x3 << 30)) | (0x2 << 30), S3C_GPNCON); /* GPN15 to EINT */
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writel(readl(S3C_EINT0CON0) | (0x3 << 29), S3C_EINT0CON0); /* EINT15 to both edge triggered */
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writel(readl(S3C_EINT0MASK) & ~(0x1 << 15), S3C_EINT0MASK); /* EINT15 unmask */
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writel(readl(S3C_VIC1INTENABLE) | (0x1 << 4), S3C_VIC1INTENABLE); /* EINT15 enable */
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#endif
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/* GPC7 to high for usb power up */
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s3c_gpio_cfgpin(S3C_GPC7, S3C_GPC7_OUTP);
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s3c_gpio_setpin(S3C_GPC7, 1);
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#endif
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}
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static void __init smdk6400_machine_init (void)
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{
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smdk6400_cs89x0_set();
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smdk_machine_init();
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smdk6400_hsmmc_init();
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}
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MACHINE_START(SMDK6400, "SMDK6400")
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/* Maintainer: Samsung Electronics */
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.phys_io = S3C24XX_PA_UART,
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.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
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.boot_params = S3C_SDRAM_PA + 0x100,
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.init_irq = s3c_init_irq,
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.map_io = smdk6400_map_io,
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.fixup = smdk6400_fixup,
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.timer = &s3c_timer,
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.init_machine = smdk6400_machine_init,
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MACHINE_END
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/*--------------------------------------------------------------
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* HS-MMC GPIO Set function
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* the location of this function must be re-considered.
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* by scsuh
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*--------------------------------------------------------------*/
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void hsmmc_set_gpio (uint channel, uint width)
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{
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u32 reg;
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switch (channel) {
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/* can supports 1 and 4 bit bus */
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case 0:
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if (width == 1) {
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/* MMC CLK0, MMC CMD0, MMC DATA0[0], MMC CDn0 0~2,6 */
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reg = readl(S3C_GPGCON) & 0xf0fff000;
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writel(reg | 0x02000222, S3C_GPGCON);
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reg = readl(S3C_GPGPU) & 0xffffcfc0;
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writel(reg, S3C_GPGPU);
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}
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else if (width == 4) {
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/* MMC CLK0, MMC CMD0, MMC DATA0[0-3], MMC CDn0 0~6 */
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reg = readl(S3C_GPGCON) & 0xf0000000;
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writel(reg | 0x02222222, S3C_GPGCON);
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reg = readl(S3C_GPGPU) & 0xfffff000;
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writel(reg, S3C_GPGPU);
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}
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break;
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/* can supports 1, 4, and 8 bit bus */
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case 1:
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/* MMC CDn1 - 6 */
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reg = readl(S3C_GPGCON) & 0xf0ffffff;
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writel(reg | 0x03000000, S3C_GPGCON);
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reg = readl(S3C_GPGPU) & 0xffffcfff;
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writel(reg, S3C_GPGPU);
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if (width == 1) {
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/* MMC CLK1, MMC CMD1, MMC DATA1[0] - 0~2 */
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reg = readl(S3C_GPH0CON) & 0xfffff000;
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writel(reg | 0x222, S3C_GPH0CON);
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reg = readl(S3C_GPHPU) & 0xffffffc0;
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writel(reg, S3C_GPHPU);
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}
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else if (width == 4) {
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/* MMC CLK1, MMC CMD1, MMC DATA1[0-3] - 0~5 */
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reg = readl(S3C_GPH0CON) & 0xff000000;
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writel(reg | 0x00222222, S3C_GPH0CON);
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reg = readl(S3C_GPHPU) & 0xfffff000;
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writel(reg, S3C_GPHPU);
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}
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else if (width == 8) {
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/* MMC CLK1, MMC CMD1, MMC DATA1[0-5] - 0~7 */
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writel(0x22222222, S3C_GPH0CON);
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/* MMC DATA1[6-7] 8~9 */
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writel(0x00000022, S3C_GPH1CON);
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reg = readl(S3C_GPHPU) & 0xfff00000;
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writel(reg, S3C_GPHPU);
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}
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break;
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/* can supports 1 and 4 bit bus, no irq_cd */
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case 2:
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/* MMC CLK2, MMC CMD2 */
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reg = readl(S3C_GPCCON) & 0xff00ffff;
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writel(reg | 0x00330000, S3C_GPCCON);
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reg = readl(S3C_GPCPU) & 0xfffff0ff;
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writel(reg, S3C_GPCPU);
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if (width == 1) {
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/* MMC DATA2[0] */
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reg = readl(S3C_GPH0CON) & 0xf0ffffff;
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writel(reg | 0x03000000, S3C_GPH0CON);
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reg = readl(S3C_GPHPU) & 0xfffff3ff;
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writel(reg, S3C_GPHPU);
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}
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else if (width == 4) {
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/* MMC DATA2[1] */
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reg = readl(S3C_GPH0CON) & 0x00ffffff;
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writel(reg | 0x33000000, S3C_GPH0CON);
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/* MMC DATA2[2-3] */
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writel(0x00000033, S3C_GPH1CON);
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reg = readl(S3C_GPHPU) & 0xfff00fff;
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writel(reg, S3C_GPHPU);
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}
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break;
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default:
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break;
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}
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}
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/* For host controller's capabilities */
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#define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | \
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MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
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struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
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.hwport = 0,
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.enabled = 0,
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.host_caps = HOST_CAPS,
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.bus_width = 4,
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.highspeed = 0,
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/* ctrl for mmc */
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.fd_ctrl[MMC_MODE_MMC] = {
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.ctrl2 = 0xC0004100, /* ctrl2 for mmc */
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.ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
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.ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
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.ctrl4 = 0,
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},
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/* ctrl for sd */
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.fd_ctrl[MMC_MODE_SD] = {
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.ctrl2 = 0xC0000100, /* ctrl2 for sd */
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.ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
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.ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
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.ctrl4 = 0,
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},
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.clk_name[0] = "hsmmc0", /* 1st clock source */
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.clk_name[1] = "", /* 2nd clock source */
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.clk_name[2] = "sclk_48m_mmc0", /* 3rd clock source */
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};
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struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
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.hwport = 1,
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.enabled = 1,
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.host_caps = HOST_CAPS | MMC_CAP_8_BIT_DATA,
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.bus_width = 8,
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.highspeed = 0,
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/* ctrl for mmc */
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.fd_ctrl[MMC_MODE_MMC] = {
|
|
.ctrl2 = 0xC0004100, /* ctrl2 for mmc */
|
|
.ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
|
|
.ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
|
|
.ctrl4 = 0,
|
|
},
|
|
|
|
/* ctrl for sd */
|
|
.fd_ctrl[MMC_MODE_SD] = {
|
|
.ctrl2 = 0xC0000100, /* ctrl2 for sd */
|
|
.ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
|
|
.ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
|
|
.ctrl4 = 0,
|
|
},
|
|
|
|
.clk_name[0] = "hsmmc1", /* 1st clock source */
|
|
.clk_name[1] = "", /* 2nd clock source */
|
|
.clk_name[2] = "sclk_48m_mmc1", /* 3rd clock source */
|
|
};
|
|
|
|
struct s3c_hsmmc_cfg s3c_hsmmc2_platform = {
|
|
.hwport = 2,
|
|
.enabled = 0,
|
|
.host_caps = HOST_CAPS,
|
|
.bus_width = 4,
|
|
.highspeed = 0,
|
|
|
|
/* ctrl for mmc */
|
|
.fd_ctrl[MMC_MODE_MMC] = {
|
|
.ctrl2 = 0xC0004100, /* ctrl2 for mmc */
|
|
.ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
|
|
.ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
|
|
.ctrl4 = 0,
|
|
},
|
|
|
|
/* ctrl for sd */
|
|
.fd_ctrl[MMC_MODE_SD] = {
|
|
.ctrl2 = 0xC0000100, /* ctrl2 for sd */
|
|
.ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
|
|
.ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
|
|
.ctrl4 = 0,
|
|
},
|
|
|
|
.clk_name[0] = "hsmmc2", /* 1st clock source */
|
|
.clk_name[1] = "", /* 2nd clock source */
|
|
.clk_name[2] = "sclk_48m_mmc2", /* 3rd clock source */
|
|
};
|
|
|