810 lines
21 KiB
C
810 lines
21 KiB
C
/* linux/drivers/mtd/nand/s3c_nand.c
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*
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* Copyright (c) 2007 Samsung Electronics
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*
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* Samsung S3C NAND driver
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*
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* $Id: s3c_nand.c,v 1.20 2008/04/30 07:36:39 ihlee215 Exp $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Based on nand driver from Ben Dooks <ben@simtec.co.uk>
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* modified by scsuh. based on au1550nd.c
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*
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* Many functions about hardware ecc are implemented by jsgood.
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*/
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/* Simple H/W Table for Implementation of S3C nand driver
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* by scsuh
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* ------------------------------------------------------------------
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* | En/Dis CE | required | |
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* | En/Dis ALE | X | * nand controller does |
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* | En/Dis CLE | X | * nand controller does |
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* | Wait/Ready | required | |
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* | Write Command | required | |
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* | Write Address | required | |
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* | Write Data | required | |
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* | Read Data | required | |
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* | WP on/off | required | * board specific |
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* | AP Specific Init | required | |
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* ------------------------------------------------------------------
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/jiffies.h>
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#include <linux/sched.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/nand.h>
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#include <asm/arch/regs-nand.h>
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struct s3c_nand_info {
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/* mtd info */
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struct nand_hw_control controller;
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struct s3c_nand_mtd_info *mtds;
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struct s3c2410_platform_nand *platform;
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/* device info */
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struct device *device;
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struct resource *area;
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struct clk *clk;
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void __iomem *regs;
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void __iomem *sel_reg;
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int sel_bit;
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int mtd_count;
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//enum s3c_cpu_type cpu_type;
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};
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static struct s3c_nand_info s3c_nand;
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static struct mtd_info *s3c_mtd = NULL;
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/* Nand flash definition values by jsgood */
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#define S3C_NAND_TYPE_UNKNOWN 0x0
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#define S3C_NAND_TYPE_SLC 0x1
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#define S3C_NAND_TYPE_MLC 0x2
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/*
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* Cached progamming disabled for now, Not sure if its worth the
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* trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
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*
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* if want to use cached program, define next
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* by jsgood (modified to keep prevent rule)
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*/
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#undef CONFIG_MTD_NAND_S3C_CACHEDPROG
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/* Nand flash global values by jsgood */
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int cur_ecc_mode = 0;
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int nand_type = S3C_NAND_TYPE_UNKNOWN;
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/* Nand flash oob definition for SLC 512b page size by jsgood */
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static struct nand_ecclayout s3c_nand_oob_16 = {
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.eccbytes = 3,
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.eccpos = {2, 3, 4},
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.oobfree = {
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{.offset = 6,
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.length = 10}}
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};
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#if 1
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/* Nand flash oob definition for SLC 2k page size by jsgood */
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static struct nand_ecclayout s3c_nand_oob_64 = {
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.eccbytes = 4,
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.eccpos = {40, 41, 42, 43},
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.oobfree = {
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{.offset = 2,
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.length = 38}}
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};
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#else
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static struct nand_ecclayout s3c_nand_oob_64 = {
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.eccbytes = 4,
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.eccpos = {56, 57, 58, 59},
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.oobfree = {
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{2, 6}, {13, 3}, {18, 6}, {29, 3},
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{34, 6}, {45, 3}, {50, 6}, {61, 3}}
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};
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#endif
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/* Nand flash oob definition for MLC 2k page size by jsgood */
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static struct nand_ecclayout s3c_nand_oob_mlc_64 = {
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.eccbytes = 32,
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.eccpos = {
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32, 33, 34, 35, 36, 37, 38, 39,
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40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55,
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56, 57, 58, 59, 60, 61, 62, 63},
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.oobfree = {
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{.offset = 2,
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.length = 28}}
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};
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#if defined(CONFIG_MTD_NAND_S3C_DEBUG)
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/*
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* Function to print out oob buffer for debugging
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* Written by jsgood
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*/
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void print_oob(const char *header, struct mtd_info *mtd)
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{
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int i;
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struct nand_chip *chip = mtd->priv;
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printk("%s:\t", header);
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for(i = 0; i < 64; i++)
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printk("%02x ", chip->oob_poi[i]);
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printk("\n");
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}
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EXPORT_SYMBOL(print_oob);
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#endif
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/*
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* Hardware specific access to control-lines function
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* Written by jsgood
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*/
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static void s3c_nand_hwcontrol(struct mtd_info *mtd, int dat, unsigned int ctrl)
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{
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unsigned int cur;
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void __iomem *regs = s3c_nand.regs;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_NCE) {
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if (dat != NAND_CMD_NONE) {
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cur = readl(regs + S3C2440_NFCONT);
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cur &= ~S3C2412_NFCONT_nFCE0;
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writel(cur, regs + S3C2440_NFCONT);
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}
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} else {
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cur = readl(regs + S3C2440_NFCONT);
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cur |= S3C2412_NFCONT_nFCE0;
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writel(cur, regs + S3C2440_NFCONT);
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}
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}
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if (dat != NAND_CMD_NONE) {
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if (ctrl & NAND_CLE)
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writeb(dat, regs + S3C2440_NFCMD);
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else if (ctrl & NAND_ALE)
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writeb(dat, regs + S3C2440_NFADDR);
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}
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}
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/*
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* Function for checking device ready pin
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* Written by jsgood
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*/
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static int s3c_nand_device_ready(struct mtd_info *mtd)
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{
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void __iomem *regs = s3c_nand.regs;
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/* it's to check the RnB nand signal bit and return to device ready condition in nand_base.c */
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return ((readl(regs + S3C2412_NFSTAT) & S3C2410_NFSTAT_BUSY));
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}
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/*
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* Flash based bbt used
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*/
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static int s3c_nand_scan_bbt(struct mtd_info *mtd)
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{
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return nand_default_bbt(mtd);
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}
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#if defined(CONFIG_MTD_NAND_S3C_HWECC)
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#if 0
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/*
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* S3C Nand flash chip enable function
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* Written by jsgood
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*/
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static void s3c_nand_ce_on(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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chip->cmd_ctrl(mtd, 0x0, NAND_NCE | NAND_CTRL_CHANGE);
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nand_wait_ready(mtd);
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}
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/*
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* S3C Nand flash chip disable function
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* Written by jsgood
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*/
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static void s3c_nand_ce_off(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_CTRL_CHANGE);
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nand_wait_ready(mtd);
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}
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#endif
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/*
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* Function for checking ECCEncDone in NFSTAT
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* Written by jsgood
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*/
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static void s3c_nand_wait_enc(void)
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{
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/* S3C2412 can not check S3C2412_NFSTAT_ECC_ENCDONE */
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#if defined(CONFIG_S3C2443) || defined(CONFIG_S3C6400) || defined(CONFIG_S3C2450) || defined(CONFIG_CPU_S3C2416)
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void __iomem *regs = s3c_nand.regs;
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unsigned long timeo = jiffies;
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timeo += 16; /* when Hz=200, jiffies interval 1/200=5mS, waiting for 80mS 80/5 = 16 */
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/* Apply this short delay always to ensure that we do wait tWB in
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* any case on any machine. */
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while (time_before(jiffies, timeo)) {
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if( readl(regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_ECC_ENCDONE )
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break;
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cond_resched();
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}
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#else
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return;
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#endif
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}
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/*
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* Function for checking ECCDecDone in NFSTAT
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* Written by jsgood
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*/
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static void s3c_nand_wait_dec(void)
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{
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void __iomem *regs = s3c_nand.regs;
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unsigned long timeo = jiffies;
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timeo += 16; /* when Hz=200, jiffies interval 1/200=5mS, waiting for 80mS 80/5 = 16 */
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/* Apply this short delay always to ensure that we do wait tWB in
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* any case on any machine. */
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while (time_before(jiffies, timeo)) {
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if(readl(regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_ECC_DECDONE)
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break;
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cond_resched();
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}
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}
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/*
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* Function for checking ECC Busy
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* Written by jsgood
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*/
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static void s3c_nand_wait_ecc_busy(void)
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{
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void __iomem *regs = s3c_nand.regs;
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unsigned long timeo = jiffies;
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timeo += 16; /* when Hz=200, jiffies interval 1/200=5mS, waiting for 80mS 80/5 = 16 */
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/* Apply this short delay always to ensure that we do wait tWB in
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* any case on any machine. */
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while (time_before(jiffies, timeo)) {
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if (!(readl(regs + S3C2412_NFMECC_ERR0) & S3C_NFSTAT0_ECCBUSY))
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break;
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cond_resched();
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}
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}
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/*
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* This function is called before encoding ecc codes to ready ecc engine.
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* Written by jsgood
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*/
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void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct nand_chip *nand = mtd->priv;
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u_long nfcont;
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u_long nfconf;
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void __iomem *regs = s3c_nand.regs;
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cur_ecc_mode = mode;
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#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
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nfconf = readl(regs + S3C2410_NFCONF);
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if (((nand->cellinfo >> 2) & 0x3) == 0)
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nfconf &= ~S3C2412_NFCONF_ECC_MLC; /* SLC */
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else
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nfconf |= S3C2412_NFCONF_ECC_MLC; /* MLC */
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writel(nfconf, regs + S3C2410_NFCONF);
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#endif
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/* Init main ECC & unlock */
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nfcont = readl(regs + S3C2440_NFCONT);
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nfcont |= S3C_NFCONT_INITECC;
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nfcont &= ~S3C2412_NFCONT_MAIN_ECC_LOCK;
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#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
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if (mode == NAND_ECC_WRITE)
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nfcont |= S3C2412_NFCONT_ECC4_DIRWR;
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else if (mode == NAND_ECC_READ)
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nfcont &= ~S3C2412_NFCONT_ECC4_DIRWR;
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#endif
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writel(nfcont, regs + S3C2440_NFCONT);
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}
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/*
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* This function is called immediately after encoding ecc codes.
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* This function returns encoded ecc codes.
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* Written by jsgood
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*/
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int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
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{
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u_long nfcont, nfmecc0, nfmecc1;
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void __iomem *regs = s3c_nand.regs;
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/* Lock */
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nfcont = readl(regs + S3C2440_NFCONT);
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nfcont |= S3C2412_NFCONT_MAIN_ECC_LOCK;
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writel(nfcont, regs + S3C2440_NFCONT);
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if (nand_type == S3C_NAND_TYPE_SLC) {
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nfmecc0 = readl(regs + S3C2412_NFMECC0);
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ecc_code[0] = nfmecc0 & 0xff;
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ecc_code[1] = (nfmecc0 >> 8) & 0xff;
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ecc_code[2] = (nfmecc0 >> 16) & 0xff;
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ecc_code[3] = (nfmecc0 >> 24) & 0xff;
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} else {
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if (cur_ecc_mode == NAND_ECC_READ)
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s3c_nand_wait_dec();
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else {
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s3c_nand_wait_enc();
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nfmecc0 = readl(regs + S3C2412_NFMECC0);
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nfmecc1 = readl(regs + S3C2412_NFMECC1);
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ecc_code[0] = nfmecc0 & 0xff;
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ecc_code[1] = (nfmecc0 >> 8) & 0xff;
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ecc_code[2] = (nfmecc0 >> 16) & 0xff;
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ecc_code[3] = (nfmecc0 >> 24) & 0xff;
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ecc_code[4] = nfmecc1 & 0xff;
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ecc_code[5] = (nfmecc1 >> 8) & 0xff;
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ecc_code[6] = (nfmecc1 >> 16) & 0xff;
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ecc_code[7] = (nfmecc1 >> 24) & 0xff;
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}
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}
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return 0;
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}
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/*
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* This function determines whether read data is good or not.
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* If SLC, must write ecc codes to controller before reading status bit.
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* If MLC, status bit is already set, so only reading is needed.
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* If status bit is good, return 0.
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* If correctable errors occured, do that.
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* If uncorrectable errors occured, return -1.
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* Written by jsgood
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*/
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int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
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{
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int ret = -1;
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u_long nfestat0, nfestat1, nfmeccdata0, nfmeccdata1, nfmlcbitpt;
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u_char err_type;
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void __iomem *regs = s3c_nand.regs;
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if (!dat) {
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printk("No page data.\n");
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return ret;
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}
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if (nand_type == S3C_NAND_TYPE_SLC) {
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/* SLC: Write ECC data to compare */
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nfmeccdata0 = (calc_ecc[1] << 16) | calc_ecc[0];
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nfmeccdata1 = (calc_ecc[3] << 16) | calc_ecc[2];
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writel(nfmeccdata0, regs + S3C2440_NFECCD0);
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writel(nfmeccdata1, regs + S3C2440_NFECCD1);
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/* Read ECC status */
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nfestat0 = readl(regs + S3C2412_NFMECC_ERR0);
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err_type = nfestat0 & 0x3;
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switch (err_type) {
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case 0: /* No error */
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ret = 0;
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break;
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case 1: /* 1 bit error (Correctable)
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(nfestat0 >> 7) & 0x7ff :error byte number
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(nfestat0 >> 4) & 0x7 :error bit number */
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printk("S3C NAND: 1 bit error detected at byte %ld. Correcting from "
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"0x%02x ", (nfestat0 >> 7) & 0x7ff, dat[(nfestat0 >> 7) & 0x7ff]);
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dat[(nfestat0 >> 7) & 0x7ff] ^= (1 << ((nfestat0 >> 4) & 0x7));
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printk("to 0x%02x...OK\n", dat[(nfestat0 >> 7) & 0x7ff]);
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ret = 1;
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break;
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case 2: /* Multiple error */
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case 3: /* ECC area error */
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printk("S3C NAND: ECC uncorrectable error detected. Not correctable.\n");
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ret = -1;
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break;
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}
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} else {
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/* MLC: */
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s3c_nand_wait_ecc_busy();
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nfestat0 = readl(regs + S3C2412_NFMECC_ERR0);
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nfestat1 = readl(regs + S3C2412_NFMECC_ERR1);
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nfmlcbitpt = readl(regs + S3C_NFMLCBITPT);
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err_type = (nfestat0 >> 26) & 0x7;
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/* No error, If free page (all 0xff) */
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if ((nfestat0 >> 29) & 0x1) {
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err_type = 0;
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} else {
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/* No error, If all 0xff from 17th byte in oob (in case of JFFS2 format) */
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if (dat) {
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if (dat[17] == 0xff && dat[26] == 0xff && dat[35] == 0xff && dat[44] == 0xff && dat[54] == 0xff)
|
|
err_type = 0;
|
|
}
|
|
}
|
|
|
|
switch (err_type) {
|
|
case 5: /* Uncorrectable */
|
|
printk("S3C NAND: ECC uncorrectable error detected.\n");
|
|
ret = -1;
|
|
break;
|
|
|
|
case 4: /* 4 bit error (Correctable) */
|
|
dat[(nfestat1 >> 16) & 0x3ff] ^= ((nfmlcbitpt >> 24) & 0xff);
|
|
|
|
case 3: /* 3 bit error (Correctable) */
|
|
dat[nfestat1 & 0x3ff] ^= ((nfmlcbitpt >> 16) & 0xff);
|
|
|
|
case 2: /* 2 bit error (Correctable) */
|
|
dat[(nfestat0 >> 16) & 0x3ff] ^= ((nfmlcbitpt >> 8) & 0xff);
|
|
|
|
case 1: /* 1 bit error (Correctable) */
|
|
printk("S3C NAND: %d bit(s) error detected. Corrected successfully.\n", err_type);
|
|
dat[nfestat0 & 0x3ff] ^= (nfmlcbitpt & 0xff);
|
|
ret = err_type;
|
|
break;
|
|
|
|
case 0: /* No error */
|
|
ret = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Hardware specific page read function for MLC.
|
|
* Written by jsgood
|
|
*/
|
|
int s3c_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
|
|
uint8_t *buf)
|
|
{
|
|
int i, stat, eccsize = chip->ecc.size;
|
|
int eccbytes = chip->ecc.bytes;
|
|
int eccsteps = chip->ecc.steps;
|
|
int col = 0;
|
|
uint8_t *p = buf;
|
|
uint32_t *mecc_pos = chip->ecc.layout->eccpos;
|
|
|
|
/* Step1: read whole oob */
|
|
col = mtd->writesize;
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
|
|
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
col = 0;
|
|
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
|
|
chip->ecc.hwctl(mtd, NAND_ECC_READ);
|
|
chip->read_buf(mtd, p, eccsize);
|
|
chip->write_buf(mtd, chip->oob_poi + mecc_pos[0] + ((chip->ecc.steps - eccsteps) * eccbytes), eccbytes);
|
|
chip->ecc.calculate(mtd, 0, 0);
|
|
stat = chip->ecc.correct(mtd, p, 0, 0);
|
|
|
|
if (stat == -1)
|
|
mtd->ecc_stats.failed++;
|
|
|
|
col = eccsize * (chip->ecc.steps + 1 - eccsteps);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Hardware specific page write function for MLC.
|
|
* Written by jsgood
|
|
*/
|
|
void s3c_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
|
const uint8_t *buf)
|
|
{
|
|
int i, eccsize = chip->ecc.size;
|
|
int eccbytes = chip->ecc.bytes;
|
|
int eccsteps = chip->ecc.steps;
|
|
const uint8_t *p = buf;
|
|
uint8_t *ecc_calc = chip->buffers->ecccalc;
|
|
uint32_t *mecc_pos = chip->ecc.layout->eccpos;
|
|
|
|
/* Step1: write main data and encode mecc */
|
|
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
|
chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
|
|
chip->write_buf(mtd, p, eccsize);
|
|
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
|
|
}
|
|
|
|
/* Step2: save encoded mecc */
|
|
for (i = 0; i < chip->ecc.total; i++)
|
|
chip->oob_poi[mecc_pos[i]] = ecc_calc[i];
|
|
|
|
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
}
|
|
#endif
|
|
|
|
/* s3c_nand_probe
|
|
*
|
|
* called by device layer when it finds a device matching
|
|
* one our driver can handled. This code checks to see if
|
|
* it can allocate all necessary resources then calls the
|
|
* nand layer to look for devices
|
|
*/
|
|
static int s3c_nand_probe(struct platform_device *pdev)
|
|
{
|
|
struct s3c_nand_mtd_info *plat_info = pdev->dev.platform_data;
|
|
struct mtd_partition *partition_info = (struct mtd_partition *)plat_info->partition;
|
|
struct nand_chip *nand;
|
|
struct resource *res;
|
|
int err = 0;
|
|
int ret = 0;
|
|
int i, size;
|
|
u_char tmp;
|
|
struct nand_flash_dev *type = NULL;
|
|
|
|
|
|
/* get the clock source and enable it */
|
|
|
|
s3c_nand.clk = clk_get(&pdev->dev, "nand");
|
|
if (IS_ERR(s3c_nand.clk)) {
|
|
dev_err(&pdev->dev, "failed to get clock");
|
|
err = -ENOENT;
|
|
goto exit_error;
|
|
}
|
|
|
|
clk_enable(s3c_nand.clk);
|
|
|
|
/* allocate and map the resource */
|
|
|
|
/* currently we assume we have the one resource */
|
|
res = pdev->resource;
|
|
size = res->end - res->start + 1;
|
|
|
|
s3c_nand.area = request_mem_region(res->start, size, pdev->name);
|
|
|
|
if (s3c_nand.area == NULL) {
|
|
dev_err(&pdev->dev, "cannot reserve register region\n");
|
|
err = -ENOENT;
|
|
goto exit_error;
|
|
}
|
|
|
|
s3c_nand.device = &pdev->dev;
|
|
s3c_nand.regs = ioremap(res->start, size);
|
|
//info->cpu_type = cpu_type;
|
|
|
|
if (s3c_nand.regs == NULL) {
|
|
dev_err(&pdev->dev, "cannot reserve register region\n");
|
|
err = -EIO;
|
|
goto exit_error;
|
|
}
|
|
|
|
/* allocate memory for MTD device structure and private data */
|
|
s3c_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
|
|
|
|
if (!s3c_mtd) {
|
|
printk("Unable to allocate NAND MTD dev structure.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Get pointer to private data */
|
|
nand = (struct nand_chip *) (&s3c_mtd[1]);
|
|
|
|
/* Initialize structures */
|
|
memset((char *) s3c_mtd, 0, sizeof(struct mtd_info));
|
|
memset((char *) nand, 0, sizeof(struct nand_chip));
|
|
|
|
/* Link the private data with the MTD structure */
|
|
s3c_mtd->priv = nand;
|
|
|
|
for (i = 0; i < plat_info->chip_nr; i++) {
|
|
nand->IO_ADDR_R = (char *)(s3c_nand.regs+S3C2440_NFDATA);
|
|
nand->IO_ADDR_W = (char *)(s3c_nand.regs+S3C2440_NFDATA);
|
|
nand->cmd_ctrl = s3c_nand_hwcontrol;
|
|
nand->dev_ready = s3c_nand_device_ready;
|
|
nand->scan_bbt = s3c_nand_scan_bbt;
|
|
nand->options = 0;
|
|
|
|
#if defined(CONFIG_MTD_NAND_S3C_CACHEDPROG)
|
|
nand->options |= NAND_CACHEPRG;
|
|
#endif
|
|
|
|
#if defined(CONFIG_MTD_NAND_S3C_FLASH_BBT)
|
|
nand->options |= NAND_USE_FLASH_BBT;
|
|
#else
|
|
nand->options |= NAND_SKIP_BBTSCAN;
|
|
#endif
|
|
|
|
#if defined(CONFIG_MTD_NAND_S3C_HWECC)
|
|
nand->ecc.mode = NAND_ECC_HW;
|
|
nand->ecc.hwctl = s3c_nand_enable_hwecc;
|
|
nand->ecc.calculate = s3c_nand_calculate_ecc;
|
|
nand->ecc.correct = s3c_nand_correct_data;
|
|
|
|
s3c_nand_hwcontrol(0, NAND_CMD_READID, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
|
|
s3c_nand_hwcontrol(0, 0x00, NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE);
|
|
s3c_nand_hwcontrol(0, 0x00, NAND_NCE | NAND_ALE);
|
|
s3c_nand_hwcontrol(0, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
|
|
s3c_nand_device_ready(0);
|
|
|
|
tmp = readb(nand->IO_ADDR_R); /* Maf. ID */
|
|
tmp = readb(nand->IO_ADDR_R); /* Device ID */
|
|
|
|
for (i = 0; nand_flash_ids[i].name != NULL; i++) {
|
|
if (tmp == nand_flash_ids[i].id) {
|
|
type = &nand_flash_ids[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!type) {
|
|
printk("Unknown NAND Device.\n");
|
|
goto exit_error;
|
|
}
|
|
|
|
nand->cellinfo = readb(nand->IO_ADDR_R); /* 3rd byte */
|
|
tmp = readb(nand->IO_ADDR_R); /* 4th byte */
|
|
|
|
if (!type->pagesize) {
|
|
if (((nand->cellinfo >> 2) & 0x3) == 0) {
|
|
nand_type = S3C_NAND_TYPE_SLC;
|
|
|
|
if ((1024 << (tmp & 0x3)) > 512) {
|
|
nand->ecc.size = 2048;
|
|
nand->ecc.bytes = 4;
|
|
nand->ecc.layout = &s3c_nand_oob_64;
|
|
} else {
|
|
nand->ecc.size = 512;
|
|
nand->ecc.bytes = 3;
|
|
nand->ecc.layout = &s3c_nand_oob_16;
|
|
}
|
|
} else {
|
|
nand_type = S3C_NAND_TYPE_MLC;
|
|
nand->options |= NAND_NO_SUBPAGE_WRITE; /* NOP = 1 if MLC */
|
|
nand->ecc.read_page = s3c_nand_read_page;
|
|
nand->ecc.write_page = s3c_nand_write_page;
|
|
nand->ecc.size = 512;
|
|
nand->ecc.bytes = 8; /* really 7 bytes */
|
|
nand->ecc.layout = &s3c_nand_oob_mlc_64;
|
|
}
|
|
} else {
|
|
/*Qisa Qube for EVT2 2k page*/
|
|
#ifdef CONFIG_QISDA_E600_EVT0
|
|
nand_type = S3C_NAND_TYPE_SLC;
|
|
nand->ecc.size = 512;
|
|
nand->cellinfo = 0;
|
|
nand->ecc.bytes = 3;
|
|
nand->ecc.layout = &s3c_nand_oob_16;
|
|
#else
|
|
nand_type = S3C_NAND_TYPE_SLC;
|
|
nand->ecc.size = 2048;
|
|
nand->cellinfo = 0;
|
|
nand->ecc.bytes = 4;
|
|
nand->ecc.layout = &s3c_nand_oob_64;
|
|
#endif
|
|
/*Qisa Qube for EVT2 2k page*/
|
|
}
|
|
|
|
printk("S3C NAND Driver is using hardware ECC.\n");
|
|
#else
|
|
nand->ecc.mode = NAND_ECC_SOFT;
|
|
printk("S3C NAND Driver is using software ECC.\n");
|
|
#endif
|
|
if (nand_scan(s3c_mtd, 1)) {
|
|
ret = -ENXIO;
|
|
goto exit_error;
|
|
}
|
|
|
|
/* Register the partitions */
|
|
add_mtd_partitions(s3c_mtd, partition_info, plat_info->mtd_part_nr);
|
|
}
|
|
|
|
pr_debug("initialized ok\n");
|
|
return 0;
|
|
|
|
exit_error:
|
|
kfree(s3c_mtd);
|
|
|
|
return ret;
|
|
}
|
|
|
|
|
|
/* PM Support */
|
|
#if defined(CONFIG_PM)
|
|
static int s3c_nand_suspend(struct platform_device *dev, pm_message_t pm)
|
|
{
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c_nand_resume(struct platform_device *dev)
|
|
{
|
|
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define s3c_nand_suspend NULL
|
|
#define s3c_nand_resume NULL
|
|
#endif
|
|
|
|
/* device management functions */
|
|
static int s3c_nand_remove(struct platform_device *dev)
|
|
{
|
|
platform_set_drvdata(dev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver s3c_nand_driver = {
|
|
.probe = s3c_nand_probe,
|
|
.remove = s3c_nand_remove,
|
|
.suspend = s3c_nand_suspend,
|
|
.resume = s3c_nand_resume,
|
|
.driver = {
|
|
.name = "s3c-nand",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init s3c_nand_init(void)
|
|
{
|
|
printk("S3C NAND Driver, (c) 2007 Samsung Electronics\n");
|
|
return platform_driver_register(&s3c_nand_driver);
|
|
}
|
|
|
|
static void __exit s3c_nand_exit(void)
|
|
{
|
|
platform_driver_unregister(&s3c_nand_driver);
|
|
}
|
|
|
|
module_init(s3c_nand_init);
|
|
module_exit(s3c_nand_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Jinsung Yang <jsgood.yang@samsung.com>");
|
|
MODULE_DESCRIPTION("S3C MTD NAND driver");
|