221 lines
8.2 KiB
C
221 lines
8.2 KiB
C
/* linux/include/asm-arm/arch-s3c2410/regs-gpioj.h
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*
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* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2440 GPIO J register definitions
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*/
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#ifndef __ASM_ARCH_REGS_GPIOJ_H
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#define __ASM_ARCH_REGS_GPIOJ_H "gpioj"
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/* Port J consists of 13 GPIO/Camera pins
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*
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* GPJCON has 2 bits for each of the input pins on port F
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* 00 = 0 input, 1 output, 2 Camera
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*
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* pull up works like all other ports.
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*/
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#define S3C2440_GPJCON S3C2410_GPIOREG(0xd0)
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#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4)
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#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8)
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#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
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#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
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#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
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#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
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#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 0)
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#define S3C2440_GPJ0_INP (0x00 << 0)
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#define S3C2440_GPJ0_OUTP (0x01 << 0)
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#define S3C2440_GPJ0_CAMDATA0 (0x02 << 0)
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#define S3C2440_GPJ1 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 1)
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#define S3C2440_GPJ1_INP (0x00 << 2)
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#define S3C2440_GPJ1_OUTP (0x01 << 2)
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#define S3C2440_GPJ1_CAMDATA1 (0x02 << 2)
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#define S3C2440_GPJ2 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 2)
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#define S3C2440_GPJ2_INP (0x00 << 4)
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#define S3C2440_GPJ2_OUTP (0x01 << 4)
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#define S3C2440_GPJ2_CAMDATA2 (0x02 << 4)
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#define S3C2440_GPJ3 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 3)
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#define S3C2440_GPJ3_INP (0x00 << 6)
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#define S3C2440_GPJ3_OUTP (0x01 << 6)
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#define S3C2440_GPJ3_CAMDATA3 (0x02 << 6)
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#define S3C2440_GPJ4 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 4)
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#define S3C2440_GPJ4_INP (0x00 << 8)
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#define S3C2440_GPJ4_OUTP (0x01 << 8)
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#define S3C2440_GPJ4_CAMDATA4 (0x02 << 8)
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#define S3C2440_GPJ5 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 5)
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#define S3C2440_GPJ5_INP (0x00 << 10)
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#define S3C2440_GPJ5_OUTP (0x01 << 10)
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#define S3C2440_GPJ5_CAMDATA5 (0x02 << 10)
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#define S3C2440_GPJ6 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 6)
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#define S3C2440_GPJ6_INP (0x00 << 12)
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#define S3C2440_GPJ6_OUTP (0x01 << 12)
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#define S3C2440_GPJ6_CAMDATA6 (0x02 << 12)
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#define S3C2440_GPJ7 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 7)
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#define S3C2440_GPJ7_INP (0x00 << 14)
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#define S3C2440_GPJ7_OUTP (0x01 << 14)
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#define S3C2440_GPJ7_CAMDATA7 (0x02 << 14)
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#define S3C2440_GPJ8 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 8)
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#define S3C2440_GPJ8_INP (0x00 << 16)
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#define S3C2440_GPJ8_OUTP (0x01 << 16)
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#define S3C2440_GPJ8_CAMPCLK (0x02 << 16)
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#define S3C2440_GPJ9 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 9)
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#define S3C2440_GPJ9_INP (0x00 << 18)
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#define S3C2440_GPJ9_OUTP (0x01 << 18)
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#define S3C2440_GPJ9_CAMVSYNC (0x02 << 18)
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#define S3C2440_GPJ10 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 10)
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#define S3C2440_GPJ10_INP (0x00 << 20)
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#define S3C2440_GPJ10_OUTP (0x01 << 20)
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#define S3C2440_GPJ10_CAMHREF (0x02 << 20)
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#define S3C2440_GPJ11 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 11)
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#define S3C2440_GPJ11_INP (0x00 << 22)
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#define S3C2440_GPJ11_OUTP (0x01 << 22)
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#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
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#define S3C2440_GPJ12 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 12)
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#define S3C2440_GPJ12_INP (0x00 << 24)
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#define S3C2440_GPJ12_OUTP (0x01 << 24)
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#define S3C2440_GPJ12_CAMRESET (0x02 << 24)
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#define S3C2443_GPJ13 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 13)
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#define S3C2443_GPJ13_INP (0x00 << 26)
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#define S3C2443_GPJ13_OUTP (0x01 << 26)
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#define S3C2443_GPJ13_SD0LED (0x02 << 26)
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#define S3C2450_GPJ13_I2S1_LRCK (0x03 << 26)
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#define S3C2450_GPJ13_SD1LED (0x02 << 26)
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#define S3C2443_GPJ14 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 14)
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#define S3C2443_GPJ14_INP (0x00 << 28)
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#define S3C2443_GPJ14_OUTP (0x01 << 28)
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#define S3C2443_GPJ14_nSD0CD (0x02 << 28)
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#define S3C2450_GPJ14_nSD1CD (0x02 << 28)
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#define S3C2443_GPJ15 S3C2410_GPIONO(S3C2410_GPIO_BANKJ, 15)
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#define S3C2443_GPJ15_INP (0x00 << 30)
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#define S3C2443_GPJ15_OUTP (0x01 << 30)
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#define S3C2443_GPJ15_nSD0WP (0x02 << 30)
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#define S3C2450_GPJ15_nSD1WP (0x02 << 30)
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#define S3C2443_GPJDN S3C2410_GPIOREG(0xd8)
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/* Port L consists of 14 GPIO
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*
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* GPLCON has 2 bits for each of the input pins on port K
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* 00 = 0 input, 1 output, 2 SD
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*
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* pull down works like all other ports.
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*/
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#define S3C2443_GPLCON S3C2410_GPIOREG(0xf0)
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#define S3C2443_GPLDAT S3C2410_GPIOREG(0xf4)
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#define S3C2443_GPLUDP S3C2410_GPIOREG(0xf8)
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#define S3C2443_GPL0 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 0)
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#define S3C3443_GPL0_INP (0x00 << 0)
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#define S3C2443_GPL0_OUTP (0x01 << 0)
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#define S3C2443_GPL0_SD0DAT0 (0x02 << 0)
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#define S3C2450_GPL0_SD1DAT0 (0x02 << 0)
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#define S3C2443_GPL1 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 1)
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#define S3C2443_GPL1_INP (0x00 << 2)
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#define S3C2443_GPL1_OUTP (0x01 << 2)
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#define S3C2443_GPL1_SD0DAT1 (0x02 << 2)
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#define S3C2450_GPL1_SD1DAT1 (0x02 << 2)
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#define S3C2443_GPL2 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 2)
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#define S3C2443_GPL2_INP (0x00 << 4)
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#define S3C2443_GPL2_OUTP (0x01 << 4)
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#define S3C2443_GPL2_SD0DAT2 (0x02 << 4)
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#define S3C2450_GPL2_SD1DAT2 (0x02 << 4)
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#define S3C2443_GPL3 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 3)
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#define S3C2443_GPL3_INP (0x00 << 6)
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#define S3C2443_GPL3_OUTP (0x01 << 6)
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#define S3C2443_GPL3_SD0DAT3 (0x02 << 6)
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#define S3C2450_GPL3_SD1DAT3 (0x02 << 6)
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#define S3C2443_GPL4 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 4)
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#define S3C2443_GPL4_INP (0x00 << 8)
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#define S3C2443_GPL4_OUTP (0x01 << 8)
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#define S3C2443_GPL4_SD0DAT4 (0x02 << 8)
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#define S3C2450_GPL4_SD1DAT4 (0x02 << 8)
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#define S3C2443_GPL5 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 5)
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#define S3C2443_GPL5_INP (0x00 << 10)
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#define S3C2443_GPL5_OUTP (0x01 << 10)
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#define S3C2443_GPL5_SD0DAT5 (0x02 << 10)
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#define S3C2450_GPL5_SD1DAT5 (0x02 << 10)
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#define S3C2443_GPL6 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 6)
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#define S3C2443_GPL6_INP (0x00 << 12)
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#define S3C2443_GPL6_OUTP (0x01 << 12)
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#define S3C2443_GPL6_SD0DAT6 (0x02 << 12)
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#define S3C2450_GPL6_SD1DAT6 (0x02 << 12)
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#define S3C2443_GPL7 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 7)
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#define S3C2443_GPL7_INP (0x00 << 14)
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#define S3C2443_GPL7_OUTP (0x01 << 14)
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#define S3C2443_GPL7_SD0DAT7 (0x02 << 14)
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#define S3C2450_GPL7_SD1DAT7 (0x02 << 14)
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#define S3C2443_GPL8 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 8)
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#define S3C2443_GPL8_INP (0x00 << 16)
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#define S3C2443_GPL8_OUTP (0x01 << 16)
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#define S3C2443_GPL8_SD0CMD (0x02 << 16)
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#define S3C2450_GPL8_SD1CMD (0x02 << 16)
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#define S3C2443_GPL9 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 9)
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#define S3C2443_GPL9_INP (0x00 << 18)
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#define S3C2443_GPL9_OUTP (0x01 << 18)
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#define S3C2443_GPL9_SD0CLK (0x02 << 18)
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#define S3C2450_GPL9_SD1CLK (0x02 << 18)
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#define S3C2443_GPL10 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 10)
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#define S3C2443_GPL10_INP (0x00 << 20)
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#define S3C2443_GPL10_OUTP (0x01 << 20)
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#define S3C2443_GPL10_SPICLK1 (00x2 << 20)
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#define S3C2443_GPL11 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 11)
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#define S3C2443_GPL11_INP (0x00 << 22)
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#define S3C2443_GPL11_OUTP (0x01 << 22)
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#define S3C2443_GPL11_SPIMOSI1 (0x02 << 22)
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#define S3C2443_GPL12 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 12)
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#define S3C2443_GPL12_INP (0x00 << 24)
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#define S3C2443_GPL12_OUTP (0x01 << 24)
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#define S3C2443_GPL12_SPIMISO1 (0x02 << 24)
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#define S3C2443_GPL13 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 13)
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#define S3C2443_GPL13_INP (00x0 << 26)
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#define S3C2443_GPL13_OUTP (0x01 << 26)
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#define S3C2443_GPL13_nSS0 (0x02 << 26)
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#define S3C2443_GPL14 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 14)
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#define S3C2443_GPL14_INP (0x00 << 28)
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#define S3C2443_GPL14_OUTP (0x01 << 28)
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#define S3C2443_GPL14_nSS1 (0x02 << 28)
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#endif /* __ASM_ARCH_REGS_GPIOJ_H */
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