114 lines
3.1 KiB
C
114 lines
3.1 KiB
C
/* ------------------------------------------------------------------------- */
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/* */
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/* spi-s3c6400.h - definitions of s3c6400 specific spi interface */
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/* */
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/* ------------------------------------------------------------------------- */
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/* Copyright (C) 2006 Samsung Electronics Co. ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* ------------------------------------------------------------------------- */
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#ifndef _S3C2443_SPI_H
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#define _S3C2443_SPI_H
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#include <asm/dma.h>
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#include <asm/arch/dma.h>
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#define S3C_DCON_HANDSHAKE (1<<31)
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#define S3C_DCON_SYNC_PCLK (0<<30)
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//#define SPI_CHANNEL 1
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#if(SPI_CHANNEL==0)
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/* SPI CHANNEL 0 */
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#define S3C_SPI_TX_DATA_REG 0x52000018 //SPI TX data
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#define S3C_SPI_RX_DATA_REG 0x5200001C //SPI RX data
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#else
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/* SPI CHANNEL 1 */
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#define S3C_SPI_TX_DATA_REG 0x59000018 //SPI TX data
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#define S3C_SPI_RX_DATA_REG 0x5900001C //SPI RX data
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#endif
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/* DMA channel to be used for the SPI interface. */
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#define S3C_SPI_DMA 0
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/* DMA transfer unit (byte). */
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#define S3C_DMA_XFER_BYTE 1
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#define S3C_DMA_XFER_WORD 4
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/* DMA configuration setup byte. */
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#define S3C_DCON_SPI1 (S3C_DCON_HANDSHAKE | S3C_DCON_SYNC_PCLK)
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/* DMA hardware configuration mode (DISRCC register). */
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#define S3C_SPI1_DMA_HWCFG 3
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#define S3C_SPI_DMA_HWCFG 3
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#define DMA_BUFFER_SIZE 1500
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/* spi controller state */
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int req_dma_flag = 1;
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enum s3c_spi_state {
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STATE_IDLE,
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STATE_XFER_TX,
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STATE_XFER_RX,
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STATE_STOP
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};
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/* vivek, 2009-05-14 11:01 Notes: define clients for dma read and write channels*/
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//static struct s3c2410_dma_client s3c2443spi_dma_client = {
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// .name = "s3c2443-spi-dma",
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//};
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static struct s3c2410_dma_client s3c2443spi_dma_clientw = {
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.name = "s3c2443-spi-dmaw",
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};
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static struct s3c2410_dma_client s3c2443spi_dma_clientr = {
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.name = "s3c2443-spi-dmar",
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};
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struct s3c_spi {
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spinlock_t lock;
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struct semaphore sem;
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int nr;
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int dma;
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/* vivek, 2009-05-14 10:45 Notes: define dmar and dmaw for both write and read channels*/
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int dmar;
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int dmaw;
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u_int subchannel;/* user fragment index */
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dma_addr_t dmabuf_addr;
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struct spi_msg *msg;
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unsigned int msg_num;
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unsigned int msg_idx;
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unsigned int msg_ptr;
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unsigned int msg_rd_ptr;
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enum s3c_spi_state state;
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void __iomem *regs;
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struct clk *clk;
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struct device *dev;
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struct resource *irq;
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struct resource *ioarea;
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struct spi_dev spidev;
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/* GeorgeKuo: */
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struct completion comp;
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};
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#endif /* _S3C6400_SPI_H */
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