249 lines
12 KiB
C
249 lines
12 KiB
C
/* linux/include/asm-arm/arch-s3c2410/regs-udc.h
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*
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* Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
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*
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* This include file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
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#define __ASM_ARCH_REGS_USB_OTG_HS_H
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/* USB2.0 OTG Controller register */
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#define S3C_USBOTG_PHYREG(x) ((x) + S3C24XX_VA_OTGSFR)
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#define S3C_USBOTG_PHYPWR S3C_USBOTG_PHYREG(0x0)
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#define S3C_USBOTG_PHYCLK S3C_USBOTG_PHYREG(0x4)
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#define S3C_USBOTG_RSTCON S3C_USBOTG_PHYREG(0x8)
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/* USB2.0 OTG Controller register */
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#define S3C_USBOTGREG(x) ((x) + S3C24XX_VA_OTG)
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//==============================================================================================
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// Core Global Registers
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#define S3C_UDC_OTG_GOTGCTL S3C_USBOTGREG(0x000) // OTG Control & Status
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#define S3C_UDC_OTG_GOTGINT S3C_USBOTGREG(0x004) // OTG Interrupt
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#define S3C_UDC_OTG_GAHBCFG S3C_USBOTGREG(0x008) // Core AHB Configuration
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#define S3C_UDC_OTG_GUSBCFG S3C_USBOTGREG(0x00C) // Core USB Configuration
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#define S3C_UDC_OTG_GRSTCTL S3C_USBOTGREG(0x010) // Core Reset
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#define S3C_UDC_OTG_GINTSTS S3C_USBOTGREG(0x014) // Core Interrupt
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#define S3C_UDC_OTG_GINTMSK S3C_USBOTGREG(0x018) // Core Interrupt Mask
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#define S3C_UDC_OTG_GRXSTSR S3C_USBOTGREG(0x01C) // Receive Status Debug Read/Status Read
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#define S3C_UDC_OTG_GRXSTSP S3C_USBOTGREG(0x020) // Receive Status Debug Pop/Status Pop
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#define S3C_UDC_OTG_GRXFSIZ S3C_USBOTGREG(0x024) // Receive FIFO Size
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#define S3C_UDC_OTG_GNPTXFSIZ S3C_USBOTGREG(0x028) // Non-Periodic Transmit FIFO Size
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#define S3C_UDC_OTG_GNPTXSTS S3C_USBOTGREG(0x02C) // Non-Periodic Transmit FIFO/Queue Status
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#define S3C_UDC_OTG_HPTXFSIZ S3C_USBOTGREG(0x100) // Host Periodic Transmit FIFO Size
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#define S3C_UDC_OTG_DPTXFSIZ1 S3C_USBOTGREG(0x104) // Device Periodic Transmit FIFO-1 Size
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#define S3C_UDC_OTG_DPTXFSIZ2 S3C_USBOTGREG(0x108) // Device Periodic Transmit FIFO-2 Size
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#define S3C_UDC_OTG_DPTXFSIZ3 S3C_USBOTGREG(0x10C) // Device Periodic Transmit FIFO-3 Size
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#define S3C_UDC_OTG_DPTXFSIZ4 S3C_USBOTGREG(0x110) // Device Periodic Transmit FIFO-4 Size
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#define S3C_UDC_OTG_DPTXFSIZ5 S3C_USBOTGREG(0x114) // Device Periodic Transmit FIFO-5 Size
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#define S3C_UDC_OTG_DPTXFSIZ6 S3C_USBOTGREG(0x118) // Device Periodic Transmit FIFO-6 Size
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#define S3C_UDC_OTG_DPTXFSIZ7 S3C_USBOTGREG(0x11C) // Device Periodic Transmit FIFO-7 Size
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#define S3C_UDC_OTG_DPTXFSIZ8 S3C_USBOTGREG(0x120) // Device Periodic Transmit FIFO-8 Size
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#define S3C_UDC_OTG_DPTXFSIZ9 S3C_USBOTGREG(0x124) // Device Periodic Transmit FIFO-9 Size
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#define S3C_UDC_OTG_DPTXFSIZ10 S3C_USBOTGREG(0x128) // Device Periodic Transmit FIFO-10 Size
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#define S3C_UDC_OTG_DPTXFSIZ11 S3C_USBOTGREG(0x12C) // Device Periodic Transmit FIFO-11 Size
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#define S3C_UDC_OTG_DPTXFSIZ12 S3C_USBOTGREG(0x130) // Device Periodic Transmit FIFO-12 Size
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#define S3C_UDC_OTG_DPTXFSIZ13 S3C_USBOTGREG(0x134) // Device Periodic Transmit FIFO-13 Size
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#define S3C_UDC_OTG_DPTXFSIZ14 S3C_USBOTGREG(0x138) // Device Periodic Transmit FIFO-14 Size
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#define S3C_UDC_OTG_DPTXFSIZ15 S3C_USBOTGREG(0x13C) // Device Periodic Transmit FIFO-15 Size
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//==============================================================================================
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// Host Mode Registers
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//------------------------------------------------
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// Host Global Registers
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#define S3C_UDC_OTG_HCFG S3C_USBOTGREG(0x400) // Host Configuration
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#define S3C_UDC_OTG_HFIR S3C_USBOTGREG(0x404) // Host Frame Interval
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#define S3C_UDC_OTG_HFNUM S3C_USBOTGREG(0x408) // Host Frame Number/Frame Time Remaining
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#define S3C_UDC_OTG_HPTXSTS S3C_USBOTGREG(0x410) // Host Periodic Transmit FIFO/Queue Status
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#define S3C_UDC_OTG_HAINT S3C_USBOTGREG(0x414) // Host All Channels Interrupt
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#define S3C_UDC_OTG_HAINTMSK S3C_USBOTGREG(0x418) // Host All Channels Interrupt Mask
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//------------------------------------------------
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// Host Port Control & Status Registers
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#define S3C_UDC_OTG_HPRT S3C_USBOTGREG(0x440) // Host Port Control & Status
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//------------------------------------------------
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// Host Channel-Specific Registers
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#define S3C_UDC_OTG_HCCHAR0 S3C_USBOTGREG(0x500) // Host Channel-0 Characteristics
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#define S3C_UDC_OTG_HCSPLT0 S3C_USBOTGREG(0x504) // Host Channel-0 Split Control
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#define S3C_UDC_OTG_HCINT0 S3C_USBOTGREG(0x508) // Host Channel-0 Interrupt
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#define S3C_UDC_OTG_HCINTMSK0 S3C_USBOTGREG(0x50C) // Host Channel-0 Interrupt Mask
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#define S3C_UDC_OTG_HCTSIZ0 S3C_USBOTGREG(0x510) // Host Channel-0 Transfer Size
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#define S3C_UDC_OTG_HCDMA0 S3C_USBOTGREG(0x514) // Host Channel-0 DMA Address
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//==============================================================================================
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// Device Mode Registers
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//------------------------------------------------
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// Device Global Registers
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#define S3C_UDC_OTG_DCFG S3C_USBOTGREG(0x800) // Device Configuration
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#define S3C_UDC_OTG_DCTL S3C_USBOTGREG(0x804) // Device Control
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#define S3C_UDC_OTG_DSTS S3C_USBOTGREG(0x808) // Device Status
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#define S3C_UDC_OTG_DIEPMSK S3C_USBOTGREG(0x810) // Device IN Endpoint Common Interrupt Mask
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#define S3C_UDC_OTG_DOEPMSK S3C_USBOTGREG(0x814) // Device OUT Endpoint Common Interrupt Mask
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#define S3C_UDC_OTG_DAINT S3C_USBOTGREG(0x818) // Device All Endpoints Interrupt
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#define S3C_UDC_OTG_DAINTMSK S3C_USBOTGREG(0x81C) // Device All Endpoints Interrupt Mask
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#define S3C_UDC_OTG_DTKNQR1 S3C_USBOTGREG(0x820) // Device IN Token Sequence Learning Queue Read 1
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#define S3C_UDC_OTG_DTKNQR2 S3C_USBOTGREG(0x824) // Device IN Token Sequence Learning Queue Read 2
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#define S3C_UDC_OTG_DVBUSDIS S3C_USBOTGREG(0x828) // Device VBUS Discharge Time
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#define S3C_UDC_OTG_DVBUSPULSE S3C_USBOTGREG(0x82C) // Device VBUS Pulsing Time
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#define S3C_UDC_OTG_DTKNQR3 S3C_USBOTGREG(0x830) // Device IN Token Sequence Learning Queue Read 3
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#define S3C_UDC_OTG_DTKNQR4 S3C_USBOTGREG(0x834) // Device IN Token Sequence Learning Queue Read 4
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//------------------------------------------------
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// Device Logical IN Endpoint-Specific Registers
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#define S3C_UDC_OTG_DIEPCTL0 S3C_USBOTGREG(0x900) // Device IN Endpoint 0 Control
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#define S3C_UDC_OTG_DIEPINT0 S3C_USBOTGREG(0x908) // Device IN Endpoint 0 Interrupt
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#define S3C_UDC_OTG_DIEPTSIZ0 S3C_USBOTGREG(0x910) // Device IN Endpoint 0 Transfer Size
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#define S3C_UDC_OTG_DIEPDMA0 S3C_USBOTGREG(0x914) // Device IN Endpoint 0 DMA Address
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#define S3C_UDC_OTG_DIEPCTL2 S3C_USBOTGREG(0x940) // Device IN Endpoint 2 Control
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#define S3C_UDC_OTG_DIEPINT2 S3C_USBOTGREG(0x948) // Device IN Endpoint 2 Interrupt
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#define S3C_UDC_OTG_DIEPTSIZ2 S3C_USBOTGREG(0x950) // Device IN Endpoint 2 Transfer Size
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#define S3C_UDC_OTG_DIEPDMA2 S3C_USBOTGREG(0x954) // Device IN Endpoint 2 DMA Address
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#define S3C_UDC_OTG_DIEPCTL3 S3C_USBOTGREG(0x960) // Device IN Endpoint 3 Control
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#define S3C_UDC_OTG_DIEPINT3 S3C_USBOTGREG(0x968) // Device IN Endpoint 3 Interrupt
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#define S3C_UDC_OTG_DIEPTSIZ3 S3C_USBOTGREG(0x970) // Device IN Endpoint 3 Transfer Size
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#define S3C_UDC_OTG_DIEPDMA3 S3C_USBOTGREG(0x974) // Device IN Endpoint 3 DMA Address
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//------------------------------------------------
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// Device Logical OUT Endpoint-Specific Registers
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#define S3C_UDC_OTG_DOEPCTL0 S3C_USBOTGREG(0xB00) // Device OUT Endpoint 0 Control
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#define S3C_UDC_OTG_DOEPINT0 S3C_USBOTGREG(0xB08) // Device OUT Endpoint 0 Interrupt
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#define S3C_UDC_OTG_DOEPTSIZ0 S3C_USBOTGREG(0xB10) // Device OUT Endpoint 0 Transfer Size
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#define S3C_UDC_OTG_DOEPDMA0 S3C_USBOTGREG(0xB14) // Device OUT Endpoint 0 DMA Address
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#define S3C_UDC_OTG_DOEPCTL1 S3C_USBOTGREG(0xB20) // Device OUT Endpoint 1 Control
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#define S3C_UDC_OTG_DOEPINT1 S3C_USBOTGREG(0xB28) // Device OUT Endpoint 1 Interrupt
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#define S3C_UDC_OTG_DOEPTSIZ1 S3C_USBOTGREG(0xB30) // Device OUT Endpoint 1 Transfer Size
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#define S3C_UDC_OTG_DOEPDMA1 S3C_USBOTGREG(0xB34) // Device OUT Endpoint 1 DMA Address
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//------------------------------------------------
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// Endpoint FIFO address
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#define S3C_UDC_OTG_EP0_FIFO S3C_USBOTGREG(0x1000)
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#define S3C_UDC_OTG_EP1_FIFO S3C_USBOTGREG(0x2000)
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#define S3C_UDC_OTG_EP2_FIFO S3C_USBOTGREG(0x3000)
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#define S3C_UDC_OTG_EP3_FIFO S3C_USBOTGREG(0x4000)
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#define S3C_UDC_OTG_EP4_FIFO S3C_USBOTGREG(0x5000)
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#define S3C_UDC_OTG_EP5_FIFO S3C_USBOTGREG(0x6000)
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#define S3C_UDC_OTG_EP6_FIFO S3C_USBOTGREG(0x7000)
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#define S3C_UDC_OTG_EP7_FIFO S3C_USBOTGREG(0x8000)
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#define S3C_UDC_OTG_EP8_FIFO S3C_USBOTGREG(0x9000)
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//=====================================================================
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//definitions related to CSR setting
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// S3C_UDC_OTG_GOTGCTL
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#define B_SESSION_VALID (0x1<<19)
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#define A_SESSION_VALID (0x1<<18)
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// S3C_UDC_OTG_GAHBCFG
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#define PTXFE_HALF (0<<8)
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#define PTXFE_ZERO (1<<8)
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#define NPTXFE_HALF (0<<7)
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#define NPTXFE_ZERO (1<<7)
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#define MODE_SLAVE (0<<5)
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#define MODE_DMA (1<<5)
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#define BURST_SINGLE (0<<1)
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#define BURST_INCR (1<<1)
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#define BURST_INCR4 (3<<1)
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#define BURST_INCR8 (5<<1)
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#define BURST_INCR16 (7<<1)
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#define GBL_INT_UNMASK (1<<0)
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#define GBL_INT_MASK (0<<0)
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// S3C_UDC_OTG_GRSTCTL
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#define AHB_MASTER_IDLE (1u<<31)
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#define CORE_SOFT_RESET (0x1<<0)
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// S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register
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#define INT_RESUME (1u<<31)
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#define INT_DISCONN (0x1<<29)
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#define INT_CONN_ID_STS_CNG (0x1<<28)
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#define INT_OUT_EP (0x1<<19)
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#define INT_IN_EP (0x1<<18)
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#define INT_ENUMDONE (0x1<<13)
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#define INT_RESET (0x1<<12)
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#define INT_SUSPEND (0x1<<11)
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#define INT_EARLY_SUSPEND (0x1<<10)
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#define INT_TX_FIFO_EMPTY (0x1<<5)
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#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
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#define INT_SOF (0x1<<3)
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#define INT_DEV_MODE (0x0<<0)
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#define INT_HOST_MODE (0x1<<1)
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#define FULL_SPEED_CONTROL_PKT_SIZE 8
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#define FULL_SPEED_BULK_PKT_SIZE 64
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#define HIGH_SPEED_CONTROL_PKT_SIZE 64
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#define HIGH_SPEED_BULK_PKT_SIZE 512
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#define RX_FIFO_SIZE 2048
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#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE
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#define NPTX_FIFO_SIZE 2048
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#define PTX_FIFO_SIZE 2048
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// Enumeration speed
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#define USB_HIGH_30_60MHZ (0x0<<1)
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#define USB_FULL_30_60MHZ (0x1<<1)
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#define USB_LOW_6MHZ (0x2<<1)
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#define USB_FULL_48MHZ (0x3<<1)
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// S3C_UDC_OTG_GRXSTSP STATUS
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#define OUT_PKT_RECEIVED (0x2<<17)
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#define OUT_TRANSFER_COMPLELTED (0x3<<17)
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#define SETUP_TRANSACTION_COMPLETED (0x4<<17)
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#define SETUP_PKT_RECEIVED (0x6<<17)
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// S3C_UDC_OTG_DCTL device control register
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#define NORMAL_OPERATION (0x1<<0)
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#define SOFT_DISCONNECT (0x1<<1)
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// S3C_UDC_OTG_DAINT device all endpoint interrupt register
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#define S3C_UDC_INT_IN_EP0 (0x1<<0)
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#define S3C_UDC_INT_IN_EP2 (0x1<<2)
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#define S3C_UDC_INT_IN_EP3 (0x1<<3)
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#define S3C_UDC_INT_OUT_EP0 (0x1<<16)
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#define S3C_UDC_INT_OUT_EP1 (0x1<<17)
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#define S3C_UDC_INT_OUT_EP4 (0x1<<20)
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// S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register
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#define DEPCTL_EPENA (0x1<<31)
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#define DEPCTL_EPDIS (0x1<<30)
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#define DEPCTL_SNAK (0x1<<27)
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#define DEPCTL_CNAK (0x1<<26)
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#define DEPCTL_CTRL_TYPE (0x0<<18)
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#define DEPCTL_ISO_TYPE (0x1<<18)
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#define DEPCTL_BULK_TYPE (0x2<<18)
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#define DEPCTL_INTR_TYPE (0x3<<18)
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#define DEPCTL_USBACTEP (0x1<<15)
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#define DEPCTL0_MPS_64 (0x0<<0)
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#define DEPCTL0_MPS_32 (0x1<<0)
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#define DEPCTL0_MPS_16 (0x2<<0)
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#define DEPCTL0_MPS_8 (0x3<<0)
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// S3C_UDC_OTG_DIEPCTLn/DOEPCTLn device control IN/OUT endpoint n control register
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// S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register
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// S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register
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#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
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#define INTKN_TXFEMP (0x1<<4)
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#define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
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#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
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#define AHB_ERROR (0x1<<2)
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#define TRANSFER_DONE (0x1<<0)
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#endif
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