191 lines
5.2 KiB
C
191 lines
5.2 KiB
C
/* linux/arch/arm/mach-s3c2450/pm.c
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* http://armlinux.simtec.co.uk/.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/sysdev.h>
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#include <linux/platform_device.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/arch/regs-mem.h>
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#include <asm/arch/regs-power.h>
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#include <asm/arch/regs-gpioj.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-irq.h>
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#include <asm/arch/regs-dsc.h>
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#include <asm/arch/regs-s3c2416-clock.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#include <asm/plat-s3c24xx/pm.h>
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#include <asm/plat-s3c24xx/s3c2450.h>
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#ifdef CONFIG_PM_CPU_MODE
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extern unsigned char pm_cpu_mode;
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#endif
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static void s3c2450_cpu_suspend(void)
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{
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//unsigned long tmp;
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/* USB Physical power */
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__raw_writel(__raw_readl(S3C2443_PHYPWR) | 0xf, S3C2443_PHYPWR);
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/* USB Suspend mode */
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__raw_writel(__raw_readl(S3C2410_MISCCR)|(1<<12)|(1<<13), S3C2410_MISCCR);
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__raw_writel(0xffffffff, S3C2410_INTMSK);
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__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
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__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
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__raw_writel(0xffffffff, S3C2410_EINTPEND);
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__raw_writel(0xffffffff, S3C2410_EINTMASK);
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__raw_writel(0xffffffff, S3C2410_SRCPND);
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__raw_writel(0xffffffff, S3C2410_INTPND);
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__raw_writel(0xff80, S3C2443_RSTCON);
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__raw_writel(0xffff, S3C2443_OSCSET);
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/* ack any outstanding external interrupts before we go to sleep */
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__raw_writel((0xffffffff & ~((1<<0) | (1<<3) | (1<<30))) , S3C2410_INTMSK);
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__raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
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__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
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__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
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__raw_writel( (1<<15), S3C2443_PWRCFG);
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#ifdef CONFIG_PM_CPU_MODE
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/* set our standby method to sleep */
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switch(pm_cpu_mode){
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case PM_CPU_DEVICE_MODE_SUSPEND:
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__raw_writel(0x2BED, S3C2443_PWRMODE);
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break;
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case PM_CPU_MODE_STOP:
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__raw_writel(((__raw_readl(S3C2443_PWRMODE) & ~(1<<16))| (1<<16)), S3C2443_PWRMODE);
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break;
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case PM_CPU_MODE_DEEP_STOP:
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__raw_writel(((__raw_readl(S3C2443_PWRCFG) & ~(1<<16))| (1<<16)), S3C2443_PWRCFG);
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__raw_writel(((__raw_readl(S3C2443_PWRMODE) & ~(1<<16))| (1<<16)), S3C2443_PWRMODE);
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break;
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case PM_CPU_MODE_IDLE:
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__raw_writel(((__raw_readl(S3C2443_PWRCFG) & ~(1<<17))| (1<<17)), S3C2443_PWRCFG);
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asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
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break;
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case PM_CPU_MODE_SLEEP:
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__raw_writel(0x2BED, S3C2443_PWRMODE);
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break;
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default:
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__raw_writel(0x2BED, S3C2443_PWRMODE);
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break;
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}
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#else
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__raw_writel(0x2BED, S3C2443_PWRMODE);
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#endif
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}
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static void s3c2450_pm_prepare(void)
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{
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int ret;
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/* set flag to wake up */
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__raw_writel(0x2BED, S3C2443_INFORM0);
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/* memory auto-detect configuration for u-boot side wake-up */
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ret = __raw_readl(S3C2410_BWSCON) & S3C2410_MEMCFG_MASK;
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if(ret == S3C2410_MEMCFG_MDDR)
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__raw_writel(0xDD, S3C2443_INFORM2); /* mDDR */
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else if(ret == S3C2410_MEMCFG_MSDR)
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__raw_writel(0xDA, S3C2443_INFORM2); /* mSDRAM */
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else if(ret == S3C2410_MEMCFG_DDR2)
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panic("DDR2 is not supported at u-boot");
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else
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panic("memory setup is not correct?");
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}
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static int s3c2450_pm_add(struct sys_device *sysdev)
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{
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pm_cpu_prep = s3c2450_pm_prepare;
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pm_cpu_sleep = s3c2450_cpu_suspend;
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return 0;
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}
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static struct sleep_save s3c2450_sleep[] = {
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// SAVE_ITEM(S3C2450_DSC0),
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// SAVE_ITEM(S3C2450_DSC1),
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// SAVE_ITEM(S3C2413_GPJDAT),
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// SAVE_ITEM(S2C2413_GPJCON),
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// SAVE_ITEM(S3C2413_GPJUP),
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/* save the PWRCFG to get back to original sleep method */
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// SAVE_ITEM(S3C2443_PWRMODE),
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/* save the sleep configuration anyway, just in case these
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* get damaged during wakeup */
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// SAVE_ITEM(S3C2450_GPBSLPCON),
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// SAVE_ITEM(S3C2450_GPCSLPCON),
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// SAVE_ITEM(S3C2450_GPDSLPCON),
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// SAVE_ITEM(S3C2450_GPESLPCON),
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// SAVE_ITEM(S3C2450_GPFSLPCON),
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// SAVE_ITEM(S3C2450_GPGSLPCON),
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// SAVE_ITEM(S3C2450_GPHSLPCON),
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// SAVE_ITEM(S3C2413_GPJSLPCON),
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};
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static int s3c2450_pm_suspend(struct sys_device *dev, pm_message_t state)
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{
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s3c2410_pm_do_save(s3c2450_sleep, ARRAY_SIZE(s3c2450_sleep));
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return 0;
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}
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static int s3c2450_pm_resume(struct sys_device *dev)
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{
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// unsigned long tmp;
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// tmp = __raw_readl(S3C2443_RSTCON);
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// tmp |= (1<<16);
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// __raw_writel(tmp, S3C2443_RSTCON);
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// __raw_writel(0, S3C2443_PWRMODE);
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__raw_writel(0x0, S3C2443_INFORM0);
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__raw_writel(0x0, S3C2443_INFORM2);
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s3c2410_pm_do_restore(s3c2450_sleep, ARRAY_SIZE(s3c2450_sleep));
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return 0;
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}
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static struct sysdev_driver s3c2450_pm_driver = {
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.add = s3c2450_pm_add,
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.suspend = s3c2450_pm_suspend,
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.resume = s3c2450_pm_resume,
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};
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static __init int s3c2450_pm_init(void)
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{
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return sysdev_driver_register(&s3c2416_sysclass, &s3c2450_pm_driver);
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}
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arch_initcall(s3c2450_pm_init);
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