162 lines
6.5 KiB
C
162 lines
6.5 KiB
C
/* linux/include/asm-arm/arch-s3c2410/regs-ac97.h
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*
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* Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2440 AC97 Controller
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*/
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#ifndef __ASM_ARCH_REGS_AC97_H
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#define __ASM_ARCH_REGS_AC97_H __FILE__
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#define S3C_AC97_GLBCTRL (0x00)
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#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22)
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#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21)
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#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20)
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#define S3C_AC97_GLBCTRL_MICINORIE (1<<19)
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#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18)
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#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17)
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#define S3C_AC97_GLBCTRL_MICINTIE (1<<16)
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#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12)
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#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12)
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#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12)
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#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12)
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#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10)
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#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10)
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#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10)
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#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10)
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#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8)
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#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8)
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#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8)
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#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8)
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#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3)
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#define S3C_AC97_GLBCTRL_ACLINKON (1<<2)
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#define S3C_AC97_GLBCTRL_WARMRESET (1<<1)
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#define S3C_AC97_GLBCTRL_COLDRESET (1<<0)
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#define S3C_AC97_GLBSTAT (0x04)
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#define S3C_AC97_GLBSTAT_CODECREADY (1<<22)
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#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21)
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#define S3C_AC97_GLBSTAT_PCMINORI (1<<20)
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#define S3C_AC97_GLBSTAT_MICINORI (1<<19)
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#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18)
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#define S3C_AC97_GLBSTAT_PCMINTI (1<<17)
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#define S3C_AC97_GLBSTAT_MICINTI (1<<16)
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#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0)
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#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0)
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#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0)
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#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0)
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#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0)
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#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0)
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#define S3C_AC97_CODEC_CMD (0x08)
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#define S3C_AC97_CODEC_CMD_READ (1<<23)
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#define S3C_AC97_STAT (0x0c)
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#define S3C_AC97_PCM_ADDR (0x10)
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#define S3C_AC97_PCM_DATA (0x18)
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#define S3C_AC97_MIC_DATA (0x1C)
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#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
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#include <asm/arch/bitfield.h>
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/*************************************************************
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AC-97 interface registers */
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#define AC97_CTL_BASE S3C24XX_VA_AC97
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#define S3C_AC97REG(x) ((x) + AC97_CTL_BASE)
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#define S3C_AC97REG_PHYS(x) ((x) + S3C24XX_PA_AC97)
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#define AC_GLBCTRL S3C_AC97REG(0x00) /* global control */
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#define AC_GLBSTAT S3C_AC97REG(0x04) /* global status */
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#define AC_CODEC_CMD S3C_AC97REG(0x08) /* codec command */
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#define AC_CODEC_STAT S3C_AC97REG(0x0c) /* codec status */
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#define AC_PCMADDR S3C_AC97REG(0x10) /* PCM out/in FIFO address */
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#define AC_MICADDR S3C_AC97REG(0x14) /* MIC in FIFO address */
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#define AC_PCMDATA S3C_AC97REG(0x18) /* PCM out/in FIFO data */
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#define AC_MICDATA S3C_AC97REG(0x1c) /* MIC in FIFO data */
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#define AC_CLRINT S3C_AC97REG(0x20) /* MIC in FIFO data */
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#define AC_PCMDATA_PHYS S3C_AC97REG_PHYS(0x18) /* PCM out/in FIFO data */
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#define AC_MICDATA_PHYS S3C_AC97REG_PHYS(0x1c) /* MIC in FIFO data */
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#define AC_GLBCTRL_RIE (1<<22) /* codec ready interrupt enable */
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#define AC_GLBCTRL_POUIE (1<<21) /* PCM out underrun interrupt enable */
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#define AC_GLBCTRL_PIOIE (1<<20) /* PCM in overrun interrupt enable */
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#define AC_GLBCTRL_MIOIE (1<<19) /* MIC in underrun interrupt enable */
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#define AC_GLBCTRL_POTIE (1<<18) /* PCM out threshold interrupt enable */
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#define AC_GLBCTRL_PITIE (1<<17) /* PCM in threshold interrupt enable */
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#define AC_GLBCTRL_MITIE (1<<16) /* MIC in threshold interrupt enable */
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#define fAC_GLBCTRL_POMODE Fld(2,12) /* PCM out transfer mode */
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#define AC_GLBCTRL_POMODE FMsk(fAC_GLBCTRL_POMODE)
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#define AC_GLBCTRL_POMODE_OFF FInsrt(0, fAC_GLBCTRL_POMODE) /* off */
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#define AC_GLBCTRL_POMODE_PIO FInsrt(1, fAC_GLBCTRL_POMODE) /* PIO */
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#define AC_GLBCTRL_POMODE_DMA FInsrt(2, fAC_GLBCTRL_POMODE) /* DMA */
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#define fAC_GLBCTRL_PIMODE Fld(2,10) /* PCM in transfer mode */
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#define AC_GLBCTRL_PIMODE FMsk(fAC_GLBCTRL_PIMODE)
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#define AC_GLBCTRL_PIMODE_OFF FInsrt(0, fAC_GLBCTRL_PIMODE) /* off */
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#define AC_GLBCTRL_PIMODE_PIO FInsrt(1, fAC_GLBCTRL_PIMODE) /* PIO */
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#define AC_GLBCTRL_PIMODE_DMA FInsrt(2, fAC_GLBCTRL_PIMODE) /* DMA */
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#define fAC_GLBCTRL_MIMODE Fld(2,8) /* MIC in transfer mode */
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#define AC_GLBCTRL_MIMODE FMsk(fAC_GLBCTRL_MIMODE)
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#define AC_GLBCTRL_MIMODE_OFF FInsrt(0, fAC_GLBCTRL_MIMODE) /* off */
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#define AC_GLBCTRL_MIMODE_PIO FInsrt(1, fAC_GLBCTRL_MIMODE) /* PIO */
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#define AC_GLBCTRL_MIMODE_DMA FInsrt(2, fAC_GLBCTRL_MIMODE) /* DMA */
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#define AC_GLBCTRL_TE (1<<3) /* Transfer data enable using AC-link */
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#define AC_GLBCTRL_AE (1<<2) /* AC-link on */
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#define AC_GLBCTRL_WARM (1<<1) /* warm reset */
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#define AC_GLBCTRL_COLD (1<<0) /* cold reset */
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#define AC_GLBSTAT_RI (1<<22) /* codec ready interrupt */
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#define AC_GLBSTAT_POUI (1<<21) /* PCM out underrun interrupt */
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#define AC_GLBSTAT_PIOI (1<<20) /* PCM in overrun interrupt */
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#define AC_GLBSTAT_MIOI (1<<19) /* MIC in overrun interrupt */
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#define AC_GLBSTAT_POTI (1<<18) /* PCM out threshold interrupt */
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#define AC_GLBSTAT_PITI (1<<17) /* PCM in threshold interrupt */
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#define AC_GLBSTAT_MITI (1<<16) /* MIC in threshold interrupt */
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#define fAC_GLBSTAT_CSTAT Fld(3,0) /* Controller main state */
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#define AC_GLBSTAT_CSTAT() FExtr(__raw_readl(AC_GLBSTAT), fAC_GLBSTAT_CSTAT)
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#define AC_CSTAT_IDLE (0)
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#define AC_CSTAT_INIT (1)
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#define AC_CSTAT_READY (2)
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#define AC_CSTAT_ACTIVE (3)
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#define AC_CSTAT_LP (4)
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#define AC_CSTAT_WARM (5)
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#define AC_CMD_R (1<<23) /* read enable - 0: command write, 1: status read */
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#define fAC_CMD_ADDR Fld(7, 16) /* codec command address */
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#define AC_CMD_ADDR(x) FInsrt((x), fAC_CMD_ADDR)
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#define fAC_CMD_DATA Fld(16, 0) /* codec command data */
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#define AC_CMD_DATA(x) FInsrt((x), fAC_CMD_DATA)
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#define fAC_STAT_ADDR Fld(7, 16) /* codec status address */
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#define AC_STAT_ADDR(x) FExtr((x), fAC_STAT_ADDR)
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#define fAC_STAT_DATA Fld(16, 0) /* codec status data */
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#define AC_STAT_DATA(x) FExtr((x), fAC_STAT_DATA)
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#define DMA_CH0 0
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#define DMA_CH1 1
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#define DMA_CH2 2
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#define DMA_CH3 3
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#define MODE_PLAY 1
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#define MODE_REC 0
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#define DMA_BUF_WR 1
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#define DMA_BUF_RD 0
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#endif
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#endif /* __ASM_ARCH_REGS_AC97_H */
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