317 lines
10 KiB
C
317 lines
10 KiB
C
/*
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* rt5627.h -- audio driver for RT5627/RT5628
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*
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* Copyright 2008 Realtek Microelectronics
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*
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* Author: flove <flove@realtek.com>
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*
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* Based on WM8753.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef _RT5627_H
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#define _RT5627_H
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#define RT5627_RESET 0X00 //RESET CODEC TO DEFAULT
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#define RT5627_SPK_OUT_VOL 0X02 //SPEAKER OUT VOLUME
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#define RT5627_HP_OUT_VOL 0X04 //HEADPHONE OUTPUT VOLUME
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#define RT5627_AUXIN_VOL 0X08 //AUXIN VOLUME
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#define RT5627_LINE_IN_VOL 0X0A //LINE IN VOLUME
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#define RT5627_STEREO_DAC_VOL 0X0C //STEREO DAC VOLUME
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#define RT5627_SOFT_VOL_CTRL_TIME 0X16 //SOFT DELAY VOLUME CONTROL TIME
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#define RT5627_OUTPUT_MIXER_CTRL 0X1C //OUTPUT MIXER CONTROL
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#define RT5627_AUDIO_DATA_CTRL 0X34 //STEREO AUDIO DATA CONTROL
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#define RT5627_DAC_CLK_CTRL 0X38 //STEREO DAC CLOCK CONTROL
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#define RT5627_PWR_MANAG_ADD1 0X3A //POWER MANAGMENT ADDITION 1
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#define RT5627_PWR_MANAG_ADD2 0X3C //POWER MANAGMENT ADDITION 2
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#define RT5627_PWR_MANAG_ADD3 0X3E //POWER MANAGMENT ADDITION 3
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#define RT5627_GEN_CTRL 0X40 //GENERAL PURPOSE CONTROL
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#define RT5627_GLOBAL_CLK_CTRL 0X42 //GLOBAL CLOCK CONTROL
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#define RT5627_PLL_CTRL 0X44 //PLL CONTROL
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#define RT5627_GPIO_PIN_CONFIG 0X48 //GPIO PIN CONFIG
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#define RT5627_GPIO_OUTPUT_PIN_CTRL 0X4A //GPIO CONTROL
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#define RT5627_JACK_DET_CTRL 0X5A //JACK DETECT CONTROL
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#define RT5627_MISC1_CTRL 0X5C //MISC1 CONTROL
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#define RT5627_MISC2_CTRL 0X5E //MISC2 CONTROL
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#define RT5627_AVC_CTRL 0X68 //AVC CONTROL
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#define RT5627_HID_CTRL_INDEX 0X6A //PRIVATE REGISTER ADDRESS
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#define RT5627_HID_CTRL_DATA 0X6C //PRIVATE REGISTER DATA
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#define RT5627_VENDOR_ID1 0x7C //VENDOR ID1
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#define RT5627_VENDOR_ID2 0x7E //VENDOR ID2
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//global definition
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#define RT_L_MUTE (0x1<<15) //MUTE LEFT CONTROL BIT
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#define RT_R_MUTE (0x1<<7) //MUTE RIGHT CONTROL BIT
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#define RT_M_HP_MIXER (0x1<<15) //Mute source to HP Mixer
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#define RT_M_SPK_MIXER (0x1<<14) //Mute source to Speaker Mixer
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#define RT_M_MONO_MIXER (0x1<<13) //Mute source to Mono Mixer
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#define ALL_FIELD 0xffff
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//Output Mixer Control(0x1C)
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#define SPKOUT_N_SOUR_MASK (0x3<<14)
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#define SPKOUT_N_SOUR_MUTE (0x3<<14)
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#define SPKOUT_N_SOUR_LN (0x2<<14)
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#define SPKOUT_N_SOUR_RP (0x1<<14)
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#define SPKOUT_N_SOUR_RN (0x0<<14)
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#define SPKOUT_INPUT_SEL_MASK (0x3<<10)
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#define SPKOUT_INPUT_SEL_SPKMIXER (0x2<<10)
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#define SPKOUT_INPUT_SEL_HPMIXER (0x1<<10)
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#define SPKOUT_INPUT_SEL_VMID (0x0<<10)
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#define HPL_INPUT_SEL_HPLMIXER (0x1<<9)
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#define HPR_INPUT_SEL_HPRMIXER (0x1<<8)
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#define AUXOUT_L_INPUT_SEL_MASK (0x1<<7)
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#define AUXOUT_L_INPUT_SEL_HPLMIXER (0x1<<7)
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#define AUXOUT_L_INPUT_SEL_SPKMIXER (0x0<<7)
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#define AUXOUT_R_INPUT_SEL_MASK (0x1<<6)
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#define AUXOUT_R_INPUT_SEL_HPLMIXER (0x1<<6)
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#define AUXOUT_R_INPUT_SEL_SPKMIXER (0x0<<6)
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#define SPK_VOL_DIFF_NEG_SIG_ENA (0x2<<2)
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#define DAC_DIRECT_TO_HP (0x1<<1)
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#define DAC_DIRECT_TO_AUXOUT (0x1)
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//Audio Interface(0x34)
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#define SDP_MASTER_MODE (0x0<<15)
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#define SDP_SLAVE_MODE (0x1<<15)
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#define MAIN_I2S_BCLK_POL_CTRL (0x1<<7) //0:Normal 1:Invert
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#define DAC_DATA_L_R_SWAP (0x1<<4) //0:DAC data appear at left phase of LRCK
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//1:DAC data appear at right phase of LRCK
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//Data Length Slection
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#define I2S_DL_MASK (0x3<<2) //main i2s Data Length mask
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#define I2S_DL_16 (0x0<<2) //16 bits
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#define I2S_DL_20 (0x1<<2) //20 bits
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#define I2S_DL_24 (0x2<<2) //24 bits
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//PCM Data Format Selection
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#define I2S_DF_MASK (0x3) //IIS Data Format Mask
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#define I2S_DF_I2S (0x0) //I2S FORMAT
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#define I2S_DF_LEFT (0x1) //LEFT JUSTIFIED FORMAT
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#define I2S_DF_PCM_A (0x2) //PCM MODE A
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#define I2S_DF_PCM_B (0x3) //PCM MODE B
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//Stereo AD/DA Clock Control(0x38h)
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#define I2S_PRE_DIV_MASK (0x7<<13)
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#define I2S_PRE_DIV_1 (0x0<<13) //DIV 1
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#define I2S_PRE_DIV_2 (0x1<<13) //DIV 2
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#define I2S_PRE_DIV_4 (0x2<<13) //DIV 4
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#define I2S_PRE_DIV_8 (0x3<<13) //DIV 8
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#define I2S_PRE_DIV_16 (0x4<<13) //DIV 16
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#define I2S_PRE_DIV_32 (0x5<<13) //DIV 32
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#define I2S_BCLK_SEL_64FS (0x0<<12) //32 BITS(64FS)
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#define I2S_BCLK_SEL_32FS (0x1<<12) //16 BITS(32FS)
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#define DAC_FILTER_CLK_SEL_256FS (0<<2) //256FS
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#define DAC_FILTER_CLK_SEL_384FS (1<<2) //384FS
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//Power managment addition 1 (0x3A),0:Disable,1:Enable
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#define PWR_MAIN_I2S_EN (0x1<<15)
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#define PWR_ZC_DET_PD_EN (0x1<<14)
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#define PWR_SOFTGEN_EN (0x1<<8)
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#define PWR_HP_AMP (0x1<<5)
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#define PWR_HP_ENH_AMP (0x1<<4)
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//Power managment addition 2(0x3C),0:Disable,1:Enable
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#define PWR_CLASS_D (0x1<<14)
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#define PWR_VREF (0x1<<13)
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#define PWR_PLL (0x1<<12)
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#define PWR_THERMAL_SD (0x1<<11)
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#define PWR_DAC_REF_CIR (0x1<<10)
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#define PWR_L_DAC_CLK (0x1<<9)
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#define PWR_R_DAC_CLK (0x1<<8)
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#define PWR_L_DAC_L_D_S (0x1<<7)
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#define PWR_R_DAC_R_D_S (0x1<<6)
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#define PWR_L_HP_MIXER (0x1<<5)
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#define PWR_R_HP_MIXER (0x1<<4)
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#define PWR_SPK_MIXER (0x1<<3)
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//Power managment addition 3(0x3E),0:Disable,1:Enable
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#define PWR_MAIN_BIAS (0x1<<15)
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#define PWR_SPK_OUT (0x1<<12)
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#define PWR_HP_L_OUT_VOL_AMP (0x1<<10)
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#define PWR_HP_R_OUT_VOL_AMP (0x1<<9)
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#define PWR_LINEIN_L_VOL (0x1<<7)
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#define PWR_LINEIN_R_VOL (0x1<<6)
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#define PWR_AUXIN_L_VOL (0x1<<5)
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#define PWR_AUXIN_R_VOL (0x1<<4)
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//Additional Control Register(0x40)
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#define SPK_D_AMP_CTRL_MASK (0x7<<9)
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#define SPK_D_AMP_CTRL_RATIO_225 (0x0<<9) //2.25 Vdd
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#define SPK_D_AMP_CTRL_RATIO_200 (0x1<<9) //2.00 Vdd
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#define SPK_D_AMP_CTRL_RATIO_175 (0x2<<9) //1.75 Vdd
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#define SPK_D_AMP_CTRL_RATIO_150 (0x3<<9) //1.50 Vdd
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#define SPK_D_AMP_CTRL_RATIO_125 (0x4<<9) //1.25 Vdd
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#define SPK_D_AMP_CTRL_RATIO_100 (0x5<<9) //1.00 Vdd
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#define STEREO_DAC_H_PASS_EN (0x1<<8) //enable HIGH PASS FILTER FOR DAC
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//Global Clock Control Register(0x42)
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#define SYSCLK_SOUR_SEL_MASK (0x1<<15)
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#define SYSCLK_SOUR_SEL_MCLK (0x0<<15) //system Clock source from MCLK
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#define SYSCLK_SOUR_SEL_PLL (0x1<<15) //system Clock source from PLL
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#define PLLCLK_SOUR_SEL_MCLK (0x0<<14) //PLL clock source from MCLK
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#define PLLCLK_SOUR_SEL_BITCLK (0x1<<14) //PLL clock source from BITCLK
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#define PLLCLK_DIV_RATIO_MASK (0x3<<1)
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#define PLLCLK_DIV_RATIO_DIV1 (0x0<<1) //DIV 1
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#define PLLCLK_DIV_RATIO_DIV2 (0x1<<1) //DIV 2
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#define PLLCLK_DIV_RATIO_DIV4 (0x2<<1) //DIV 4
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#define PLLCLK_DIV_RATIO_DIV8 (0x3<<1) //DIV 8
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#define PLLCLK_PRE_DIV1 (0x0) //DIV 1
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#define PLLCLK_PRE_DIV2 (0x1) //DIV 2
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//PLL Control(0x44)
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#define PLL_CTRL_M_VAL(m) ((m)&0xf)
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#define PLL_CTRL_K_VAL(k) (((k)&0x7)<<4)
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#define PLL_CTRL_N_VAL(n) (((n)&0xff)<<8)
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//GPIO CONTROL(0x4A)
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#define GPIO_PIN_SEL_MASK (0x3<<14)
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#define GPIO_PIN_SEL_LOG_OUT (0x0<<14)
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#define GPIO_PIN_SEL_IRQ (0x1<<14)
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#define GPIO_PIN_SEL_PLLOUT (0x3<<14)
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#define GPIO_PIN_CON_MASK (0x1<<3)
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#define GPIO_PIN_CON_OUTPUT (0x0<<3)
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#define GPIO_PIN_CON_INPUT (0x1<<3)
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#define GPIO_PIN_OUTPUT_SET_MASK (0x1<<2)
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#define GPIO_PIN_OUTPUT_SET_LOW (0x0<<2)
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#define GPIO_PIN_OUTPUT_SET_HIGH (0x1<<2)
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#define GPIO_PIN_POLARITY_INV (0x1<<1)
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//JACK DETECT CONTROL(0x5A)
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#define JACK_DET_SEL_MASK (0x3<<14)
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#define JACK_DET_SEL_OFF (0x0<<14) //Jack Detect Select none
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#define JACK_DET_SEL_GPIO (0x1<<14) //Jack Detect Select GPIO
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#define JACK_DET_SEL_JD1 (0x2<<14) //Jack Detect Select JD1,LineIn Left disable
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#define JACK_DET_SEL_JD2 (0x3<<14) //Jack Detect Select JD2,LineIn Right Disable
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#define JACK_DET_TRI_VREF (0x1<<13)
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#define JACK_DET_POL_TRI_VREF (0x1<<12)
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#define JACK_DET_TRI_HP (0x1<<11)
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#define JACK_DET_POL_TRI_HP (0x1<<10)
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#define JACK_DET_TRI_SPK (0x1<<9)
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#define JACK_DET_POL_TRI_SPK (0x1<<8)
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#define JACK_DET_POL (0x1<<3)
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//MISC1 CONTROL(0x5C)
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#define SPK_L_ZC_CTRL_EN (0x1<<15)
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#define SPK_L_SV_CTRL_EN (0x1<<14)
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#define SPK_R_ZC_CTRL_EN (0x1<<13)
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#define SPK_R_SV_CTRL_EN (0x1<<12)
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#define HP_L_ZC_CTRL_EN (0x1<<11)
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#define HP_L_SV_CTRL_EN (0x1<<10)
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#define HP_R_ZC_CTRL_EN (0x1<<9)
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#define HP_R_SV_CTRL_EN (0x1<<8)
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#define AUXOUT_L_ZC_CTRL_EN (0x1<<7)
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#define AUXOUT_L_SV_CTRL_EN (0x1<<6)
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#define AUXOUT_R_ZC_CTRL_EN (0x1<<5)
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#define AUXOUT_R_SV_CTRL_EN (0x1<<4)
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#define DAC_ZC_CTRL_EN (0x1<<3)
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#define DAC_SV_CTRL_EN (0x1<<2)
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////MISC2 CONTROL(0x5E)
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#define DISABLE_FAST_VREG (0x1<<15)
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#define THERMAL_SHUTDOWN_EN (0x1<<14)
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#define HP_DEPOP_MODE2_EN (0x1<<9)
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#define HP_DEPOP_MODE1_EN (0x1<<8)
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#define HP_L_M_UM_DEPOP_EN (0x1<<7)
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#define HP_R_M_UM_DEPOP_EN (0x1<<6)
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#define M_UM_DEPOP_EN (0x1<<5)
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#define M_DAC_L_INPUT (0x1<<3)
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#define M_DAC_R_INPUT (0x1<<2)
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//AVC Control(0x68)
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#define AVC_ENABLE (0x1<<15)
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#define AVC_TARTGET_SEL_MASK (0x1<<14)
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#define AVC_TARTGET_SEL_R (0x1<<14)
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#define AVC_TARTGET_SEL_L (0x0<<14)
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//WaveOut channel for realtek codec
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enum
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{
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RT_WAVOUT_SPK =(0x1<<0),
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RT_WAVOUT_SPK_R =(0x1<<1),
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RT_WAVOUT_SPK_L =(0x1<<2),
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RT_WAVOUT_HP =(0x1<<3),
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RT_WAVOUT_HP_R =(0x1<<4),
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RT_WAVOUT_HP_L =(0x1<<5),
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RT_WAVOUT_MONO =(0x1<<6),
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RT_WAVOUT_AUXOUT =(0x1<<7),
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RT_WAVOUT_AUXOUT_R =(0x1<<8),
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RT_WAVOUT_AUXOUT_L =(0x1<<9),
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RT_WAVOUT_LINEOUT =(0x1<<10),
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RT_WAVOUT_LINEOUT_R =(0x1<<11),
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RT_WAVOUT_LINEOUT_L =(0x1<<12),
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RT_WAVOUT_DAC =(0x1<<13),
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RT_WAVOUT_ALL_ON =(0x1<<14),
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};
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//WaveIn channel for realtek codec
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enum
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{
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RT_WAVIN_R_MONO_MIXER =(0x1<<0),
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RT_WAVIN_R_SPK_MIXER =(0x1<<1),
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RT_WAVIN_R_HP_MIXER =(0x1<<2),
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RT_WAVIN_R_PHONE =(0x1<<3),
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RT_WAVIN_R_AUXIN =(0x1<<3),
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RT_WAVIN_R_LINE_IN =(0x1<<4),
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RT_WAVIN_R_MIC2 =(0x1<<5),
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RT_WAVIN_R_MIC1 =(0x1<<6),
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RT_WAVIN_L_MONO_MIXER =(0x1<<8),
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RT_WAVIN_L_SPK_MIXER =(0x1<<9),
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RT_WAVIN_L_HP_MIXER =(0x1<<10),
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RT_WAVIN_L_PHONE =(0x1<<11),
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RT_WAVIN_L_AUXIN =(0x1<<11),
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RT_WAVIN_L_LINE_IN =(0x1<<12),
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RT_WAVIN_L_MIC2 =(0x1<<13),
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RT_WAVIN_L_MIC1 =(0x1<<14),
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};
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enum
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{
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POWER_STATE_D0=0,
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POWER_STATE_D1,
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POWER_STATE_D1_PLAYBACK,
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POWER_STATE_D1_RECORD,
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POWER_STATE_D2,
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POWER_STATE_D2_PLAYBACK,
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POWER_STATE_D2_RECORD,
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POWER_STATE_D3,
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POWER_STATE_D4
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};
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struct rt5627_setup_data {
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unsigned short i2c_address;
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};
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#define RT5627_PLL_FR_MCLK 0
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#define RT5627_PLL_FR_BCK 1
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extern struct snd_soc_codec_dai rt5627_dai;
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extern struct snd_soc_codec_device soc_codec_dev_rt5627;
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#endif
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