653 lines
16 KiB
C
653 lines
16 KiB
C
/*
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* s3c-i2s.c -- ALSA Soc Audio Layer
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*
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* (c) 2006 Wolfson Microelectronics PLC.
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* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
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*
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* (c) 2004-2005 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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* Ryu Euiyoul <ryu.real@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* Revision history
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* 11th Dec 2006 Merged with Simtec driver
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* 10th Nov 2006 Initial version.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <sound/driver.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/dma.h>
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#include <asm/arch/regs-iis.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/audio.h>
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#include <asm/arch/dma.h>
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#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
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#include <asm/arch/regs-clock.h>
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#else
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#include <asm/arch/regs-s3c6400-clock.h>
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#endif
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#include "s3c-pcm.h"
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#include "s3c-i2s.h"
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#ifdef CONFIG_SND_DEBUG
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#define s3cdbg(x...) printk(x)
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#else
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#define s3cdbg(x...)
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#endif
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/* used to disable sysclk if external crystal is used */
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static int extclk = 0;
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module_param(extclk, int, 0);
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MODULE_PARM_DESC(extclk, "set to 1 to disable s3c24XX i2s sysclk");
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static struct s3c2410_dma_client s3c24xx_dma_client_out = {
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.name = "I2S PCM Stereo out"
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};
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static struct s3c2410_dma_client s3c24xx_dma_client_in = {
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.name = "I2S PCM Stereo in"
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};
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static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
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.client = &s3c24xx_dma_client_out,
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.channel = DMACH_I2S_OUT,
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#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
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.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
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.dma_size = 2,
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#else
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.dma_addr = S3C6400_PA_IIS + S3C2410_IISFIFO,
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.dma_size = 4,
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#endif
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};
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static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
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.client = &s3c24xx_dma_client_in,
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.channel = DMACH_I2S_IN,
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#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
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.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFORX,
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.dma_size = 2,
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#else
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.dma_addr = S3C6400_PA_IIS + S3C2410_IISFIFORX,
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.dma_size = 4,
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#endif
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};
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struct s3c24xx_i2s_info {
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void __iomem *regs;
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struct clk *iis_clk;
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int master;
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};
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static struct s3c24xx_i2s_info s3c24xx_i2s;
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static void s3c24xx_snd_txctrl(int on)
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{
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u32 iisfcon;
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u32 iiscon;
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u32 iismod;
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s3cdbg("Entered %s : on = %d \n", __FUNCTION__, on);
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
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s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
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if (on) {
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#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
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iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
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iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
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iiscon &= ~S3C2410_IISCON_TXIDLE;
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iismod |= S3C2410_IISMOD_TXMODE;
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#else
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iiscon |= S3C_IIS0CON_I2SACTIVE;
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#endif
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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} else {
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/* note, we have to disable the FIFOs otherwise bad things
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* seem to happen when the DMA stops. According to the
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* Samsung supplied kernel, this should allow the DMA
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* engine and FIFOs to reset. If this isn't allowed, the
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* DMA engine will simply freeze randomly.
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*/
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#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
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iisfcon &= ~S3C2410_IISFCON_TXENABLE;
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iisfcon &= ~S3C2410_IISFCON_TXDMA;
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iiscon |= S3C2410_IISCON_TXIDLE;
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iiscon &= ~S3C2410_IISCON_TXDMAEN;
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iismod &= ~S3C2410_IISMOD_TXMODE;
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#else
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iiscon &=~(S3C_IIS0CON_I2SACTIVE);
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iismod &= ~S3C_IIS0MOD_TXMODE;
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#endif
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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}
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s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
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}
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static void s3c24xx_snd_rxctrl(int on)
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{
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u32 iisfcon;
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u32 iiscon;
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u32 iismod;
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s3cdbg("Entered %s: on = %d\n", __FUNCTION__, on);
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iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
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if (on) {
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#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
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iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
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iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
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iiscon &= ~S3C2410_IISCON_RXIDLE;
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iismod |= S3C2410_IISMOD_RXMODE;
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#else
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iiscon |= S3C_IIS0CON_I2SACTIVE;
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#endif
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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} else {
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/* note, we have to disable the FIFOs otherwise bad things
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* seem to happen when the DMA stops. According to the
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* Samsung supplied kernel, this should allow the DMA
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* engine and FIFOs to reset. If this isn't allowed, the
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* DMA engine will simply freeze randomly.
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*/
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#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
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iisfcon &= ~S3C2410_IISFCON_RXENABLE;
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iisfcon &= ~S3C2410_IISFCON_RXDMA;
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iiscon |= S3C2410_IISCON_RXIDLE;
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iiscon &= ~S3C2410_IISCON_RXDMAEN;
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iismod &= ~S3C2410_IISMOD_RXMODE;
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#else
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iiscon &=~ S3C_IIS0CON_I2SACTIVE;
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iismod &= ~S3C_IIS0MOD_RXMODE;
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#endif
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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}
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s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
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}
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/*
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* Wait for the LR signal to allow synchronisation to the L/R clock
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* from the codec. May only be needed for slave mode.
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*/
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static int s3c24xx_snd_lrsync(void)
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{
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u32 iiscon;
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unsigned long timeout = jiffies + msecs_to_jiffies(5);
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s3cdbg("Entered %s\n", __FUNCTION__);
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while (1) {
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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if (iiscon & S3C2410_IISCON_LRINDEX)
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break;
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if (timeout < jiffies)
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return -ETIMEDOUT;
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}
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return 0;
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}
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/*
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* Check whether CPU is the master or slave
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*/
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static inline int s3c24xx_snd_is_clkmaster(void)
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{
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s3cdbg("Entered %s\n", __FUNCTION__);
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return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
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}
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/*
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* Set S3C24xx I2S DAI format
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*/
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static int s3c_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
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unsigned int fmt)
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{
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#if 0
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u32 iismod;
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s3cdbg("Entered %s: fmt = %d\n", __FUNCTION__, fmt);
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
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iismod |= S3C2410_IISMOD_SLAVE;
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#else
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iismod |= S3C2410_IISMOD_MASTER;
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#endif
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_LEFT_J:
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#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
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iismod |= S3C2410_IISMOD_MSB;
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#else
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iismod |= S3C_IIS0MOD_MSB;
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#endif
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break;
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case SND_SOC_DAIFMT_I2S:
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break;
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default:
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return -EINVAL;
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}
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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#endif
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return 0;
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}
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static int s3c_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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unsigned long iiscon;
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unsigned long iismod;
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unsigned long iisfcon;
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s3cdbg("Entered %s\n", __FUNCTION__);
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/*Set I2C port to controll WM8753 codec*/
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s3c_gpio_pullup(S3C_GPB5, 0);
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s3c_gpio_pullup(S3C_GPB6, 0);
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s3c_gpio_cfgpin(S3C_GPB5, S3C_GPB5_I2C_SCL);
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s3c_gpio_cfgpin(S3C_GPB6, S3C_GPB6_I2C_SDA);
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s3c24xx_i2s.master = 1;
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/* Configure the I2S pins in correct mode */
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s3c_gpio_cfgpin(S3C_GPD2,S3C_GPD2_I2S_LRCLK0);
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if (s3c24xx_i2s.master && !extclk){
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s3cdbg("Setting Clock Output as we are Master\n");
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s3c_gpio_cfgpin(S3C_GPD0,S3C_GPD0_I2S_CLK0);
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}
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s3c_gpio_cfgpin(S3C_GPD1,S3C_GPD1_I2S_CDCLK0);
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s3c_gpio_cfgpin(S3C_GPD3,S3C_GPD3_I2S_DI0);
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s3c_gpio_cfgpin(S3C_GPD4,S3C_GPD4_I2S_DO0);
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/* pull-up-enable, pull-down-disable*/
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s3c_gpio_pullup(S3C_GPD0, 0x2);
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s3c_gpio_pullup(S3C_GPD1, 0x2);
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s3c_gpio_pullup(S3C_GPD2, 0x2);
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s3c_gpio_pullup(S3C_GPD3, 0x2);
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s3c_gpio_pullup(S3C_GPD4, 0x2);
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s3cdbg("substream->stream : %d\n", substream->stream);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
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} else {
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rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
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}
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/* Working copies of registers */
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iiscon = readl(S3C_IIS0CON);
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iismod = readl(S3C_IIS0MOD);
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iisfcon = readl(S3C_IIS0FIC);
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/* is port used by another stream */
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if (!(iiscon & S3C_IIS0CON_I2SACTIVE)) {
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iismod |= S3C_IIS0MOD_INTERNAL_CLK;
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if (!s3c24xx_i2s.master)
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iismod |= S3C_IIS0MOD_IMS_SLAVE;
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else
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iismod |= S3C_IIS0MOD_IMS_EXTERNAL_MASTER;
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}
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/* enable TX & RX all to support Full-duplex */
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iismod |= S3C_IIS0MOD_TXRXMODE;
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iiscon |= S3C_IIS0CON_TXDMACTIVE;
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iisfcon |= S3C_IIS_TX_FLUSH;
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iiscon |= S3C_IIS0CON_RXDMACTIVE;
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iisfcon |= S3C_IIS_RX_FLUSH;
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/* Set the bit rate */
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iismod &= ~0x6000;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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iismod |= S3C_IIS0MOD_16BIT;
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break;
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#ifdef CONFIG_CPU_S3C6410
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case SNDRV_PCM_FORMAT_S8:
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iismod |= S3C_IIS0MOD_8BIT;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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iismod |= S3C_IIS0MOD_24BIT;
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break;
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#endif
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default:
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return -EINVAL;
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}
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writel(iiscon, S3C_IIS0CON);
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writel(iismod, S3C_IIS0MOD);
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writel(iisfcon, S3C_IIS0FIC);
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// Tx, Rx fifo flush bit clear
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iisfcon &= ~(S3C_IIS_TX_FLUSH | S3C_IIS_RX_FLUSH);
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writel(iisfcon, S3C_IIS0FIC);
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s3cdbg("IISCON: %lx IISMOD: %lx", iiscon, iismod);
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return 0;
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}
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static int s3c_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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int ret = 0;
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s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (!s3c24xx_snd_is_clkmaster()) {
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ret = s3c24xx_snd_lrsync();
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if (ret)
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goto exit_err;
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}
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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s3c24xx_snd_rxctrl(1);
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else
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s3c24xx_snd_txctrl(1);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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s3c24xx_snd_rxctrl(0);
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else
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s3c24xx_snd_txctrl(0);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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exit_err:
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return ret;
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}
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static void s3c64xx_i2s_shutdown(struct snd_pcm_substream *substream)
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{
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unsigned long iismod, iiscon;
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s3cdbg("Entered %s\n", __FUNCTION__);
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iismod=readl(S3C_IIS0MOD);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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iismod &= ~S3C_IIS0MOD_TXMODE;
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} else {
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iismod &= ~S3C_IIS0MOD_RXMODE;
|
|
}
|
|
|
|
writel(iismod,S3C_IIS0MOD);
|
|
|
|
iiscon=readl(S3C_IIS0CON);
|
|
iiscon &= !S3C_IIS0CON_I2SACTIVE;
|
|
writel(iiscon,S3C_IIS0CON);
|
|
|
|
/* Clock disable
|
|
* PCLK & SCLK gating disable
|
|
*/
|
|
__raw_writel(__raw_readl(S3C_PCLK_GATE)&~(S3C_CLKCON_PCLK_IIS0), S3C_PCLK_GATE);
|
|
__raw_writel(__raw_readl(S3C_SCLK_GATE)&~(S3C_CLKCON_SCLK_AUDIO0), S3C_SCLK_GATE);
|
|
|
|
/* EPLL disable */
|
|
__raw_writel(__raw_readl(S3C_EPLL_CON0)&~(1<<31) ,S3C_EPLL_CON0);
|
|
|
|
}
|
|
|
|
|
|
/*
|
|
* Set S3C24xx Clock source
|
|
*/
|
|
static int s3c_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
|
|
int clk_id, unsigned int freq, int dir)
|
|
{
|
|
u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
|
|
|
|
s3cdbg("Entered %s : clk_id = %d\n", __FUNCTION__, clk_id);
|
|
|
|
iismod &= ~S3C2440_IISMOD_MPLL;
|
|
|
|
switch (clk_id) {
|
|
case S3C24XX_CLKSRC_PCLK:
|
|
break;
|
|
case S3C24XX_CLKSRC_MPLL:
|
|
iismod |= S3C2440_IISMOD_MPLL;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set S3C24xx Clock dividers
|
|
*/
|
|
static int s3c_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
|
|
int div_id, int div)
|
|
{
|
|
u32 reg;
|
|
|
|
s3cdbg("Entered %s : div_id = %d, div = %d\n", __FUNCTION__, div_id, div);
|
|
|
|
switch (div_id) {
|
|
case S3C24XX_DIV_MCLK:
|
|
#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
|
|
reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
|
|
writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
|
|
#endif
|
|
break;
|
|
case S3C24XX_DIV_BCLK:
|
|
reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
|
|
writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
|
|
break;
|
|
case S3C24XX_DIV_PRESCALER:
|
|
#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
|
|
writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
|
|
reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
|
|
writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
|
|
#else
|
|
writel(div|(1<<15),S3C_IIS0PSR);
|
|
#endif
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
|
|
/*
|
|
* To avoid duplicating clock code, allow machine driver to
|
|
* get the clockrate from here.
|
|
*/
|
|
u32 s3c24xx_i2s_get_clockrate(void)
|
|
{
|
|
return clk_get_rate(s3c24xx_i2s.iis_clk);
|
|
}
|
|
EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
|
|
#endif
|
|
|
|
static int s3c_i2s_probe(struct platform_device *pdev)
|
|
{
|
|
s3cdbg("Entered %s\n", __FUNCTION__);
|
|
|
|
s3c24xx_i2s.regs = ioremap(S3C24XX_PA_IIS, 0x100);
|
|
if (s3c24xx_i2s.regs == NULL)
|
|
return -ENXIO;
|
|
|
|
#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
|
|
s3c24xx_i2s.iis_clk=clk_get(&pdev->dev, "iis");
|
|
if (s3c24xx_i2s.iis_clk == NULL) {
|
|
s3cdbg("failed to get iis_clock\n");
|
|
return -ENODEV;
|
|
}
|
|
clk_enable(s3c24xx_i2s.iis_clk);
|
|
|
|
/* Configure the I2S pins in correct mode */
|
|
s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
|
|
s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
|
|
s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
|
|
s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
|
|
s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
|
|
|
|
writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
|
|
|
|
/* Configure the I2S pins in correct mode */
|
|
s3c_gpio_cfgpin(S3C_GPD2,S3C_GPD2_I2S_LRCLK0);
|
|
|
|
s3c_gpio_cfgpin(S3C_GPD0,S3C_GPD0_I2S_CLK0);
|
|
|
|
s3c_gpio_cfgpin(S3C_GPD1,S3C_GPD1_I2S_CDCLK0);
|
|
s3c_gpio_cfgpin(S3C_GPD3,S3C_GPD3_I2S_DI0);
|
|
s3c_gpio_cfgpin(S3C_GPD4,S3C_GPD4_I2S_DO0);
|
|
|
|
/* pull-up-enable, pull-down-disable*/
|
|
s3c_gpio_pullup(S3C_GPD0, 0x2);
|
|
s3c_gpio_pullup(S3C_GPD1, 0x2);
|
|
s3c_gpio_pullup(S3C_GPD2, 0x2);
|
|
s3c_gpio_pullup(S3C_GPD3, 0x2);
|
|
s3c_gpio_pullup(S3C_GPD4, 0x2);
|
|
|
|
writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
|
|
s3c24xx_snd_txctrl(0);
|
|
s3c24xx_snd_rxctrl(0);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int s3c_i2s_suspend(struct platform_device *dev,
|
|
struct snd_soc_cpu_dai *dai)
|
|
{
|
|
s3cdbg("Entered %s\n", __FUNCTION__);
|
|
return 0;
|
|
}
|
|
|
|
static int s3c_i2s_resume(struct platform_device *pdev,
|
|
struct snd_soc_cpu_dai *dai)
|
|
{
|
|
s3cdbg("Entered %s\n", __FUNCTION__);
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define s3c_i2s_suspend NULL
|
|
#define s3c_i2s_resume NULL
|
|
#endif
|
|
|
|
|
|
#define S3C24XX_I2S_RATES \
|
|
(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
|
|
SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
|
|
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
|
|
|
|
struct snd_soc_cpu_dai s3c_i2s_dai = {
|
|
.name = "s3c-i2s",
|
|
.id = 0,
|
|
.type = SND_SOC_DAI_I2S,
|
|
.probe = s3c_i2s_probe,
|
|
.suspend = s3c_i2s_suspend,
|
|
.resume = s3c_i2s_resume,
|
|
.playback = {
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.rates = S3C24XX_I2S_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE,},
|
|
.capture = {
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.rates = S3C24XX_I2S_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE,},
|
|
.ops = {
|
|
.shutdown = s3c64xx_i2s_shutdown,
|
|
.trigger = s3c_i2s_trigger,
|
|
.hw_params = s3c_i2s_hw_params,},
|
|
.dai_ops = {
|
|
.set_fmt = s3c_i2s_set_fmt,
|
|
.set_clkdiv = s3c_i2s_set_clkdiv,
|
|
.set_sysclk = s3c_i2s_set_sysclk,
|
|
},
|
|
};
|
|
EXPORT_SYMBOL_GPL(s3c_i2s_dai);
|
|
|
|
|
|
static int __init s3c_i2s_init(void)
|
|
{
|
|
/* Add in 24 bit audio support - FIXME, detect at runtime */
|
|
#ifdef CONFIG_CPU_S3C6410
|
|
s3c_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;
|
|
s3c_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
module_init(s3c_i2s_init);
|
|
|
|
/* Module information */
|
|
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
|
|
MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
|
|
MODULE_LICENSE("GPL");
|