562 lines
14 KiB
C
562 lines
14 KiB
C
/*
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* s3c2450-ac97.c -- ALSA Soc Audio Layer
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*
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* (c) 2007 Wolfson Microelectronics PLC.
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* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
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*
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* Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Revision history
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* 21st Mar 2007 Initial Version
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/wait.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <sound/driver.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/ac97_codec.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/regs-ac97.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-s3c2450-clock.h>
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#include <asm/arch/audio.h>
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#include <asm/dma.h>
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#include <asm/arch/dma.h>
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#include "s3c-pcm.h"
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#include "s3c24xx-ac97.h"
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#ifdef CONFIG_SND_DEBUG
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#define s3cdbg(x...) printk(x)
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#else
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#define s3cdbg(x...)
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#endif
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extern struct clk *clk_get(struct device *dev, const char *id);
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extern int clk_enable(struct clk *clk);
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extern void clk_disable(struct clk *clk);
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struct s3c24xx_ac97_info {
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void __iomem *regs;
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struct clk *ac97_clk;
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};
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static struct s3c24xx_ac97_info s3c24xx_ac97;
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static u32 codec_ready;
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static DEFINE_MUTEX(ac97_mutex);
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static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
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static unsigned short s3c24xx_ac97_read(struct snd_ac97 *ac97,
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unsigned short reg)
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{
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u32 ac_glbctrl;
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u32 ac_codec_cmd;
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u32 stat, addr, data;
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s3cdbg("Entered %s: reg=0x%x\n", __FUNCTION__, reg);
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mutex_lock(&ac97_mutex);
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codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
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ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
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writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
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udelay(1000);
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
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addr = (stat >> 16) & 0x7f;
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data = (stat & 0xffff);
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wait_event_timeout(gsr_wq,addr==reg,1);
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if(addr!=reg){
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printk(KERN_ERR"AC97: read error (ac97_reg=%x addr=%x)\n", reg, addr);
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printk(KERN_ERR"Check audio codec jumpper settings\n\n");
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goto out;
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}
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out: mutex_unlock(&ac97_mutex);
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return (unsigned short)data;
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}
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static void s3c24xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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unsigned short val)
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{
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u32 ac_glbctrl;
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u32 ac_codec_cmd;
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u32 stat, data;
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s3cdbg("Entered %s: reg=0x%x, val=0x%x\n", __FUNCTION__,reg,val);
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mutex_lock(&ac97_mutex);
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codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
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ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
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writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
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udelay(50);
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
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writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
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stat = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
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data = (stat & 0xffff);
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wait_event_timeout(gsr_wq,data==val,1);
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if(data!=val){
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printk("%s: write error (ac97_val=%x data=%x)\n",
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__FUNCTION__, val, data);
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}
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mutex_unlock(&ac97_mutex);
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}
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static void s3c24xx_ac97_warm_reset(struct snd_ac97 *ac97)
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{
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u32 ac_glbctrl;
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s3cdbg("Entered %s\n", __FUNCTION__);
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl |= S3C_AC97_GLBCTRL_WARMRESET;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl &= ~S3C_AC97_GLBCTRL_WARMRESET;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl = S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
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S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl |= S3C_AC97_GLBCTRL_ACLINKON;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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udelay(1000);
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}
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static void s3c24xx_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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u32 ac_glbctrl;
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s3cdbg("Entered %s\n", __FUNCTION__);
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ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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}
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static irqreturn_t s3c24xx_ac97_irq(int irq, void *dev_id)
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{
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int status;
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u32 ac_glbctrl, ac_glbstat;
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ac_glbstat = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT);
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s3cdbg("Entered %s: AC_GLBSTAT = 0x%x\n", __FUNCTION__, ac_glbstat);
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status = ac_glbstat & codec_ready;
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if (status) {
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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wake_up(&gsr_wq);
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}
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return IRQ_HANDLED;
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}
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struct snd_ac97_bus_ops soc_ac97_ops = {
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.read = s3c24xx_ac97_read,
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.write = s3c24xx_ac97_write,
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.warm_reset = s3c24xx_ac97_warm_reset,
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.reset = s3c24xx_ac97_cold_reset,
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};
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static struct s3c2410_dma_client s3c24xx_dma_client_out = {
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.name = "AC97 PCM Stereo out"
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};
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static struct s3c24xx_pcm_dma_params s3c24xx_ac97_pcm_stereo_out = {
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.client = &s3c24xx_dma_client_out,
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.channel = DMACH_PCM_OUT,
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.dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
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.dma_size = 4,
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};
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#ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
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static struct s3c2410_dma_client s3c24xx_dma_client_micin = {
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.name = "AC97 Mic Mono in"
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};
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static struct s3c24xx_pcm_dma_params s3c24xx_ac97_mic_mono_in = {
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.client = &s3c24xx_dma_client_micin,
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.channel = DMACH_MIC_IN,
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.dma_addr = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
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.dma_size = 4,
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};
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#else /* Input Stream is LINE-IN */
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static struct s3c2410_dma_client s3c24xx_dma_client_in = {
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.name = "AC97 PCM Stereo Line in"
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};
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static struct s3c24xx_pcm_dma_params s3c24xx_ac97_pcm_stereo_in = {
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.client = &s3c24xx_dma_client_in,
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.channel = DMACH_PCM_IN,
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.dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
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.dma_size = 4,
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};
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#endif
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static int s3c24xx_ac97_probe(struct platform_device *pdev)
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{
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int ret;
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s3cdbg("Entered %s\n", __FUNCTION__);
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s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100);
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if (s3c24xx_ac97.regs == NULL)
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return -ENXIO;
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s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
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if (s3c24xx_ac97.ac97_clk == NULL) {
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printk(KERN_ERR "s3c24xx-ac97 failed to get ac97_clock\n");
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iounmap(s3c24xx_ac97.regs);
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return -ENODEV;
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}
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clk_enable(s3c24xx_ac97.ac97_clk);
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s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET);
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s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC);
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s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK);
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s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI);
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s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO);
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ret = request_irq(IRQ_S3C2443_AC97, s3c24xx_ac97_irq,
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IRQF_DISABLED, "AC97", NULL);
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if (ret < 0) {
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printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
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clk_disable(s3c24xx_ac97.ac97_clk);
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clk_put(s3c24xx_ac97.ac97_clk);
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iounmap(s3c24xx_ac97.regs);
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}
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return ret;
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}
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static void s3c24xx_ac97_remove(struct platform_device *pdev)
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{
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s3cdbg("Entered %s\n", __FUNCTION__);
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free_irq(IRQ_S3C2443_AC97, NULL);
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clk_disable(s3c24xx_ac97.ac97_clk);
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clk_put(s3c24xx_ac97.ac97_clk);
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iounmap(s3c24xx_ac97.regs);
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}
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static int s3c24xx_ac97_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
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s3cdbg("Entered %s\n", __FUNCTION__);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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cpu_dai->dma_data = &s3c24xx_ac97_pcm_stereo_out;
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else
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#ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
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cpu_dai->dma_data = &s3c24xx_ac97_mic_mono_in;
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#else /* Input Stream is LINE-IN */
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cpu_dai->dma_data = &s3c24xx_ac97_pcm_stereo_in;
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#endif
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return 0;
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}
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static int s3c24xx_ac97_hifi_prepare(struct snd_pcm_substream *substream)
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{
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s3cdbg("Entered %s\n", __FUNCTION__);
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/*
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* register 26h : standard power down control register
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* now set 0x0 is all power on. Need to optimize if reduce power condition
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*/
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s3c24xx_ac97_write(0,0x26,0x0);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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/*
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* register 02h : speaker volume
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* now set 0x8080 is mute speaker left and right.
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*/
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s3c24xx_ac97_write(0,0x02,0x8080);
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/*
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* register 04h : Headphone volume
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* now set 0x0606 is Un-Mute headphone and volume set.
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*/
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s3c24xx_ac97_write(0,0x04,0x0606);
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/*
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* register 0Ch : DAC Volume
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* now set 0x6808 is only ON the path to headphone mixer
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* and set the DAC volume.
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*/
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s3c24xx_ac97_write(0,0x0c,0x6808);
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/*
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* register 1Ch : Output PGA Mux select
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* now set 0x00aa is headphone mixer and OUT3, OUT4 enable
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* to roud sound?
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*/
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s3c24xx_ac97_write(0,0x1c,0x00aa);
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/*
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* register 3Ch : Power management
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* now set 0xf933 enables headphone mixer, DAC, PLL and Vref.
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*/
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s3c24xx_ac97_write(0,0x3c,0xf933);
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/*
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* register 3Eh : Power management
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* now set 0xf9ff only enables headphone output PGA.
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*/
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s3c24xx_ac97_write(0,0x3e,0xf9ff);
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}
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else
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{
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/*
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* register 0Ch : DAC Volume
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* now set 0xe808 is Mute DAC path to headphone,speaker,mono mixer
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* and set the DAC volume.
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*/
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s3c24xx_ac97_write(0,0x0c,0xe808);
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/*
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* register 12h : Record Gain
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* 0x0F0F set right and left ADC recording volume as +22.5dB.
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*/
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s3c24xx_ac97_write(0,0x12,0x0f0f);
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/*
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* register 3Ch : Power management
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* now set 0xf933 enables ADC, PLL and Vref.
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*/
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s3c24xx_ac97_write(0,0x3c,0xf8cf);
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#ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
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/*
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* register 5Ch : ADC SLOT Mapping
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* now set 0x2 is Left = slot7, Right = slot8.
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*/
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s3c24xx_ac97_write(0,0x5c,0x2);
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/*
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* register 22h : MIC input select
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*/
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s3c24xx_ac97_write(0,0x22,0x4060);
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/*
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* register 10h : MIC Routing
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*/
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s3c24xx_ac97_write(0,0x10,0x68);
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/*
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* register 14h : Record Routing & Mux select
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* Default value 0xD600 is MIC
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*/
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s3c24xx_ac97_write(0,0x14,0xfe00);
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/*
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* register 3Eh : Power management
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* now set 0xff9f only enables LINE PGA.
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*/
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s3c24xx_ac97_write(0,0x3e,0xbff0);
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#else /* Input Stream is LINE-IN */
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/*
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* register 14h : Record Routing & Mux select
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* 0xD612 set record mux source as LINE
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* and mute headphone, mono mixer path.
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* Default value 0xD600 is MIC
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*/
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s3c24xx_ac97_write(0,0x14,0xd612);
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/*
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* register 3Eh : Power management
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* now set 0xff9f only enables LINE PGA.
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*/
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s3c24xx_ac97_write(0,0x3e,0xff9f);
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#endif
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}
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return 0;
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}
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static int s3c24xx_ac97_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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u32 ac_glbctrl;
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s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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switch(cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
|
ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
|
|
else
|
|
ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
|
ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
|
|
else
|
|
ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
|
|
break;
|
|
}
|
|
writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if 0
|
|
static int s3c24xx_ac97_hw_mic_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params)
|
|
{
|
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
|
struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
return -ENODEV;
|
|
else
|
|
cpu_dai->dma_data = &s3c24xx_ac97_mic_mono_in;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c24xx_ac97_mic_trigger(struct snd_pcm_substream *substream,
|
|
int cmd)
|
|
{
|
|
u32 ac_glbctrl;
|
|
|
|
s3cdbg("Entered %s\n", __FUNCTION__);
|
|
|
|
ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
|
|
switch(cmd) {
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
|
|
}
|
|
writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#define s3c24xx_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
|
|
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
|
|
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
|
|
|
|
struct snd_soc_cpu_dai s3c24xx_ac97_dai[] = {
|
|
{
|
|
.name = "s3c24xx-ac97",
|
|
.id = 0,
|
|
.type = SND_SOC_DAI_AC97,
|
|
.probe = s3c24xx_ac97_probe,
|
|
.remove = s3c24xx_ac97_remove,
|
|
.playback = {
|
|
.stream_name = "AC97 Playback",
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.rates = s3c24xx_AC97_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
|
|
.capture = {
|
|
.stream_name = "AC97 Capture",
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.rates = s3c24xx_AC97_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
|
|
.ops = {
|
|
.hw_params = s3c24xx_ac97_hw_params,
|
|
.prepare = s3c24xx_ac97_hifi_prepare,
|
|
.trigger = s3c24xx_ac97_trigger},
|
|
},
|
|
#if 0
|
|
{
|
|
.name = "s3c24xx-ac97-mic",
|
|
.id = 1,
|
|
.type = SND_SOC_DAI_AC97,
|
|
.capture = {
|
|
.stream_name = "AC97 Mic Capture",
|
|
.channels_min = 1,
|
|
.channels_max = 1,
|
|
.rates = s3c24xx_AC97_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
|
|
.ops = {
|
|
.hw_params = s3c24xx_ac97_hw_mic_params,
|
|
.trigger = s3c24xx_ac97_mic_trigger,},
|
|
},
|
|
#endif
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(s3c24xx_ac97_dai);
|
|
EXPORT_SYMBOL_GPL(soc_ac97_ops);
|
|
|
|
MODULE_AUTHOR("Ryu Euiyoul");
|
|
MODULE_DESCRIPTION("AC97 driver for the Samsung s3c24xx chip");
|
|
MODULE_LICENSE("GPL");
|