554 lines
14 KiB
C
554 lines
14 KiB
C
/*
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* s3c-i2s.c -- ALSA Soc Audio Layer
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*
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* (c) 2006 Wolfson Microelectronics PLC.
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* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
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*
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* (c) 2004-2005 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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* Ryu Euiyoul <ryu.real@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* Revision history
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* 11th Dec 2006 Merged with Simtec driver
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* 10th Nov 2006 Initial version.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <sound/driver.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/dma.h>
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#include <asm/arch/regs-iis.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-gpioj.h>
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#include <asm/arch/audio.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/regs-s3c2450-clock.h>
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#include "s3c-pcm.h"
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#include "s3c-i2s.h"
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#ifdef CONFIG_SND_DEBUG
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#define s3cdbg(x...) printk(x)
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#else
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#define s3cdbg(x...)
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#endif
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/* used to disable sysclk if external crystal is used */
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static int extclk = 0;
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module_param(extclk, int, 0);
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MODULE_PARM_DESC(extclk, "set to 1 to disable s3c24XX i2s sysclk");
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static struct s3c2410_dma_client s3c24xx_dma_client_out = {
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.name = "I2S PCM Stereo out"
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};
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static struct s3c2410_dma_client s3c24xx_dma_client_in = {
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.name = "I2S PCM Stereo in"
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};
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static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
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.client = &s3c24xx_dma_client_out,
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#if defined CONFIG_SND_SOC_I2S_V32
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.channel = DMACH_I2S_OUT_1,
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.dma_addr = S3C2450_PA_IIS_1 + S3C2410_IISFIFO,
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#elif defined CONFIG_SND_SOC_I2S_V40
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.channel = DMACH_I2S_OUT,
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.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
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#endif
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.dma_size = 4,
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};
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static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
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.client = &s3c24xx_dma_client_in,
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#if defined CONFIG_SND_SOC_I2S_V32
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.channel = DMACH_I2S_IN_1,
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.dma_addr = S3C2450_PA_IIS_1 + S3C2410_IISFIFORX,
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#elif defined CONFIG_SND_SOC_I2S_V40
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.channel = DMACH_I2S_IN,
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.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFORX,
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#endif
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.dma_size = 4,
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};
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struct s3c24xx_i2s_info {
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void __iomem *regs;
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struct clk *iis_clk;
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int master;
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};
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static struct s3c24xx_i2s_info s3c24xx_i2s;
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static void s3c24xx_snd_txctrl(int on)
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{
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u32 iiscon;
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s3cdbg("Entered %s : on = %d \n", __FUNCTION__, on);
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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if (on) {
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iiscon |= S3C_IIS0CON_I2SACTIVE;
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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} else {
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/* note, we have to disable the FIFOs otherwise bad things
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* seem to happen when the DMA stops. According to the
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* Samsung supplied kernel, this should allow the DMA
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* engine and FIFOs to reset. If this isn't allowed, the
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* DMA engine will simply freeze randomly.
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*/
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iiscon &= ~S3C_IIS0CON_I2SACTIVE;
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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}
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}
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static void s3c24xx_snd_rxctrl(int on)
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{
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u32 iiscon;
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s3cdbg("Entered %s: on = %d\n", __FUNCTION__, on);
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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if (on) {
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iiscon |= S3C_IIS0CON_I2SACTIVE;
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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} else {
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/* note, we have to disable the FIFOs otherwise bad things
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* seem to happen when the DMA stops. According to the
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* Samsung supplied kernel, this should allow the DMA
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* engine and FIFOs to reset. If this isn't allowed, the
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* DMA engine will simply freeze randomly.
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*/
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iiscon &= ~S3C_IIS0CON_I2SACTIVE;
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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}
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}
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/*
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* Wait for the LR signal to allow synchronisation to the L/R clock
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* from the codec. May only be needed for slave mode.
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*/
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static int s3c24xx_snd_lrsync(void)
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{
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u32 iiscon;
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unsigned long timeout = jiffies + msecs_to_jiffies(5);
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s3cdbg("Entered %s\n", __FUNCTION__);
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while (1) {
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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if (iiscon & S3C_IISCON_LRINDEX)
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break;
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if (timeout < jiffies)
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return -ETIMEDOUT;
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}
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return 0;
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}
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/*
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* Check whether CPU is the master or slave
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*/
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static inline int s3c24xx_snd_is_clkmaster(void)
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{
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s3cdbg("Entered %s\n", __FUNCTION__);
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return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C_IIS0MOD_IMS_SLAVE) ? 0:1;
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}
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/*
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* Set S3C24xx I2S DAI format
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*/
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static int s3c_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
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unsigned int fmt)
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{
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u32 iismod;
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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iismod &= ~S3C_IIS0MOD_FS_MASK;
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iismod |= S3C_IIS0MOD_384FS;
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#if defined CONFIG_SND_SOC_I2S_V40
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/* 24bit enable */
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// iismod &= ~S3C_IIS0MOD_BLC_MASK;
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// iismod |= S3C_IIS0MOD_BLC_24BIT;
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#endif
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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return 0;
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}
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static int s3c_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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unsigned long iiscon;
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unsigned long iismod;
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unsigned long iisfcon;
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s3cdbg("Entered %s\n", __FUNCTION__);
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writel((readl(S3C2410_MISCCR) & ~(7<<8))|(1<<8), S3C2410_MISCCR);
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/*Set I2C port to controll WM8753 codec*/
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s3c2410_gpio_pullup(S3C2410_GPE15, 0);
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s3c2410_gpio_pullup(S3C2410_GPE14, 0);
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s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
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s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
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#if defined CONFIG_SND_SOC_I2S_V40
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/* Configure the I2S pins in correct mode */
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writel(0x0, S3C2450_GPESEL);
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s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
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s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
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s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
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s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
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s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
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writel(readl(S3C2410_GPEUP)| 0x3ff, S3C2410_GPEUP);
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writel(readl(S3C2450_GPBSEL)|(0x3<<3), S3C2450_GPBSEL);
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writel(readl(S3C2410_GPBUP)|(0xF<<18), S3C2410_GPBUP);
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#elif defined CONFIG_SND_SOC_I2S_V32
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/* Configure the I2S pins in correct mode */
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writel(0x0, S3C2450_GPLSEL);
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s3c2410_gpio_cfgpin(S3C2410_GPL4, S3C2450_GPL4_I2S1_SCLK);
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s3c2410_gpio_cfgpin(S3C2410_GPL5, S3C2450_GPL5_I2S1_CDCLK);
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s3c2410_gpio_cfgpin(S3C2410_GPL6, S3C2450_GPL6_I2S1_SDI);
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s3c2410_gpio_cfgpin(S3C2410_GPL7, S3C2450_GPL7_I2S1_SDO);
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s3c2410_gpio_cfgpin(S3C2443_GPJ13, S3C2450_GPJ13_I2S1_LRCK);
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writel(readl(S3C2410_GPLUP)| (0xf<<4), S3C2410_GPLUP);
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writel(readl(S3C2443_GPJDN)| (0x3<<26), S3C2443_GPJDN);
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#else
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printk("Error: S3C2450 I2S configration \n",);
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#endif
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
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} else {
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rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
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}
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/* Working copies of registers */
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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iisfcon = readl(s3c24xx_i2s.regs + S3C2443_IISFIC);
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iiscon |= S3C_IIS0CON_TXDMACTIVE;
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iiscon |= S3C_IIS0CON_RXDMACTIVE;
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iismod &= ~S3C_IIS0MOD_CLK_MASK;
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iismod |= S3C_IIS0MOD_IMS_EXTERNAL_MASTER| S3C_IIS0MOD_INTERNAL_CLK;
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iismod &= ~S3C_IIS0MOD_MODE_MASK;
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iismod |= S3C_IIS0MOD_TXRXMODE;
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/* Multi channel enable */
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iismod &= ~S3C_IIS0MOD_DCE_MASK;
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switch (params_channels(params)) {
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case 6:
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printk("s3c i2s: 5.1channel\n");
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iismod |= S3C_IIS0MOD_DCE_SD1;
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iismod |= S3C_IIS0MOD_DCE_SD2;
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break;
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case 4:
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printk("s3c i2s: 4 channel\n");
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iismod |= S3C_IIS0MOD_DCE_SD1;
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break;
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case 2:
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printk("s3c i2s: 2 channel\n");
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break;
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default:
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printk(KERN_ERR "s3c-i2s-v40: %d channels unsupported\n",
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params_channels(params));
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return -EINVAL;
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}
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/* Set the bit rate */
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#if 0
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iismod &= ~0x6000;
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#endif
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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iismod |= S3C_IIS0MOD_8BIT;
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iismod &= ~S3C_IIS0MOD_BFS_MASK;
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iismod |= S3C_IIS0MOD_32FS;
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iismod &= ~S3C_IIS0MOD_FS_MASK;
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iismod |= S3C_IIS0MOD_384FS;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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iismod &= ~S3C_IIS0MOD_FS_MASK;
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iismod &= ~S3C_IIS0MOD_BFS_MASK;
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iismod |= S3C_IIS0MOD_384FS | S3C_IIS0MOD_32FS;
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iismod &= ~S3C_IIS0MOD_BLC_MASK;
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iismod |= S3C_IIS0MOD_16BIT;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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iismod &= ~S3C_IIS0MOD_FS_MASK;
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iismod &= ~S3C_IIS0MOD_BFS_MASK;
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iismod |= S3C_IIS0MOD_384FS | S3C_IIS0MOD_48FS;
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iismod &= ~S3C_IIS0MOD_BLC_MASK;
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iismod |= S3C_IIS0MOD_24BIT;
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break;
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default:
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return -EINVAL;
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}
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iisfcon |= S3C_IIS_TX_FLUSH;
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iisfcon |= S3C_IIS_RX_FLUSH;
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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iismod &= ~S3C_IIS0MOD_FM_MASK;
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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writel(iisfcon, s3c24xx_i2s.regs + S3C2443_IISFIC);
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/* Tx, Rx fifo flush bit clear */
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iisfcon &= ~(S3C_IIS_TX_FLUSH | S3C_IIS_RX_FLUSH);
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writel(iisfcon, s3c24xx_i2s.regs + S3C2443_IISFIC);
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s3cdbg("s3c iis mode: 0x%08x\n", readl(s3c24xx_i2s.regs + S3C2410_IISMOD));
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s3cdbg("s3c: params_channels %d\n", params_channels(params));
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s3cdbg("s3c: params_format %d\n", params_format(params));
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s3cdbg("s3c: params_subformat %d\n", params_subformat(params));
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s3cdbg("s3c: params_period_size %d\n", params_period_size(params));
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s3cdbg("s3c: params_period_bytes %d\n", params_period_bytes(params));
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s3cdbg("s3c: params_periods %d\n", params_periods(params));
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s3cdbg("s3c: params_buffer_size %d\n", params_buffer_size(params));
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s3cdbg("s3c: params_buffer_bytes %d\n", params_buffer_bytes(params));
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s3cdbg("s3c: params_tick_time %d\n", params_tick_time(params));
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return 0;
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}
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static int s3c_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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int ret = 0;
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s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (!s3c24xx_snd_is_clkmaster()) {
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ret = s3c24xx_snd_lrsync();
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if (ret)
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goto exit_err;
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}
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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s3c24xx_snd_rxctrl(1);
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else
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s3c24xx_snd_txctrl(1);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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s3c24xx_snd_rxctrl(0);
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else
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s3c24xx_snd_txctrl(0);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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exit_err:
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return ret;
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}
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static void s3c64xx_i2s_shutdown(struct snd_pcm_substream *substream)
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{
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unsigned long iiscon;
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iiscon=readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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iiscon &= ~S3C_IIS0CON_I2SACTIVE;
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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}
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/*
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* Set S3C24xx Clock source
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*/
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static int s3c_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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switch (clk_id) {
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case S3C24XX_CLKSRC_PCLK:
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break;
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case S3C24XX_CLKSRC_MPLL:
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break;
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default:
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return -EINVAL;
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}
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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return 0;
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}
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/*
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* Set S3C24xx Clock dividers
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*/
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static int s3c_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
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int div_id, int div)
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{
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u32 reg;
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s3cdbg("Entered %s : div_id = %d, div = %d\n", __FUNCTION__, div_id, div);
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|
|
switch (div_id) {
|
|
case S3C24XX_DIV_MCLK:
|
|
reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_BFS_MASK;
|
|
writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
|
|
break;
|
|
case S3C24XX_DIV_BCLK:
|
|
reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C_IIS0MOD_FS_MASK);
|
|
writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
|
|
break;
|
|
case S3C24XX_DIV_PRESCALER:
|
|
reg = readl(s3c24xx_i2s.regs + S3C2443_IISPSR);
|
|
reg &= ~(S3C_IISPSR_PS_MASK|S3C_IISPSR_PSRAEN);
|
|
writel(reg , s3c24xx_i2s.regs + S3C2443_IISPSR);
|
|
reg |= (div|S3C_IISPSR_PSRAEN);
|
|
writel(reg, s3c24xx_i2s.regs + S3C2443_IISPSR);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* To avoid duplicating clock code, allow machine driver to
|
|
* get the clockrate from here.
|
|
*/
|
|
u32 s3c_i2s_get_clockrate(void)
|
|
{
|
|
return clk_get_rate(s3c24xx_i2s.iis_clk);
|
|
}
|
|
EXPORT_SYMBOL_GPL(s3c_i2s_get_clockrate);
|
|
|
|
static int s3c_i2s_probe(struct platform_device *pdev)
|
|
{
|
|
s3cdbg("Entered %s\n", __FUNCTION__);
|
|
|
|
#if defined CONFIG_SND_SOC_I2S_V32
|
|
s3c24xx_i2s.regs = ioremap(S3C2450_PA_IIS_1, 0x100);
|
|
if (s3c24xx_i2s.regs == NULL)
|
|
return -ENXIO;
|
|
#elif defined CONFIG_SND_SOC_I2S_V40
|
|
s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
|
|
if (s3c24xx_i2s.regs == NULL)
|
|
return -ENXIO;
|
|
#endif
|
|
|
|
s3c24xx_i2s.iis_clk=clk_get(&pdev->dev, "iis");
|
|
if (s3c24xx_i2s.iis_clk == NULL) {
|
|
s3cdbg("failed to get iis_clock\n");
|
|
return -ENODEV;
|
|
}
|
|
clk_enable(s3c24xx_i2s.iis_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int s3c_i2s_suspend(struct platform_device *dev,
|
|
struct snd_soc_cpu_dai *dai)
|
|
{
|
|
s3cdbg("Entered %s\n", __FUNCTION__);
|
|
return 0;
|
|
}
|
|
|
|
static int s3c_i2s_resume(struct platform_device *pdev,
|
|
struct snd_soc_cpu_dai *dai)
|
|
{
|
|
s3cdbg("Entered %s\n", __FUNCTION__);
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define s3c_i2s_suspend NULL
|
|
#define s3c_i2s_resume NULL
|
|
#endif
|
|
|
|
|
|
#define S3C24XX_I2S_RATES \
|
|
(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
|
|
SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
|
|
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
|
|
|
|
struct snd_soc_cpu_dai s3c_i2s_dai = {
|
|
.name = "s3c-i2s",
|
|
.id = 0,
|
|
.type = SND_SOC_DAI_I2S,
|
|
.probe = s3c_i2s_probe,
|
|
.suspend = s3c_i2s_suspend,
|
|
.resume = s3c_i2s_resume,
|
|
.playback = {
|
|
.channels_min = 2,
|
|
.channels_max = 6,
|
|
.rates = S3C24XX_I2S_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,},
|
|
|
|
.capture = {
|
|
.channels_min = 2,
|
|
.channels_max = 6,
|
|
.rates = S3C24XX_I2S_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,},
|
|
|
|
.ops = {
|
|
.shutdown = s3c64xx_i2s_shutdown,
|
|
.trigger = s3c_i2s_trigger,
|
|
.hw_params = s3c_i2s_hw_params,},
|
|
.dai_ops = {
|
|
.set_fmt = s3c_i2s_set_fmt,
|
|
.set_clkdiv = s3c_i2s_set_clkdiv,
|
|
.set_sysclk = s3c_i2s_set_sysclk,
|
|
},
|
|
};
|
|
EXPORT_SYMBOL_GPL(s3c_i2s_dai);
|
|
|
|
/* Module information */
|
|
MODULE_AUTHOR("Ryu, <ryu.real@gmail.com>");
|
|
MODULE_DESCRIPTION("s3c2450 I2S SoC Interface");
|
|
MODULE_LICENSE("GPL");
|