117 lines
3.7 KiB
C
117 lines
3.7 KiB
C
/*
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2008.04.14. All of AP are merged single application and definitin
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in order to be matcing dvs and dfs concept
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These are confirm on SMDK2450, SMDK2416,SMDK6400,SMDK6410
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*/
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#ifndef __S3CDVFS_H_
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#define __S3CDVFS_H_
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#define DVFS_IOCTL_MAGIC 'd'
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typedef struct {
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unsigned int pwr_type; //ARM:ARMV_STEP, INT:INTV_STEP
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unsigned int curr_voltage_arm; //ARM core voltage
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unsigned int curr_voltage_internal; //Internal block voltage
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unsigned int new_voltage;
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unsigned int curr_freq;
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unsigned int freq_divider; // APLL_RATIO + 1
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unsigned int size;
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} s3c_dvfs_info;
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#define DVFS_ON _IO(DVFS_IOCTL_MAGIC, 0)
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#define DVFS_OFF _IO(DVFS_IOCTL_MAGIC, 1)
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#define DVFS_GET_STATUS _IOR(DVFS_IOCTL_MAGIC, 2, s3c_dvfs_info)
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#define DVFS_SET_STATUS _IOW(DVFS_IOCTL_MAGIC, 3, s3c_dvfs_info)
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#define DVFS_MAXNR 4
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/* Board dependency SIGNAL and GPIO configuration */
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#if defined (CONFIG_MACH_SMDK6400) ||defined (CONFIG_MACH_SMDK6410)
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#include <asm/arch/regs-s3c6400-clock.h>
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#include <asm/arch/regs-s3c6410-clock.h>
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#define ARM_LE S3C_GPL8
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#define DVS_OE S3C_GPL9
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#define INT_LE S3C_GPL10
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#define CONTROl_SET(pin,to) s3c_gpio_setpin(pin, to);
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#define ARM_LE_OUTP S3C_GPL8_OUTP
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#define DVS_OE_OUTP S3C_GPL9_OUTP
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#define INT_LE_OUTP S3C_GPL10_OUTP
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#define LTC3714_DATA1 S3C_GPN11
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#define LTC3714_DATA2 S3C_GPN12
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#define LTC3714_DATA3 S3C_GPN13
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#define LTC3714_DATA4 S3C_GPN14
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#define LTC3714_DATA5 S3C_GPN15
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#define LTC3714_OUTP1 S3C_GPN11_OUTP
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#define LTC3714_OUTP2 S3C_GPN12_OUTP
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#define LTC3714_OUTP3 S3C_GPN13_OUTP
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#define LTC3714_OUTP4 S3C_GPN14_OUTP
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#define LTC3714_OUTP5 S3C_GPN15_OUTP
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#define GPIO_CFG(pin,to) s3c_gpio_cfgpin((pin),(to))
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#define GPIO_PULLUP(pin,to) s3c_gpio_pullup((pin),(to))
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#define ARM_PLL_CON S3C_APLL_CON
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#define ARM_CLK_DIV S3C_CLK_DIV0
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#define ARM_DIV_RATIO_BIT 0
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#define ARM_DIV_MASK (0xf<<ARM_DIV_RATIO_BIT)
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#define HCLK_DIV_RATIO_BIT 9
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#define HCLK_DIV_MASK (0x7<<HCLK_DIV_RATIO_BIT)
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#define READ_ARM_DIV ((__raw_readl(ARM_CLK_DIV)&ARM_DIV_MASK) + 1)
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#define PLL_CALC_VAL(MDIV,PDIV,SDIV) ((1<<31)|(MDIV)<<16 |(PDIV)<<8 |(SDIV))
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#define GET_ARM_CLOCK(baseclk) s3c6400_get_pll(__raw_readl(S3C_APLL_CON),baseclk)
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#elif defined (CONFIG_MACH_SMDK2450) ||defined (CONFIG_MACH_SMDK2416) ||defined (CONFIG_MACH_SMDK2443)
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#include <asm/arch/regs-s3c2450-clock.h>
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#include <asm/arch/regs-s3c2416-clock.h>
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#include <asm/arch/regs-s3c2443-clock.h>
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#define ARM_LE S3C2410_GPF5
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#define DVS_OE S3C2410_GPF6
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#define INT_LE S3C2410_GPF7
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#define CONTROl_SET(pin,to) s3c2410_gpio_setpin(pin, to);
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#define ARM_LE_OUTP S3C2410_GPF5_OUTP
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#define DVS_OE_OUTP S3C2410_GPF6_OUTP
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#define INT_LE_OUTP S3C2410_GPF7_OUTP
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#define LTC3714_DATA1 S3C2410_GPC0
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#define LTC3714_DATA2 S3C2410_GPC5
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#define LTC3714_DATA3 S3C2410_GPC6
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#define LTC3714_DATA4 S3C2410_GPC7
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#define LTC3714_DATA5 S3C2410_GPB2
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#define LTC3714_OUTP1 S3C2410_GPC0_OUTP
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#define LTC3714_OUTP2 S3C2410_GPC5_OUTP
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#define LTC3714_OUTP3 S3C2410_GPC6_OUTP
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#define LTC3714_OUTP4 S3C2410_GPC7_OUTP
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#define LTC3714_OUTP5 S3C2410_GPB2_OUTP
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#define GPIO_CFG(pin, fnc) s3c2410_gpio_cfgpin((pin),(fnc))
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#define GPIO_PULLUP(pin, to) s3c2410_gpio_pullup((pin),(to))
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#define ARM_PLL_CON S3C2443_MPLLCON
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#define ARM_CLK_DIV S3C2443_CLKDIV0
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#define MPLL_CON S3C2443_MPLLCON
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#define ARM_DIV_RATIO_BIT 9
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#define ARM_DIV_MASK (0xf<<ARM_DIV_RATIO_BIT)
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#define HCLK_DIV_RATIO_BIT 0
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#define HCLK_DIV_MASK (0x3<<HCLK_DIV_RATIO_BIT)
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#define DVFS_MASK (0x1<<13)
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#define READ_ARM_DIV (((__raw_readl(ARM_CLK_DIV)&ARM_DIV_MASK)>>9) + 1)
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#define PLL_CALC_VAL(MDIV,PDIV,SDIV) ((MDIV)<<14 |(PDIV)<<5 |(SDIV))
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#define GET_ARM_CLOCK(baseclk) s3c2443_get_mpll(__raw_readl(S3C2443_MPLLCON),baseclk)
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#endif
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#endif //__S3CDVS_H_
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