117 lines
3.8 KiB
C
117 lines
3.8 KiB
C
/* linux/include/asm-arm/arch-s3c2410/regs-irq.h
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*
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* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ___ASM_ARCH_REGS_IRQ_H
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#define ___ASM_ARCH_REGS_IRQ_H "$Id: regs-irq.h,v 1.9 2008/04/04 01:49:52 ihlee215 Exp $"
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/* interrupt controller */
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#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
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#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
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#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2)
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#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
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#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
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#define S3C2410_INTMSK S3C2410_IRQREG(0x008)
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#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
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#define S3C2410_PRIORITY S3C2410_IRQREG(0x030)
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#else
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#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C)
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#endif
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#define S3C2410_INTPND S3C2410_IRQREG(0x010)
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#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014)
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#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
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#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
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#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
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#define S3C2450_SRCPND S3C2410_IRQREG(0x040)
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#define S3C2450_INTMOD S3C2410_IRQREG(0x044)
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#define S3C2450_INTMSK S3C2410_IRQREG(0x048)
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#define S3C2450_INTPND S3C2410_IRQREG(0x050)
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#define S3C2450_INTOFFSET S3C2410_IRQREG(0x054)
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#define S3C2450_PRIORITY S3C2410_IRQREG(0x070)
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#endif
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/* mask: 0=enable, 1=disable
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* 1 bit EINT, 4=EINT4, 23=EINT23
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* EINT0,1,2,3 are not handled here.
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*/
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#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
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#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
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#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4)
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#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8)
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#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
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#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
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#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
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/* interrupt controller */
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#define S3C_VIC0REG(x) ((x) + S3C24XX_VA_IRQ)
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#define S3C_VIC1REG(x) ((x) + S3C24XX_VA_IRQ+0x100000)
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#define S3C_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
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#define S3C_EINT0CON0 S3C_EINTREG(0x900)
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#define S3C_EINT0MASK S3C_EINTREG(0x924)
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#define S3C_VIC0IRQSTATUS S3C_VIC0REG(0x000)
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#define S3C_VIC1IRQSTATUS S3C_VIC1REG(0x000)
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#define S3C_VIC0FIQSTATUS S3C_VIC0REG(0x004)
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#define S3C_VIC1FIQSTATUS S3C_VIC1REG(0x004)
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#define S3C_VIC0RAWINTR S3C_VIC0REG(0x008)
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#define S3C_VIC1RAWINTR S3C_VIC1REG(0x008)
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#define S3C_VIC0INTSELECT S3C_VIC0REG(0x00C)
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#define S3C_VIC1INTSELECT S3C_VIC1REG(0x00C)
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#define S3C_VIC0INTENABLE S3C_VIC0REG(0x010)
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#define S3C_VIC1INTENABLE S3C_VIC1REG(0x010)
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#define S3C_VIC0INTENCLEAR S3C_VIC0REG(0x014)
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#define S3C_VIC1INTENCLEAR S3C_VIC1REG(0x014)
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#define S3C_VIC0SOFTINT S3C_VIC0REG(0x018)
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#define S3C_VIC1SOFTINT S3C_VIC1REG(0x018)
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#define S3C_VIC0SOFTINTCLEAR S3C_VIC0REG(0x01C)
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#define S3C_VIC1SOFTINTCLEAR S3C_VIC1REG(0x01C)
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#define S3C_VIC0PROTECTION S3C_VIC0REG(0x020)
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#define S3C_VIC1PROTECTION S3C_VIC1REG(0x020)
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#define S3C_VIC0SWPRIORITYMASK S3C_VIC0REG(0x024)
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#define S3C_VIC1SWPRIORITYMASK S3C_VIC1REG(0x024)
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#define S3C_VIC0PRIORITYDAISY S3C_VIC0REG(0x028)
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#define S3C_VIC1PRIORITYDAISY S3C_VIC1REG(0x028)
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#define S3C_VIC0VECTADDR0 S3C_VIC0REG(0x100)
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#define S3C_VIC1VECTADDR0 S3C_VIC1REG(0x100)
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#define S3C_VIC0VECTADDR1 S3C_VIC0REG(0x104)
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#define S3C_VIC1VECTADDR1 S3C_VIC1REG(0x104)
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#define S3C_VIC0VECTADDR2 S3C_VIC0REG(0x108)
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#define S3C_VIC1VECTADDR2 S3C_VIC1REG(0x108)
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#define S3C_VIC0ADDRESS S3C_VIC0REG(0xF00)
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#define S3C_VIC1ADDRESS S3C_VIC1REG(0xF00)
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#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
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#define S3C_PRIORITY S3C2410_PRIORITY
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#endif
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#endif /* ___ASM_ARCH_REGS_IRQ_H */
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