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cyb4_linux/sound/soc/s3c/smdk2416_rt5624.c

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/*
* smdk2416_rt5624.c -- SoC audio for Neo1973
*
* Copyright 2007 Wolfson Microelectronics PLC.
* Author: Graeme Gregory
* graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
*
* Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Revision history
* 20th Jan 2007 Initial version.
* 05th Feb 2007 Rename all to Neo1973
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <sound/driver.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <asm/mach-types.h>
#include <asm/hardware/scoop.h>
#include <asm/arch/regs-iis.h>
#include <asm/arch/regs-gpio.h>
#include <asm/hardware.h>
#include <asm/arch/audio.h>
#include <asm/io.h>
#include <asm/arch/spi-gpio.h>
//#if !defined(CONFIG_CPU_S3C6400) && !defined(CONFIG_CPU_S3C6410)
//#include <asm/arch/regs-clock.h>
//#else
//#include <asm/arch/regs-s3c6400-clock.h>
//#endif
//////////////////////////
//HIKO : for 2416 setting
//////////////////////////
//#include <asm-arm/arch-s3c2410/regs-s3c6400-clock.h>
//#include <asm-arm/arch-s3c2410/regs-s3c2416-clock.h>
//#include <asm-arm/arch-s3c2410/regs-s3c6410-clock.h>
#include <asm/arch/regs-s3c2450-clock.h>
#include <linux/delay.h>
//#include <asm/arch/regs-s3c6400-clock.h>
//HIKO DEBUG: for REALTEK 5624 on ebook proj
//#include <asm-arm/arch-s3c2410/regs-gpio.h>
#include "../codecs/rt5624.h"
#include "s3c-pcm.h"
#include "s3c-i2s.h"
/* define the scenarios */
#define SMDK6400_AUDIO_OFF 0
#define SMDK6400_CAPTURE_MIC1 3
#define SMDK6400_STEREO_TO_HEADPHONES 2
#define SMDK6400_CAPTURE_LINE_IN 1
#ifdef CONFIG_SND_DEBUG
#define s3cdbg(x...) printk(x)
#else
#define s3cdbg(x...)
#endif
static int smdk6400_hifi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
unsigned int pll_out = 0, bclk = 0;
int ret = 0;
unsigned int iispsr, iismod;
unsigned int prescaler = 4;
unsigned int regs;
printk("Entered %s, rate = %d\n", __FUNCTION__, params_rate(params));
// rt5624_power(true);
// rt5624_i2s_init();
// rt5624_i2c_init();
// mdelay(2000);
//HIKO DEBUG FOR OWN PARM
#if 0
s3cdbg("Entered %s, rate = %d\n", __FUNCTION__, params_rate(params));
/*PCLK & SCLK gating enable*/
//writel(readl(S3C_PCLK_GATE)|S3C_CLKCON_PCLK_IIS0, S3C_PCLK_GATE);
writel((readl(S3C2443_PCLKCON)|(S3C2443_PCLKCON_IIS)), S3C2443_PCLKCON);
//writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_AUDIO0, S3C_SCLK_GATE);
writel((readl(S3C2443_SCLKCON)|(S3C2443_SCLKCON_I2SCLK)), S3C2443_SCLKCON);
//#if 0
//iismod = readl(S3C_IIS0MOD);
iismod = get_iismod();
iismod &=~(0x3<<3);
/*Clear I2S prescaler value [13:8] and disable prescaler*/
//iispsr = readl(S3C_IIS0PSR);
iispsr = get_iispsr();
iispsr &=~((0x3f<<8)|(1<<15));
//writel(iispsr, S3C_IIS0PSR);
set_iispsr(iispsr);
s3cdbg("%s: %d , params = %d \n", __FUNCTION__, __LINE__, params_rate(params));
//#endif //0
switch (params_rate(params)) {
case 8000:
case 16000:
case 32000:
case 64000:
//writel(50332, S3C_EPLL_CON1);
writel(50332, S3C2450_EPLLCON_K);
//writel((1<<31)|(32<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
writel((1<<31)|(32<<16)|(1<<8)|(3<<0) ,S3C2443_EPLLCON);
break;
case 11025:
case 22050:
case 44100:
case 88200:
//writel(10398, S3C_EPLL_CON1);
writel(10398, S3C2450_EPLLCON_K);
//writel((1<<31)|(45<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
writel((1<<31)|(45<<16)|(1<<8)|(3<<0) ,S3C2443_EPLLCON);
break;
case 48000:
case 96000:
//writel(9961, S3C_EPLL_CON1);
writel(9961, S3C2450_EPLLCON_K);
//writel((1<<31)|(49<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
writel((1<<31)|(49<<16)|(1<<8)|(3<<0) ,S3C2443_EPLLCON);
break;
default:
//writel(0, S3C_EPLL_CON1);
writel(0, S3C2450_EPLLCON_K);
//writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0);
writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C2443_EPLLCON);
break;
}
// s3cdbg("%s, IISCON: %x IISMOD: %x,IISFIC: %x,IISPSR: %x",
// __FUNCTION__ , readl(S3C_IIS0CON), readl(S3C_IIS0MOD),
// readl(S3C_IIS0FIC), readl(S3C_IIS0PSR));
s3cdbg("%s, IISCON: %x IISMOD: %x,IISFIC: %x,IISPSR: %x",
__FUNCTION__ , get_iiscon(), get_iismod(),
get_iisfic(), get_iispsr());
//while(!(__raw_readl(S3C_EPLL_CON0)&(1<<30)));
//while(!(__raw_readl(S3C2443_EPLLCON)&(1<<30)));
/* MUXepll : FOUTepll */
//writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
/* AUDIO0 sel : FOUTepll */
//writel((readl(S3C_CLK_SRC)&~(0x7<<7))|(0<<7), S3C_CLK_SRC);
/* CLK_DIV2 setting */
//writel(readl(S3C_CLK_DIV2)&~(0xf<<8),S3C_CLK_DIV2);
iismod |= S3C_IIS0MOD_256FS;
switch (params_rate(params)) {
case 8000:
pll_out = 12288000;
prescaler = 24;
break;
case 11025:
//flove bclk = WM8753_BCLK_DIV_16;
pll_out = 16934400;
prescaler = 24;
break;
case 16000:
//flove bclk = WM8753_BCLK_DIV_2;
pll_out = 12288000;
prescaler = 12;
break;
case 22050:
//flove bclk = WM8753_BCLK_DIV_8;
pll_out = 16934400;
prescaler = 12;
break;
case 32000:
//flove bclk = WM8753_BCLK_DIV_2;
pll_out = 12288000;
prescaler = 6;
break;
case 44100:
//flove bclk = WM8753_BCLK_DIV_4;
pll_out = 16934400;
prescaler = 6;
break;
case 48000:
//flove bclk = WM8753_BCLK_DIV_4;
pll_out = 24576000; //flove011509
prescaler = 6;
break;
case 64000:
//flove bclk = WM8753_BCLK_DIV_4;
pll_out = 18432000;
prescaler = 3;
break;
case 88200:
//flove bclk = WM8753_BCLK_DIV_4;
pll_out = 18432000;
prescaler = 3;
break;
case 96000:
//flove bclk = WM8753_BCLK_DIV_4;
pll_out = 18432000;
prescaler = 3;
break;
default:
//flove bclk = WM8753_BCLK_DIV_2;
pll_out = 12288000;
prescaler = 1;
break;
}
//writel(iismod , S3C_IIS0MOD);
set_iismod(iismod);
/* set codec DAI configuration */
ret = codec_dai->dai_ops.set_fmt(codec_dai,
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS );
if (ret < 0)
return ret;
//#if 0
/* set cpu DAI configuration */
ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS );
if (ret < 0)
return ret;
//#endif //0
/* set the codec system clock for DAC and ADC */
//flove011509_S
#if 1
ret = codec_dai->dai_ops.set_sysclk(codec_dai, 0, pll_out,
SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
#else
#endif
//flove011509_E
/* set MCLK division for sample rate */
ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK,
S3C2410_IISMOD_32FS );
if (ret < 0)
return ret;
/* set codec BCLK division for sample rate */
//flove_mask ret = codec_dai->dai_ops.set_clkdiv(codec_dai, WM8753_BCLKDIV, bclk);
if (ret < 0)
return ret;
/* set prescaler division for sample rate */
ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
((prescaler - 1) << 0x8));
if (ret < 0)
return ret;
#else
//HIKO DEBUG for PCLK clock
// writel((readl(S3C2443_PCLKCON)|(S3C2443_PCLKCON_IIS)), S3C2443_PCLKCON);
/* Select Clock source EPLL */
// regs = ioremap(S3C2410_PA_CLKPWR,0x20);
regs = readl(S3C2443_CLKSRC);
regs &= ~(3<<12);
regs &= ~(3<<14);
regs |= S3C2450_CLKSRC_I2S1_EPLL;
//HIKO DEBUG
regs = (regs & ~(3<<7))|(2<<7);
// regs = (regs & ~(3<<7))|(3<<7);
writel(regs, S3C2443_CLKSRC);
regs |= (1<<6);
writel(regs, S3C2443_CLKSRC);
regs = readl(S3C2443_SCLKCON);
regs |= S3C2443_SCLKCON_I2SCLK_1;
writel(regs, S3C2443_SCLKCON);
//s3cdbg("%s: %d , params = %d \n", __FUNCTION__, __LINE__, params_rate(params));
printk("%s: %d , params = %d \n", __FUNCTION__, __LINE__, params_rate(params));
#if 1
//HIKO DEBUG: 3G with Audio concurrency issue So we let the EPLL source always be 96MHz {
#if 0
switch (params_rate(params)) {
case 8000:
case 16000:
case 32000:
case 48000:
case 64000:
case 96000:
writel(9962, S3C2450_EPLLCON_K);
writel((49<<16)|(1<<8)|(3<<0) ,S3C2443_EPLLCON);
break;
case 11025:
case 22050:
case 44100:
case 88200:
writel(10381, S3C2450_EPLLCON_K);
writel((45<<16)|(1<<8)|(2<<0) ,S3C2443_EPLLCON);
break;
default:
printk("Unsupported rate = %d\n", params_rate(params));
break;
}
#endif //0
//HIKO DEBUG: 3G with Audio concurrency issue So we let the EPLL source always be 96MHz }
//HIKO REVISION
#else
switch (params_rate(params)) {
case 8000:
case 16000:
case 32000:
case 64000:
//writel(50332, S3C_EPLL_CON1);
writel(50332, S3C2450_EPLLCON_K);
//writel((1<<31)|(32<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
writel((1<<31)|(32<<16)|(1<<8)|(3<<0) ,S3C2443_EPLLCON);
break;
case 11025:
case 22050:
case 44100:
case 88200:
//writel(10398, S3C_EPLL_CON1);
writel(10398, S3C2450_EPLLCON_K);
//writel((1<<31)|(45<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
writel((1<<31)|(45<<16)|(1<<8)|(3<<0) ,S3C2443_EPLLCON);
break;
case 48000:
case 96000:
//writel(9961, S3C_EPLL_CON1);
writel(9961, S3C2450_EPLLCON_K);
//writel((1<<31)|(49<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
writel((1<<31)|(49<<16)|(1<<8)|(3<<0) ,S3C2443_EPLLCON);
break;
default:
//writel(0, S3C_EPLL_CON1);
writel(0, S3C2450_EPLLCON_K);
//writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0);
writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C2443_EPLLCON);
break;
}
#endif //0
#if 1
switch (params_rate(params)) {
case 8000:
// bclk = WM8753_BCLK_DIV_16;
pll_out = 18432000;
prescaler = 24;
break;
case 11025:
// bclk = WM8753_BCLK_DIV_16;
pll_out = 16934400;
prescaler = 32;
break;
case 16000:
// bclk = WM8753_BCLK_DIV_8;
pll_out = 18432000;
prescaler = 12;
break;
case 22050:
// bclk = WM8753_BCLK_DIV_2;
pll_out = 16934400;
prescaler = 16;
break;
case 32000:
// bclk = WM8753_BCLK_DIV_4;
pll_out = 18432000;
prescaler = 6;
break;
case 44100:
// bclk = WM8753_BCLK_DIV_4;
pll_out = 16934400;
prescaler = 8;
break;
case 48000:
// bclk = WM8753_BCLK_DIV_4;
pll_out = 18432000;
prescaler = 4;
break;
case 64000:
// bclk = WM8753_BCLK_DIV_4;
pll_out = 18432000;
prescaler = 3;
break;
case 88200:
// bclk = WM8753_BCLK_DIV_4;
pll_out = 16934400;
prescaler = 4;
break;
case 96000:
// bclk = WM8753_BCLK_DIV_4;
pll_out = 18432000;
prescaler = 2;
break;
}
//HIKO REVISION
#else
switch (params_rate(params)) {
case 8000:
pll_out = 12288000;
prescaler = 24;
break;
case 11025:
//flove bclk = WM8753_BCLK_DIV_16;
pll_out = 16934400;
prescaler = 24;
break;
case 16000:
//flove bclk = WM8753_BCLK_DIV_2;
pll_out = 12288000;
prescaler = 12;
break;
case 22050:
//flove bclk = WM8753_BCLK_DIV_8;
pll_out = 16934400;
prescaler = 12;
break;
case 32000:
//flove bclk = WM8753_BCLK_DIV_2;
pll_out = 12288000;
prescaler = 6;
break;
case 44100:
//flove bclk = WM8753_BCLK_DIV_4;
pll_out = 16934400;
prescaler = 6;
break;
case 48000:
//flove bclk = WM8753_BCLK_DIV_4;
pll_out = 24576000; //flove011509
prescaler = 6;
break;
case 64000:
//flove bclk = WM8753_BCLK_DIV_4;
pll_out = 18432000;
prescaler = 3;
break;
case 88200:
//flove bclk = WM8753_BCLK_DIV_4;
pll_out = 18432000;
prescaler = 3;
break;
case 96000:
//flove bclk = WM8753_BCLK_DIV_4;
pll_out = 18432000;
prescaler = 3;
break;
default:
//flove bclk = WM8753_BCLK_DIV_2;
pll_out = 12288000;
prescaler = 1;
break;
}
#endif //0
/* set codec DAI configuration */
ret = codec_dai->dai_ops.set_fmt(codec_dai,
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS );
if (ret < 0)
return ret;
/* set cpu DAI configuration */
ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS );
if (ret < 0)
return ret;
#if 0
/* set the codec system clock for DAC and ADC */
ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8753_MCLK, pll_out, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
#else
//HIKO: for faster clock rate
ret = codec_dai->dai_ops.set_sysclk(codec_dai, 0, pll_out, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
#endif //0
/* set MCLK division for sample rate */
//HIKO: for faster clock rate
//BFS
//Bit clock frequency select.
//00 = 32 fs, where fs is sampling frequency
//01 = 48 fs
//10 = 16 fs
//11 = 24 fs
//(Even in the slave mode, this bit should be set for correct)
//HIKO: for faster clock rate
// ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK, S3C2410_IISMOD_32FS );
// ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK, 1<<1/*48fs BFS*/);
ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK, 0<<1/*32fs BFS*/);
if (ret < 0)
return ret;
/* set BCLK division for sample rate */
//RFS
//IIS root clock (codec clock) frequency select.
//00 = 256 fs, where fs is sampling frequency
//01 = 512 fs
//10 = 384 fs
//11 = 768 fs
//(Even in the slave mode, this bit should be set for correct)
//HIKO: for faster clock rate
// ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_BCLK, 0<<3/*256fs RFS*/);
// ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_BCLK, 2<<3/*384fs RFS*/);
if (ret < 0)
return ret;
#if 1
//HIKO: for faster clock rate
// ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, ((prescaler - 1) << 0x8));
// ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, ((prescaler/2 - 1) << 0x8));
// ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, ((prescaler/2) << 0x8));
// ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, ((prescaler/2) << 0x8));
//HIKO DEBUG: 3G with Audio concurrency issue So we let the EPLL source always be 96MHz {
ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, (prescaler-1 << 0x8));
//HIKO DEBUG: 3G with Audio concurrency issue So we let the EPLL source always be 96MHz }
if (ret < 0)
return ret;
#endif //0
#endif //HIKO DEBUG FOR OWN PARM
return 0;
}
static int smdk6400_hifi_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
/* disable the PLL */
//flove_mask return codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL1, 0, 0);
return 0;
}
/*
* Neo1973 RT5624 HiFi DAI opserations.
*/
static struct snd_soc_ops smdk6400_hifi_ops = {
.hw_params = smdk6400_hifi_hw_params,
.hw_free = smdk6400_hifi_hw_free,
};
static int smdk6400_scenario = 0;
static int smdk6400_get_scenario(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.integer.value[0] = smdk6400_scenario;
return 0;
}
static int set_scenario_endpoints(struct snd_soc_codec *codec, int scenario)
{
switch(smdk6400_scenario) {
case SMDK6400_AUDIO_OFF:
snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
break;
case SMDK6400_STEREO_TO_HEADPHONES:
snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
break;
case SMDK6400_CAPTURE_MIC1:
snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
break;
case SMDK6400_CAPTURE_LINE_IN:
snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
break;
default:
snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
break;
}
snd_soc_dapm_sync_endpoints(codec);
return 0;
}
static int smdk6400_set_scenario(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
if (smdk6400_scenario == ucontrol->value.integer.value[0])
return 0;
smdk6400_scenario = ucontrol->value.integer.value[0];
set_scenario_endpoints(codec, smdk6400_scenario);
return 1;
}
static const struct snd_soc_dapm_widget rt5624_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Mic1 Jack", NULL),
SND_SOC_DAPM_LINE("Line In Jack", NULL),
};
/* example machine audio_mapnections */
static const char* audio_map[][3] = {
{"Headphone Jack", NULL, "LOUT1"},
{"Headphone Jack", NULL, "ROUT1"},
/* mic is connected to mic1 - with bias */
/* mic is connected to mic1 - with bias */
{"MIC1", NULL, "Mic1 Jack"},
{"LINE1", NULL, "Line In Jack"},
{"LINE2", NULL, "Line In Jack"},
/* Connect the ALC pins */
{"ACIN", NULL, "ACOP"},
{NULL, NULL, NULL},
};
static const char *smdk_scenarios[] = {
"Off",
"Capture Line In",
"Headphones",
"Capture Mic1",
};
static const struct soc_enum smdk_scenario_enum[] = {
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(smdk_scenarios),smdk_scenarios),
};
static const struct snd_kcontrol_new rt5624_smdk6400_controls[] = {
SOC_ENUM_EXT("SMDK Mode", smdk_scenario_enum[0],
smdk6400_get_scenario, smdk6400_set_scenario),
};
/*
* This is an example machine initialisation for a rt5624 connected to a
* smdk6400. It is missing logic to detect hp/mic insertions and logic
* to re-route the audio in such an event.
*/
static int smdk6400_rt5624_init(struct snd_soc_codec *codec)
{
int i, err;
printk("[HIKO]smdk6400_rt5624_init()\n");
/* set endpoints to default mode */
set_scenario_endpoints(codec, SMDK6400_AUDIO_OFF);
/* Add smdk6400 specific widgets */
for (i = 0; i < ARRAY_SIZE(rt5624_dapm_widgets); i++)
snd_soc_dapm_new_control(codec, &rt5624_dapm_widgets[i]);
/* add smdk6400 specific controls */
for (i = 0; i < ARRAY_SIZE(rt5624_smdk6400_controls); i++) {
err = snd_ctl_add(codec->card,
snd_soc_cnew(&rt5624_smdk6400_controls[i],
codec, NULL));
if (err < 0)
return err;
}
/* set up smdk6400 specific audio path audio_mapnects */
for (i = 0; audio_map[i][0] != NULL; i++) {
snd_soc_dapm_connect_input(codec, audio_map[i][0],
audio_map[i][1], audio_map[i][2]);
}
/* always connected */
snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
snd_soc_dapm_sync_endpoints(codec);
return 0;
}
static struct snd_soc_dai_link smdk6400_dai[] = {
{ /* Hifi Playback - for similatious use with voice below */
.name = "RT5624",
.stream_name = "RT5624 HiFi",
.cpu_dai = &s3c_i2s_dai,
.codec_dai = &rt5624_dai,//flove011209 &wm8753_dai[WM8753_DAI_HIFI],
.init = smdk6400_rt5624_init,
.ops = &smdk6400_hifi_ops,
},
};
static struct snd_soc_machine smdk6400 = {
.name = "smdk2416",
.dai_link = smdk6400_dai,
.num_links = ARRAY_SIZE(smdk6400_dai),
};
static struct rt5624_setup_data smdk6400_rt5624_setup = { //flove011509
.i2c_address = 0x18,
// .i2c_address = 0x30,
// .i2c_address = 0x19,
};
static struct snd_soc_device smdk6400_snd_devdata = {
.machine = &smdk6400,
.platform = &s3c24xx_soc_platform,
.codec_dev = &soc_codec_dev_rt5624,//flovesoc_codec_dev_wm8753,
.codec_data = &smdk6400_rt5624_setup,
};
static struct platform_device *smdk6400_snd_device;
static int __init smdk6400_init(void)
{
int ret;
smdk6400_snd_device = platform_device_alloc("soc-audio", -1);
if (!smdk6400_snd_device)
return -ENOMEM;
platform_set_drvdata(smdk6400_snd_device, &smdk6400_snd_devdata);
smdk6400_snd_devdata.dev = &smdk6400_snd_device->dev;
ret = platform_device_add(smdk6400_snd_device);
if (ret)
platform_device_put(smdk6400_snd_device);
return ret;
}
static void __exit smdk6400_exit(void)
{
platform_device_unregister(smdk6400_snd_device);
}
/*
** The I2S init process for RT5624
*/
void rt5624_i2s_init()
{
void __iomem *regs;
printk("[HIKO]rt5624_i2s_init()\n");
//////////////////////////////////////////////////
//HIKO DEBUG: init process for REALTEK 5624
//////////////////////////////////////////////////
//Original setting for CPU Master mode
#if 1
//AUDIO [i2s] LRCK setting
s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
//AUDIO [i2s] BCLK setting
s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
//[HIKO] Realtek Charles suggestion for CPU Slave mode
#else
//AUDIO [i2s] LRCK setting
s3c2410_gpio_setpin(S3C2410_GPE0, 0);
s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_INP);
s3c2410_gpio_pullup(S3C2410_GPE0, 0);
//AUDIO [i2s] BCLK setting
s3c2410_gpio_setpin(S3C2410_GPE1, 0);
s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_INP);
s3c2410_gpio_pullup(S3C2410_GPE1, 0);
#endif
//AUDIO [i2s] DACDAT setting
s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
#if defined(CONFIG_QISDA_AS090B00_EVT1)||defined(CONFIG_QISDA_AS090B00_EVT1_1) || defined(CONFIG_QISDA_QD060N00_DVT1_1) || defined(CONFIG_QISDA_QD090B00_EVT1) || defined(CONFIG_QISDA_E600_DVT1)
printk("[HIKO rt5624] AS090B00 i2s Input MIC Setting\n");
//AUDIO [i2s] Input Mic setting
s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
#endif //CONFIG_QISDA_AS090B00_EVT1
//AUDIO [i2s] MCLK setting
s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
//MCLK 11MHz
// s3c_i2s_set_iispcr_clkdiv_rt5624(5);
//BCLK
//s3c_i2s_set_iisclk_clkdiv_rt5624(0);
regs = ioremap(S3C2410_PA_IIS, 0x100);
writel(S3C2410_IISCON_IISEN, regs + S3C2410_IISCON);
//HIKO DEBUG: Setting the LRCK to be correct mode
#if 0
{
u32 curr_reg;
curr_reg = get_iismod();
curr_reg &= ~(0x3<<16);
curr_reg |= 0x2<<16;
set_iismod(curr_reg);
}
#endif //0
// udelay(10);
}
EXPORT_SYMBOL_GPL(rt5624_i2s_init);
/*
** The I2S init process for RT5624
*/
void rt5624_i2s_release()
{
void __iomem *regs;
printk("[HIKO]rt5624_i2s_release()\n");
//////////////////////////////////////////////////
//HIKO DEBUG: init process for REALTEK 5624
//////////////////////////////////////////////////
//AUDIO [i2s] LRCK setting
s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_OUTP);
s3c2410_gpio_setpin(S3C2410_GPE0, 0);
//AUDIO [i2s] BCLK setting
s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_OUTP);
s3c2410_gpio_setpin(S3C2410_GPE1, 0);
//AUDIO [i2s] DACDAT setting
s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_OUTP);
s3c2410_gpio_setpin(S3C2410_GPE4, 0);
//AUDIO [i2s] MCLK setting
s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_OUTP);
s3c2410_gpio_setpin(S3C2410_GPE2, 0);
//MCLK 11MHz
// s3c_i2s_set_iispcr_clkdiv_rt5624(5);
//BCLK
//s3c_i2s_set_iisclk_clkdiv_rt5624(0);
regs = ioremap(S3C2410_PA_IIS, 0x100);
writel(S3C2410_IISCON_IISEN, regs + S3C2410_IISCON);
// udelay(10);
}
EXPORT_SYMBOL_GPL(rt5624_i2s_release);
/*
** The I2C init process for RT5624
*/
void rt5624_i2c_init()
{
printk("[HIKO]rt5624_i2c_init()\n");
s3c2410_gpio_pullup(S3C2410_GPE14, 0);
s3c2410_gpio_pullup(S3C2410_GPE15, 0);
//AUDIO [i2c] SCLK setting
s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
//AUDIO [i2c] SDA setting
s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
}
EXPORT_SYMBOL_GPL(rt5624_i2c_init);
/*
** The I2C release process for RT5624
*/
void rt5624_i2c_release()
{
printk("[HIKO]rt5624_i2c_release()\n");
//AUDIO [i2c] SCLK setting
s3c2410_gpio_pullup(S3C2410_GPE14, 0);
s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_INP);
//AUDIO [i2c] SDA setting
s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_INP);
s3c2410_gpio_pullup(S3C2410_GPE15, 0);
}
EXPORT_SYMBOL_GPL(rt5624_i2c_release);
/*
** The AUDIO RESET PIN on process for RT5624
*/
void rt5624_audio_reset_on()
{
printk("[HIKO]rt5624_audio_reset_on()\n");
s3c2410_gpio_cfgpin(S3C2410_GPA1, S3C2410_GPA1_OUT);
s3c2410_gpio_setpin(S3C2410_GPA1, 1);
}
EXPORT_SYMBOL_GPL(rt5624_audio_reset_on);
/*
** The AUDIO RESET PIN OFF process for RT5624
*/
void rt5624_audio_reset_off()
{
printk("[HIKO]rt5624_audio_reset_off()\n");
//AUDIO [i2c] SCLK setting
s3c2410_gpio_cfgpin(S3C2410_GPA1, S3C2410_GPA1_OUT);
s3c2410_gpio_setpin(S3C2410_GPA1, 0);
}
EXPORT_SYMBOL_GPL(rt5624_audio_reset_off);
/*
** The AUDIO SW on/off process for RT5624
*/
void rt5624_power(bool on)
{
// void __iomem *regs;
printk("[HIKO]rt5624_power(%x)\n", on);
if (on) {
//AUDIO Enable pin
s3c2410_gpio_cfgpin(S3C2410_GPB10, S3C2410_GPB10_OUTP);
s3c2410_gpio_setpin(S3C2410_GPB10, 1);
} else {
//AUDIO Disable pin
s3c2410_gpio_cfgpin(S3C2410_GPB10, S3C2410_GPB10_OUTP);
s3c2410_gpio_setpin(S3C2410_GPB10, 0);
}
}
EXPORT_SYMBOL_GPL(rt5624_power);
struct platform_device *get_rt5624_pdev()
{
return (struct platform_device *)smdk6400_snd_device;
}
EXPORT_SYMBOL_GPL(get_rt5624_pdev);
module_init(smdk6400_init);
module_exit(smdk6400_exit);
/* Module information */
MODULE_AUTHOR("flove");
MODULE_DESCRIPTION("ALSA SoC rt5624 Neo1973");
MODULE_LICENSE("GPL");
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