mirror of
https://github.com/clockworkpi/DevTerm.git
synced 2025-12-12 18:28:50 +01:00
add a04 armbian build system patches and configs
This commit is contained in:
cuu
parent
28c2b90244
commit
1d6e44ce12
@ -0,0 +1,7 @@
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# Allwinner H6 quad core 2GB RAM SoC GBE USB3
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BOARD_NAME="Clockworkpi A04"
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BOARDFAMILY="sun50iw6"
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BOOTCONFIG="clockworkpi-a04-h6_defconfig"
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KERNEL_TARGET="legacy,current,edge"
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FULL_DESKTOP="yes"
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ATFBRANCH="tag:v2.2"
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,672 @@
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diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
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index f15fb2eea..68f6e913e 100644
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--- a/arch/arm64/boot/dts/allwinner/Makefile
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+++ b/arch/arm64/boot/dts/allwinner/Makefile
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@@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-m1-plus2.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
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+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-clockworkpi-a04.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-clockworkpi-a04.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-clockworkpi-a04.dts
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new file mode 100644
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index 000000000..91b6ee040
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-clockworkpi-a04.dts
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@@ -0,0 +1,465 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
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+
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+/dts-v1/;
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+
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+#include "sun50i-h6.dtsi"
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+#include "sun50i-h6-cpu-opp.dtsi"
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ model = "Clockworkpi A04";
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+ compatible = "clockwork,devterm-a04", "allwinner,sun50i-h6";
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+
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+ aliases {
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+ serial0 = &uart0;
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+ serial1 = &uart1;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ connector {
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+ compatible = "hdmi-connector";
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+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
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+ type = "d";
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+
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+ port {
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+ hdmi_con_in: endpoint {
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+ remote-endpoint = <&hdmi_out_con>;
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+ };
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+ };
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+ };
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+
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+ ext_osc32k: ext_osc32k_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <32768>;
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+ clock-output-names = "ext_osc32k";
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+ };
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+
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+ reg_vcc5v: vcc5v {
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+ /* board wide 5V supply directly from the DC jack */
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc-5v";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-always-on;
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+ };
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+
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+ reg_vcc33_wifi: vcc33-wifi {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc33-wifi";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-always-on;
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+ vin-supply = <®_vcc5v>;
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+ };
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+
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+ reg_vcc_wifi_io: vcc-wifi-io {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc-wifi-io";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-always-on;
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+ vin-supply = <®_vcc33_wifi>;
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+ };
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+
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+ reg_vdd_gpu: vdd-gpu {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vdd-gpu";
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+ regulator-min-microvolt = <1080000>;
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+ regulator-max-microvolt = <1080000>;
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+ regulator-always-on;
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+ };
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+
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+ reg_vdd12: vdd-12 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vdd-12";
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+ regulator-min-microvolt = <1200000>;
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+ regulator-max-microvolt = <1200000>;
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+ regulator-always-on;
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+ };
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+
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+ wifi_pwrseq: wifi-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ clocks = <&rtc 1>;
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+ clock-names = "ext_clock";
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+ reset-gpios = <&pio 2 0 GPIO_ACTIVE_LOW>;
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+ post-power-on-delay-ms = <200>;
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+ };
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+
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+ battery: battery@0 {
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+ compatible = "simple-battery";
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+ constant-charge-current-max-microamp = <2100000>;
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+ voltage-min-design-microvolt = <3300000>;
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+ };
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+
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+ ocp8178_backlight: backlight@0 {
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+ compatible = "ocp8178-backlight";
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+ backlight-control-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>;
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+ default-brightness = <5>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&backlight_control>;
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+ };
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+
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+ panel {
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+ compatible = "clockwork,cpi3-lcd";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&lcd_pins>;
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+ status = "okay";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ port@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ dsi_bridge_in: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&tcon_lcd_out_bridge>;
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+ };
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+ };
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+ };
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+ };
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+
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+ ac200-sound {
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+ status = "okay";
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+ compatible = "simple-audio-card";
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+ simple-audio-card,format = "i2s";
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+ simple-audio-card,frame-master = <&i2s3_master>;
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+ simple-audio-card,bitclock-master = <&i2s3_master>;
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+ simple-audio-card,name = "allwinner,ac200-codec";
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+ simple-audio-card,mclk-fs = <512>;
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+ i2s3_master: simple-audio-card,cpu {
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+ sound-dai = <&i2s3>;
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+ system-clock-frequency = <22579200>;
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+ dai-tdm-slot-num = <2>;
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+ dai-tdm-slot-width = <32>;
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+ };
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+ simple-audio-card,codec {
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+ sound-dai = <&ac200_codec>;
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+ system-clock-frequency = <22579200>;
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+ dai-tdm-slot-num = <2>;
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+ dai-tdm-slot-width = <32>;
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+ };
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+ };
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+
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+ ac200_codec_spk: ac200_codec_spk {
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+ compatible = "allwinner,ac200_codec";
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+ gpio-switch = <&pio 2 12 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
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+ };
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+
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+};
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+
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+&de {
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+ status = "okay";
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+};
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+
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+&gpu {
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+ mali-supply = <®_vdd_gpu>;
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+ status = "okay";
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+};
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+
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+&hdmi {
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+ status = "okay";
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+};
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+
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+&hdmi_sound {
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+ status = "okay";
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+};
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+
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+&i2s1 {
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+// status = "okay";
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+};
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+
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+&i2s3 {
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+ status = "okay";
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+};
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+
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+&pwm {
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+ status = "okay";
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+};
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+
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+&ac200_pwm_clk {
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+ status = "okay";
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+};
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+
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+&hdmi_out {
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+ hdmi_out_con: endpoint {
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+ remote-endpoint = <&hdmi_con_in>;
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+ };
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+};
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+
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+&mmc0 {
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+ vmmc-supply = <®_vcc33_wifi>;
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+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
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+ bus-width = <4>;
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+ status = "okay";
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+};
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+
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+&mmc1 {
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+ vmmc-supply = <®_dldo1>;
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+ vqmmc-supply = <®_aldo3>;
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+ mmc-pwrseq = <&wifi_pwrseq>;
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+ bus-width = <4>;
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+ non-removable;
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+ status = "okay";
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+
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+ brcm: sdio-wifi@1 {
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+ reg = <1>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <2 1 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "host-wake";
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+ };
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+};
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+
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+&pio {
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+ vcc-pc-supply = <®_vcc_wifi_io>;
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+ vcc-pd-supply = <®_vcc33_wifi>;
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+ vcc-pg-supply = <®_vcc_wifi_io>;
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+
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+ panel_reset: panel-reset {
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+ pins = "PC5", "PC10", "PC13";
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+ function = "gpio_out";
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+ };
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+
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+ backlight_control: backlight-control {
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+ pins = "PC6";
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+ function = "gpio_out";
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+ };
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+
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+ lcd_pins: lcd-pin {
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+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
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+ "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
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+ "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
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+ "PD18", "PD19", "PD20", "PD21";
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+ function = "lcd0";
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+ };
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+
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+};
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+
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+&r_pio {
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+
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+};
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+
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+&rtc {
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+ clocks = <&ext_osc32k>;
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+};
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+
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+&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_ph_pins>;
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
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+ uart-has-rtscts;
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+ status = "okay";
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+
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+ bluetooth {
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+ compatible = "brcm,bcm4345c5";
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+ clocks = <&rtc 1>;
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+ clock-names = "lpo";
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+ device-wakeup-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
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+ host-wakeup-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
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+ shutdown-gpios = <&pio 2 2 GPIO_ACTIVE_HIGH>; /* PC2*/
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+ max-speed = <1500000>;
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+ };
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+};
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+
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+&dwc3 {
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+ status = "okay";
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+};
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+
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+&ohci0 {
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+ status = "okay";
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+};
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+
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+&ohci3 {
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+ status = "okay";
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+};
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+
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+&ehci0 {
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+ status = "okay";
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+};
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+
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+&ehci3 {
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+ status = "okay";
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+};
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+
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+&usb2otg {
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+ dr_mode = "peripheral";
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+ status = "okay";
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+};
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+
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+&usb2phy {
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+ usb0_id_det-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>;
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+ usb0_vbus-supply = <®_vcc5v>;
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+ usb3_vbus-supply = <®_vcc5v>;
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+ status = "okay";
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+};
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+
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+&usb3phy {
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+
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+ axp22x: pmic@34 {
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ compatible = "x-powers,axp221";
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+ reg = <0x34>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <7 7 IRQ_TYPE_LEVEL_LOW>;
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+
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+ regulators {
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+
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+ x-powers,dcdc-freq = <3000>;
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+
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+ reg_aldo1: aldo1 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "audio-vdd";
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+ };
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+
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+ reg_aldo2: aldo2 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "display-vcc";
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+ };
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+
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+ reg_aldo3: aldo3 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-name = "wifi-vdd";
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+ };
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+
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+ reg_dldo1: dldo1 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "wifi-vcc1";
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+ };
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+
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+ reg_dldo2: dldo2 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "dldo2";
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+ };
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+
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+ reg_dldo3: dldo3 {
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+ regulator-always-on;
|
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+ regulator-min-microvolt = <3300000>;
|
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+ regulator-max-microvolt = <3300000>;
|
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+ regulator-name = "dldo3";
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+ };
|
||||
+
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+ reg_dldo4: dldo4 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
|
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+ regulator-name = "dldo4";
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+ };
|
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+
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+ reg_eldo1: eldo1 {
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+ regulator-always-on;
|
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "wifi-vcc2";
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+ };
|
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+
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+ reg_eldo2: eldo2 {
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+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "wifi-vcc3";
|
||||
+ };
|
||||
+
|
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+ reg_eldo3: eldo3 {
|
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+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "wifi-vcc4";
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+
|
||||
+ battery_power_supply: battery-power-supply {
|
||||
+ compatible = "x-powers,axp221-battery-power-supply";
|
||||
+ monitored-battery = <&battery>;
|
||||
+ };
|
||||
+
|
||||
+ ac_power_supply: ac_power_supply {
|
||||
+ compatible = "x-powers,axp221-ac-power-supply";
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c2 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ dsi_bridge: tc358778@e {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ compatible = "cw,cwd686";
|
||||
+ reg = <0xe>;
|
||||
+
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&panel_reset>;
|
||||
+ reset-gpios = <&pio 2 10 GPIO_ACTIVE_HIGH>;
|
||||
+ power-gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c3 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcon_lcd {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ ports {
|
||||
+ tcon_lcd_out: port@1 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <1>;
|
||||
+
|
||||
+ tcon_lcd_out_bridge: endpoint@0 {
|
||||
+ reg = <0>;
|
||||
+ remote-endpoint = <&dsi_bridge_in>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&tcon_tv {
|
||||
+// status = "okay";
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&spi1 {
|
||||
+ status = "okay";
|
||||
+ spidev@0 {
|
||||
+ compatible = "spidev";
|
||||
+ reg = <0x0>;
|
||||
+ spi-max-frequency = <1000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
|
||||
index fac732484..9e5edb8a7 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
|
||||
@@ -80,7 +80,7 @@
|
||||
|
||||
de: display-engine {
|
||||
compatible = "allwinner,sun50i-h6-display-engine";
|
||||
- allwinner,pipelines = <&mixer0>;
|
||||
+ allwinner,pipelines = <&mixer0 &mixer1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -201,6 +201,31 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ mixer1: mixer@200000 {
|
||||
+ compatible = "allwinner,sun50i-h6-de3-mixer-1";
|
||||
+ reg = <0x200000 0x100000>;
|
||||
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
|
||||
+ <&display_clocks CLK_MIXER1>;
|
||||
+ clock-names = "bus",
|
||||
+ "mod";
|
||||
+ resets = <&display_clocks RST_MIXER1>;
|
||||
+ iommus = <&iommu 1>;
|
||||
+
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ mixer1_out: port@1 {
|
||||
+ reg = <1>;
|
||||
+
|
||||
+ mixer1_out_tcon_top_mixer1: endpoint {
|
||||
+ remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
};
|
||||
|
||||
video-codec@1c0e000 {
|
||||
@@ -426,6 +451,11 @@
|
||||
function = "i2c3";
|
||||
};
|
||||
|
||||
+ ac200_pins: ac200-pins {
|
||||
+ pins = "PB0";
|
||||
+ function = "ccir";
|
||||
+ };
|
||||
+
|
||||
mmc0_pins: mmc0-pins {
|
||||
pins = "PF0", "PF1", "PF2", "PF3",
|
||||
"PF4", "PF5";
|
||||
@@ -522,6 +552,11 @@
|
||||
pins = "PD25", "PD26";
|
||||
function = "uart3";
|
||||
};
|
||||
+
|
||||
+ i2s3_pins: i2s3-pins {
|
||||
+ pins = "PB12", "PB13", "PB14", "PB15", "PB16";
|
||||
+ function = "i2s3";
|
||||
+ };
|
||||
};
|
||||
|
||||
iommu: iommu@30f0000 {
|
||||
@@ -724,6 +759,8 @@
|
||||
interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&ac200_pins>;
|
||||
|
||||
ac200_ephy: phy {
|
||||
compatible = "x-powers,ac200-ephy";
|
||||
@@ -732,6 +769,12 @@
|
||||
nvmem-cell-names = "calibration";
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+ ac200_codec: codec {
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ compatible = "x-powers,ac200-codec";
|
||||
+ status = "okay";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
||||
@@ -768,6 +811,21 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ i2s3: i2s@508f000 {
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ compatible = "allwinner,sun50i-h6-i2s";
|
||||
+ reg = <0x0508f000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&ccu CLK_BUS_I2S3>, <&ccu CLK_I2S3>;
|
||||
+ clock-names = "apb", "mod";
|
||||
+ dmas = <&dma 6>, <&dma 6>;
|
||||
+ resets = <&ccu RST_BUS_I2S3>;
|
||||
+ dma-names = "rx", "tx";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2s3_pins>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
spdif: spdif@5093000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "allwinner,sun50i-h6-spdif";
|
||||
@@ -928,7 +986,7 @@
|
||||
reg = <0>;
|
||||
|
||||
hdmi_in_tcon_top: endpoint {
|
||||
- remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
|
||||
+ remote-endpoint = <&tcon_tv_out_tcon_top>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -985,22 +1043,49 @@
|
||||
};
|
||||
};
|
||||
|
||||
- tcon_top_hdmi_in: port@4 {
|
||||
+ tcon_top_mixer1_in: port@2 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <2>;
|
||||
+
|
||||
+ tcon_top_mixer1_in_mixer1: endpoint@1 {
|
||||
+ reg = <1>;
|
||||
+ remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tcon_top_mixer1_out: port@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
- reg = <4>;
|
||||
+ reg = <3>;
|
||||
|
||||
- tcon_top_hdmi_in_tcon_tv: endpoint@0 {
|
||||
+ tcon_top_mixer1_out_tcon_lcd: endpoint@0 {
|
||||
reg = <0>;
|
||||
- remote-endpoint = <&tcon_tv_out_tcon_top>;
|
||||
+ remote-endpoint = <&tcon_lcd_in_tcon_top_mixer1>;
|
||||
};
|
||||
};
|
||||
+ };
|
||||
+ };
|
||||
|
||||
- tcon_top_hdmi_out: port@5 {
|
||||
- reg = <5>;
|
||||
+ tcon_lcd: lcd-controller@6511000 {
|
||||
+ compatible = "allwinner,sun50i-h6-tcon-lcd";
|
||||
+ reg = <0x06511000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&ccu CLK_BUS_TCON_LCD0>, <&ccu CLK_TCON_LCD0>;
|
||||
+ clock-names = "ahb", "tcon-ch0";
|
||||
+ clock-output-names = "tcon-lcd-sclk";
|
||||
+ resets = <&ccu RST_BUS_TCON_LCD0>;
|
||||
+ reset-names = "lcd";
|
||||
|
||||
- tcon_top_hdmi_out_hdmi: endpoint {
|
||||
- remote-endpoint = <&hdmi_in_tcon_top>;
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ tcon_lcd_in: port@0 {
|
||||
+ reg = <0>;
|
||||
+
|
||||
+ tcon_lcd_in_tcon_top_mixer1: endpoint@0 {
|
||||
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1037,7 +1122,7 @@
|
||||
|
||||
tcon_tv_out_tcon_top: endpoint@1 {
|
||||
reg = <1>;
|
||||
- remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
|
||||
+ remote-endpoint = <&hdmi_in_tcon_top>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,95 @@
|
||||
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
|
||||
index 17fecb156..2409b5ee1 100644
|
||||
--- a/drivers/mfd/axp20x.c
|
||||
+++ b/drivers/mfd/axp20x.c
|
||||
@@ -1644,6 +1644,7 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ pm_power_off = 0;
|
||||
if (!pm_power_off) {
|
||||
axp20x_pm_power_off = axp20x;
|
||||
pm_power_off = axp20x_power_off;
|
||||
diff --git a/drivers/power/supply/axp20x_ac_power.c b/drivers/power/supply/axp20x_ac_power.c
|
||||
index ac360016b..c11024f3c 100644
|
||||
--- a/drivers/power/supply/axp20x_ac_power.c
|
||||
+++ b/drivers/power/supply/axp20x_ac_power.c
|
||||
@@ -53,6 +53,9 @@ static irqreturn_t axp20x_ac_power_irq(int irq, void *devid)
|
||||
{
|
||||
struct axp20x_ac_power *power = devid;
|
||||
|
||||
+ regmap_update_bits(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, 0x03, 0x00);
|
||||
+ regmap_update_bits(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, 0x03, 0x03);
|
||||
+
|
||||
power_supply_changed(power->supply);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
|
||||
index f6c849bd1..f203ebc6e 100644
|
||||
--- a/drivers/power/supply/axp20x_battery.c
|
||||
+++ b/drivers/power/supply/axp20x_battery.c
|
||||
@@ -378,6 +378,42 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
|
||||
val->intval *= 1000;
|
||||
break;
|
||||
|
||||
+ case POWER_SUPPLY_PROP_ENERGY_FULL:
|
||||
+ case POWER_SUPPLY_PROP_ENERGY_NOW:
|
||||
+ /* When no battery is present, return 0 */
|
||||
+ ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE,
|
||||
+ ®);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ if (!(reg & AXP20X_PWR_OP_BATT_PRESENT)) {
|
||||
+ val->intval = 0;
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ if(psp == POWER_SUPPLY_PROP_ENERGY_FULL) {
|
||||
+ val->intval = 8000000;
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ ret = regmap_read(axp20x_batt->regmap, AXP20X_FG_RES, ®);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ if (axp20x_batt->data->has_fg_valid && !(reg & AXP22X_FG_VALID))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ val1 = reg & AXP209_FG_PERCENT;
|
||||
+ if (val1 > 90)
|
||||
+ val1= 80;
|
||||
+ else if (val1 < 10)
|
||||
+ val1 = 0;
|
||||
+ else
|
||||
+ val1 -= 10;
|
||||
+
|
||||
+ val->intval = val1 * 100000;
|
||||
+ break;
|
||||
+
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
@@ -544,6 +580,8 @@ static enum power_supply_property axp20x_battery_props[] = {
|
||||
POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
|
||||
POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
|
||||
POWER_SUPPLY_PROP_CAPACITY,
|
||||
+ POWER_SUPPLY_PROP_ENERGY_FULL,
|
||||
+ POWER_SUPPLY_PROP_ENERGY_NOW,
|
||||
};
|
||||
|
||||
static int axp20x_battery_prop_writeable(struct power_supply *psy,
|
||||
@@ -857,6 +895,12 @@ static int axp20x_power_probe(struct platform_device *pdev)
|
||||
goto warn_bat;
|
||||
}
|
||||
|
||||
+ regmap_update_bits(axp20x_batt->regmap, AXP20X_VBUS_IPSOUT_MGMT, 0x03, 0x03);
|
||||
+ regmap_update_bits(axp20x_batt->regmap, AXP20X_OFF_CTRL, 0x08, 0x08);
|
||||
+ regmap_update_bits(axp20x_batt->regmap, AXP20X_CHRG_CTRL2, 0x30, 0x20);
|
||||
+ regmap_update_bits(axp20x_batt->regmap, AXP20X_PEK_KEY, 0x0f, 0x0b);
|
||||
+ regmap_update_bits(axp20x_batt->regmap, AXP20X_GPIO0_CTRL, 0x07, 0x00);
|
||||
+
|
||||
return 0;
|
||||
|
||||
warn_bat:
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,76 @@
|
||||
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
|
||||
index 5e751b80e..92d4cd3dc 100644
|
||||
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
|
||||
@@ -338,12 +338,12 @@ static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
|
||||
* The whole dithering process and these parameters are not
|
||||
* explained in the vendor documents or BSP kernel code.
|
||||
*/
|
||||
- regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
|
||||
- regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
|
||||
- regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
|
||||
- regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
|
||||
- regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
|
||||
- regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
|
||||
+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 1);
|
||||
+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 3);
|
||||
+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 5);
|
||||
+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 7);
|
||||
+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 11);
|
||||
+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 13);
|
||||
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
|
||||
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
|
||||
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
|
||||
@@ -1602,6 +1602,12 @@ static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
|
||||
.set_mux = sun8i_r40_tcon_tv_set_mux,
|
||||
};
|
||||
|
||||
+static const struct sun4i_tcon_quirks sun50i_h6_lcd_quirks = {
|
||||
+ .has_channel_0 = true,
|
||||
+ .dclk_min_div = 1,
|
||||
+ .set_mux = sun8i_r40_tcon_tv_set_mux,
|
||||
+};
|
||||
+
|
||||
static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
|
||||
.has_channel_0 = true,
|
||||
.dclk_min_div = 1,
|
||||
@@ -1632,6 +1638,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
|
||||
{ .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
|
||||
{ .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
|
||||
{ .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
|
||||
+ { .compatible = "allwinner,sun50i-h6-tcon-lcd", .data = &sun50i_h6_lcd_quirks },
|
||||
{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
|
||||
{ .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
|
||||
{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
|
||||
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
|
||||
index 4fe915262..cd667fef8 100644
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
|
||||
@@ -683,6 +683,16 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
|
||||
.vi_num = 1,
|
||||
};
|
||||
|
||||
+static const struct sun8i_mixer_cfg sun50i_h6_mixer1_cfg = {
|
||||
+ .ccsc = 0,
|
||||
+ .is_de3 = true,
|
||||
+ .mod_rate = 600000000,
|
||||
+ .scaler_mask = 0xf,
|
||||
+ .scanline_yuv = 4096,
|
||||
+ .ui_num = 1,
|
||||
+ .vi_num = 1,
|
||||
+};
|
||||
+
|
||||
static const struct of_device_id sun8i_mixer_of_table[] = {
|
||||
{
|
||||
.compatible = "allwinner,sun8i-a83t-de2-mixer-0",
|
||||
@@ -724,6 +734,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
|
||||
.compatible = "allwinner,sun50i-h6-de3-mixer-0",
|
||||
.data = &sun50i_h6_mixer0_cfg,
|
||||
},
|
||||
+ {
|
||||
+ .compatible = "allwinner,sun50i-h6-de3-mixer-1",
|
||||
+ .data = &sun50i_h6_mixer1_cfg,
|
||||
+ },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
|
||||
@ -0,0 +1,849 @@
|
||||
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
|
||||
index 6153972e0..c91f4b7ed 100644
|
||||
--- a/drivers/gpu/drm/panel/Kconfig
|
||||
+++ b/drivers/gpu/drm/panel/Kconfig
|
||||
@@ -500,4 +500,17 @@ config DRM_PANEL_XINPENG_XPP055C272
|
||||
Say Y here if you want to enable support for the Xinpeng
|
||||
XPP055C272 controller for 720x1280 LCD panels with MIPI/RGB/SPI
|
||||
system interfaces.
|
||||
+
|
||||
+config DRM_PANEL_CWD686
|
||||
+ tristate "CWD686 panel"
|
||||
+ depends on OF
|
||||
+ depends on DRM_MIPI_DSI
|
||||
+ depends on BACKLIGHT_CLASS_DEVICE
|
||||
+ help
|
||||
+ Say Y here if you want to enable support for CWD686 panel.
|
||||
+ The panel has a 480x1280 resolution and uses 24 bit RGB per pixel.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the module
|
||||
+ will be called panel-cwd686.
|
||||
+
|
||||
endmenu
|
||||
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
|
||||
index 2ba560bca..865cca7f6 100644
|
||||
--- a/drivers/gpu/drm/panel/Makefile
|
||||
+++ b/drivers/gpu/drm/panel/Makefile
|
||||
@@ -53,3 +53,4 @@ obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o
|
||||
obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
|
||||
obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o
|
||||
obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
|
||||
+obj-$(CONFIG_DRM_PANEL_CWD686) += panel-cwd686.o
|
||||
diff --git a/drivers/gpu/drm/panel/panel-cwd686.c b/drivers/gpu/drm/panel/panel-cwd686.c
|
||||
new file mode 100644
|
||||
index 000000000..f3005490f
|
||||
--- /dev/null
|
||||
+++ b/drivers/gpu/drm/panel/panel-cwd686.c
|
||||
@@ -0,0 +1,768 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+
|
||||
+#include <drm/drm_modes.h>
|
||||
+#include <drm/drm_mipi_dsi.h>
|
||||
+#include <drm/drm_panel.h>
|
||||
+#include <linux/backlight.h>
|
||||
+#include <linux/gpio/consumer.h>
|
||||
+#include <linux/regulator/consumer.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/module.h>
|
||||
+
|
||||
+struct cwd686 {
|
||||
+ struct device *dev;
|
||||
+ struct drm_panel panel;
|
||||
+ struct regulator *supply;
|
||||
+ struct gpio_desc *enable_gpio;
|
||||
+ struct gpio_desc *reset_gpio;
|
||||
+ struct backlight_device *backlight;
|
||||
+ bool prepared;
|
||||
+ bool enabled;
|
||||
+};
|
||||
+
|
||||
+static const struct drm_display_mode default_mode = {
|
||||
+ .clock = 54465,
|
||||
+ .hdisplay = 480,
|
||||
+ .hsync_start = 480 + 150,
|
||||
+ .hsync_end = 480 + 150 + 24,
|
||||
+ .htotal = 480 + 150 + 24 + 40,
|
||||
+ .vdisplay = 1280,
|
||||
+ .vsync_start = 1280 + 12,
|
||||
+ .vsync_end = 1280 + 12+ 6,
|
||||
+ .vtotal = 1280 + 12 + 6 + 10,
|
||||
+};
|
||||
+
|
||||
+static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
|
||||
+{
|
||||
+ return container_of(panel, struct cwd686, panel);
|
||||
+}
|
||||
+
|
||||
+#define dcs_write_seq(seq...) \
|
||||
+({ \
|
||||
+ static const u8 d[] = { seq }; \
|
||||
+ mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
|
||||
+})
|
||||
+
|
||||
+static void cwd686_init_sequence(struct cwd686 *ctx)
|
||||
+{
|
||||
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
+
|
||||
+ dcs_write_seq(0xF0,0x5A,0x5A);
|
||||
+ dcs_write_seq(0xF1,0xA5,0xA5);
|
||||
+ dcs_write_seq(0xB6,0x0D,0x0D);
|
||||
+ dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
|
||||
+ dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
|
||||
+ dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
|
||||
+ dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
|
||||
+ dcs_write_seq(0xB2,0x73);
|
||||
+ dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
|
||||
+ dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
|
||||
+ dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
|
||||
+ dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
|
||||
+ dcs_write_seq(0xBA,0x12,0x63);
|
||||
+ dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
|
||||
+ dcs_write_seq(0xC2,0x11,0x41);
|
||||
+ dcs_write_seq(0xC3,0x22,0x31,0x04);
|
||||
+ dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
|
||||
+ dcs_write_seq(0xC5,0x00);
|
||||
+ dcs_write_seq(0xD0,0x37,0xFF,0xFF);
|
||||
+ dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
|
||||
+ dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
|
||||
+ dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
|
||||
+ dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
|
||||
+ dcs_write_seq(0xF4,0x08,0x77);
|
||||
+ dcs_write_seq(0x36,0x14);
|
||||
+ dcs_write_seq(0x35,0x00);
|
||||
+ dcs_write_seq(0xF1,0x5A,0x5A);
|
||||
+ dcs_write_seq(0xF0,0xA5,0xA5);
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static int cwd686_disable(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct cwd686 *ctx = panel_to_cwd686(panel);
|
||||
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!ctx->enabled)
|
||||
+ return 0;
|
||||
+
|
||||
+ backlight_disable(ctx->backlight);
|
||||
+
|
||||
+ ctx->enabled = false;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cwd686_unprepare(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct cwd686 *ctx = panel_to_cwd686(panel);
|
||||
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
+ int ret;
|
||||
+
|
||||
+#if 0
|
||||
+ if (!ctx->prepared)
|
||||
+ return 0;
|
||||
+
|
||||
+ ret = mipi_dsi_dcs_set_display_off(dsi);
|
||||
+ if (ret) {
|
||||
+ dev_err(ctx->dev, "failed to turn display off (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
|
||||
+ if (ret) {
|
||||
+ dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
|
||||
+
|
||||
+ ctx->prepared = false;
|
||||
+#endif
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cwd686_prepare(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct cwd686 *ctx = panel_to_cwd686(panel);
|
||||
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
+ int ret;
|
||||
+
|
||||
+ if (ctx->prepared)
|
||||
+ return 0;
|
||||
+
|
||||
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
|
||||
+ msleep(10);
|
||||
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
|
||||
+ msleep(120);
|
||||
+
|
||||
+ /* Enabe tearing mode: send TE (tearing effect) at VBLANK */
|
||||
+ ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
|
||||
+ if (ret) {
|
||||
+ dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ /* Exit sleep mode and power on */
|
||||
+
|
||||
+ cwd686_init_sequence(ctx);
|
||||
+
|
||||
+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
|
||||
+ if (ret) {
|
||||
+ dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ msleep(120);
|
||||
+
|
||||
+ ret = mipi_dsi_dcs_set_display_on(dsi);
|
||||
+ if (ret) {
|
||||
+ dev_err(ctx->dev, "failed to turn display on (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ msleep(20);
|
||||
+
|
||||
+ ctx->prepared = true;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cwd686_enable(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct cwd686 *ctx = panel_to_cwd686(panel);
|
||||
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
+ int ret;
|
||||
+
|
||||
+ if (ctx->enabled)
|
||||
+ return 0;
|
||||
+
|
||||
+ backlight_enable(ctx->backlight);
|
||||
+
|
||||
+ ctx->enabled = true;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cwd686_get_modes(struct drm_panel *panel, struct drm_connector *connector)
|
||||
+{
|
||||
+ struct drm_display_mode *mode;
|
||||
+
|
||||
+ mode = drm_mode_duplicate(connector->dev, &default_mode);
|
||||
+ if (!mode) {
|
||||
+ dev_err(panel->dev, "bad mode or failed to add mode\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ drm_mode_set_name(mode);
|
||||
+ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
|
||||
+
|
||||
+ connector->display_info.width_mm = mode->width_mm;
|
||||
+ connector->display_info.height_mm = mode->height_mm;
|
||||
+
|
||||
+ drm_mode_probed_add(connector, mode);
|
||||
+
|
||||
+ return 1; /* Number of modes */
|
||||
+}
|
||||
+
|
||||
+static const struct drm_panel_funcs cwd686_drm_funcs = {
|
||||
+ .disable = cwd686_disable,
|
||||
+ .unprepare = cwd686_unprepare,
|
||||
+ .prepare = cwd686_prepare,
|
||||
+ .enable = cwd686_enable,
|
||||
+ .get_modes = cwd686_get_modes,
|
||||
+};
|
||||
+
|
||||
+static int cwd686_probe(struct mipi_dsi_device *dsi)
|
||||
+{
|
||||
+ struct device *dev = &dsi->dev;
|
||||
+ struct cwd686 *ctx;
|
||||
+ int ret;
|
||||
+
|
||||
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
||||
+ if (!ctx)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ mipi_dsi_set_drvdata(dsi, ctx);
|
||||
+ ctx->dev = dev;
|
||||
+
|
||||
+ dsi->lanes = 4;
|
||||
+ dsi->format = MIPI_DSI_FMT_RGB888;
|
||||
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO |MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
|
||||
+
|
||||
+ ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
|
||||
+ if (IS_ERR(ctx->reset_gpio)) {
|
||||
+ ret = PTR_ERR(ctx->reset_gpio);
|
||||
+ if (ret != -EPROBE_DEFER)
|
||||
+ dev_err(dev, "failed to request GPIO (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ctx->backlight = devm_of_find_backlight(dev);
|
||||
+ if (IS_ERR(ctx->backlight))
|
||||
+ return PTR_ERR(ctx->backlight);
|
||||
+
|
||||
+ drm_panel_init(&ctx->panel, dev, &cwd686_drm_funcs, DRM_MODE_CONNECTOR_DSI);
|
||||
+
|
||||
+ drm_panel_add(&ctx->panel);
|
||||
+
|
||||
+ ret = mipi_dsi_attach(dsi);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
|
||||
+ drm_panel_remove(&ctx->panel);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cwd686_remove(struct mipi_dsi_device *dsi)
|
||||
+{
|
||||
+ struct cwd686 *ctx = mipi_dsi_get_drvdata(dsi);
|
||||
+
|
||||
+ mipi_dsi_detach(dsi);
|
||||
+ drm_panel_remove(&ctx->panel);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+#if 1
|
||||
+#include <linux/i2c.h>
|
||||
+#include <linux/regmap.h>
|
||||
+
|
||||
+struct tc358768_priv {
|
||||
+ struct device *dev;
|
||||
+ struct regmap *regmap;
|
||||
+ struct gpio_desc *reset_gpio;
|
||||
+ struct gpio_desc *power_gpio;
|
||||
+};
|
||||
+
|
||||
+#define panel_mini_vdd3v3en(val) gpiod_set_value_cansleep(priv->power_gpio, val)
|
||||
+#define panel_reset(val) gpiod_set_value_cansleep(priv->reset_gpio, val)
|
||||
+#define panel_lcd_reset(val) {}
|
||||
+#define panel_lcd_power(val) {}
|
||||
+
|
||||
+static const struct regmap_config tc358768_regmap_config = {
|
||||
+ .reg_bits = 16,
|
||||
+ .val_bits = 16,
|
||||
+ .max_register = 0x062C,
|
||||
+ .cache_type = REGCACHE_NONE,
|
||||
+// .writeable_reg = tc358768_writeable_reg,
|
||||
+// .readable_reg = tc358768_readable_reg,
|
||||
+ .reg_format_endian = REGMAP_ENDIAN_BIG,
|
||||
+ .val_format_endian = REGMAP_ENDIAN_BIG,
|
||||
+};
|
||||
+
|
||||
+static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
|
||||
+{
|
||||
+ /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
|
||||
+ int tmpval = val;
|
||||
+ size_t count = 1;
|
||||
+
|
||||
+ regmap_bulk_write(priv->regmap, reg, &tmpval, count);
|
||||
+}
|
||||
+
|
||||
+static void LCD_power_on(struct tc358768_priv *priv)
|
||||
+{
|
||||
+
|
||||
+ panel_reset(0);
|
||||
+ panel_lcd_power(1);
|
||||
+ msleep(5);
|
||||
+ panel_lcd_reset(0);
|
||||
+ msleep(5);
|
||||
+ panel_lcd_reset(1);
|
||||
+ msleep(5);
|
||||
+ panel_lcd_reset(0);
|
||||
+ msleep(5);
|
||||
+ panel_lcd_reset(1);
|
||||
+// sunxi_lcd_power_enable(sel, 0);//config 775 VDD_MIPI_12 power
|
||||
+ msleep(50);
|
||||
+ panel_mini_vdd3v3en(1);
|
||||
+ msleep(50);
|
||||
+ panel_reset(1);
|
||||
+ msleep(50);
|
||||
+ panel_reset(0);
|
||||
+ msleep(50);
|
||||
+ panel_reset(1);
|
||||
+ msleep(50);
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static void LCD_power_off(struct tc358768_priv *priv)
|
||||
+{
|
||||
+ msleep(5);
|
||||
+ panel_reset(0);
|
||||
+ msleep(5);
|
||||
+ panel_lcd_reset(0);
|
||||
+ msleep(20);
|
||||
+// sunxi_lcd_power_disable(sel, 0);//config lcd_power pin to close lcd power
|
||||
+ panel_mini_vdd3v3en(0);
|
||||
+ panel_lcd_power(0);
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static void tc358778_panel_init_mipi(struct tc358768_priv *priv)
|
||||
+{
|
||||
+ __u16 value=0;
|
||||
+ tc358768_write(priv, 0x0002,0x0001);//SYSctl, S/W Reset
|
||||
+ msleep(10);
|
||||
+ tc358768_write(priv, 0x0002,0x0000);//SYSctl, S/W Reset release
|
||||
+ tc358768_write(priv, 0x0016,0x106D);//PLL Control Register 0 (PLL_PRD,PLL_FBD)
|
||||
+ tc358768_write(priv, 0x0018,0x0603);//PLL_FRS,PLL_LBWS, PLL oscillation enable
|
||||
+ msleep(100);
|
||||
+ tc358768_write(priv, 0x0018,0x0613);//PLL_FRS,PLL_LBWS, PLL clock out enable
|
||||
+ tc358768_write(priv, 0x0006,0x0014);//FIFO Control Register
|
||||
+ tc358768_write(priv, 0x0140,0x0000);//D-PHY Clock lane enable
|
||||
+ tc358768_write(priv, 0x0142,0x0000);//
|
||||
+ tc358768_write(priv, 0x0144,0x0000);//D-PHY Data lane0 enable
|
||||
+ tc358768_write(priv, 0x0146,0x0000);//
|
||||
+ tc358768_write(priv, 0x0148,0x0000);//D-PHY Data lane1 enable
|
||||
+ tc358768_write(priv, 0x014A,0x0000);//
|
||||
+ tc358768_write(priv, 0x014C,0x0000);//D-PHY Data lane2 enable
|
||||
+ tc358768_write(priv, 0x014E,0x0000);//
|
||||
+ tc358768_write(priv, 0x0150,0x0000);//D-PHY Data lane3 enable
|
||||
+ tc358768_write(priv, 0x0152,0x0000);//
|
||||
+ tc358768_write(priv, 0x0100,0x0002);//D-PHY Clock lane control
|
||||
+ tc358768_write(priv, 0x0102,0x0000);//
|
||||
+ tc358768_write(priv, 0x0104,0x0002);//D-PHY Data lane0 control
|
||||
+ tc358768_write(priv, 0x0106,0x0000);//
|
||||
+ tc358768_write(priv, 0x0108,0x0002);//D-PHY Data lane1 control
|
||||
+ tc358768_write(priv, 0x010A,0x0000);//
|
||||
+ tc358768_write(priv, 0x010C,0x0002);//D-PHY Data lane2 control
|
||||
+ tc358768_write(priv, 0x010E,0x0000);//
|
||||
+ tc358768_write(priv, 0x0110,0x0002);//D-PHY Data lane3 control
|
||||
+ tc358768_write(priv, 0x0112,0x0000);//
|
||||
+ tc358768_write(priv, 0x0210,0x1770);//LINEINITCNT
|
||||
+ tc358768_write(priv, 0x0212,0x0000);//
|
||||
+ tc358768_write(priv, 0x0214,0x0002);//LPTXTIMECNT
|
||||
+ tc358768_write(priv, 0x0216,0x0000);//
|
||||
+ tc358768_write(priv, 0x0218,0x2301);//TCLK_HEADERCNT
|
||||
+ tc358768_write(priv, 0x021A,0x0000);//
|
||||
+ tc358768_write(priv, 0x0220,0x0803);//THS_HEADERCNT
|
||||
+ tc358768_write(priv, 0x0222,0x0000);//
|
||||
+ tc358768_write(priv, 0x0224,0x4E20);//TWAKEUPCNT
|
||||
+ tc358768_write(priv, 0x0226,0x0000);//
|
||||
+ tc358768_write(priv, 0x022C,0x0000);//THS_TRAILCNT
|
||||
+ tc358768_write(priv, 0x022E,0x0000);//
|
||||
+ tc358768_write(priv, 0x0230,0x0005);//HSTXVREGCNT
|
||||
+ tc358768_write(priv, 0x0232,0x0000);//
|
||||
+ tc358768_write(priv, 0x0234,0x001F);//HSTXVREGEN enable
|
||||
+ tc358768_write(priv, 0x0236,0x0000);//
|
||||
+ tc358768_write(priv, 0x0238,0x0001);//DSI clock Enable/Disable during LP
|
||||
+ tc358768_write(priv, 0x023A,0x0000);//
|
||||
+ tc358768_write(priv, 0x023C,0x0002);//BTACNTRL1
|
||||
+ tc358768_write(priv, 0x023E,0x0002);//
|
||||
+ tc358768_write(priv, 0x0204,0x0001);//STARTCNTRL
|
||||
+ tc358768_write(priv, 0x0206,0x0000);//
|
||||
+ tc358768_write(priv, 0x0620,0x0001);//Sync Pulse/Sync Event mode setting
|
||||
+ tc358768_write(priv, 0x0622,0x001E);//V Control Register1
|
||||
+ tc358768_write(priv, 0x0624,0x0014);//V Control Register2
|
||||
+ tc358768_write(priv, 0x0626,0x0500);//V Control Register3
|
||||
+ tc358768_write(priv, 0x0628,0x00CF);//H Control Register1
|
||||
+ tc358768_write(priv, 0x062A,0x00BA);//H Control Register2
|
||||
+ tc358768_write(priv, 0x062C,0x05A0);//H Control Register3
|
||||
+ tc358768_write(priv, 0x0518,0x0001);//DSI Start
|
||||
+ tc358768_write(priv, 0x051A,0x0000);//
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0003);
|
||||
+ tc358768_write(priv, 0x0610,0x5AF0);
|
||||
+ tc358768_write(priv, 0x0612,0x005A);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0003);
|
||||
+ tc358768_write(priv, 0x0610,0xA5F1);
|
||||
+ tc358768_write(priv, 0x0612,0x00A5);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0003);
|
||||
+ tc358768_write(priv, 0x0610,0x0DB6);
|
||||
+ tc358768_write(priv, 0x0612,0x000D);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0008,0x0001);
|
||||
+ tc358768_write(priv, 0x0050,0x0029);
|
||||
+ tc358768_write(priv, 0x0022,0x0015);
|
||||
+ tc358768_write(priv, 0x00E0,0x8000);
|
||||
+ tc358768_write(priv, 0x00E8,0x0AB4);
|
||||
+ tc358768_write(priv, 0x00E8,0x1208);
|
||||
+ tc358768_write(priv, 0x00E8,0x0E10);
|
||||
+ tc358768_write(priv, 0x00E8,0x000C);
|
||||
+ tc358768_write(priv, 0x00E8,0x0000);
|
||||
+ tc358768_write(priv, 0x00E8,0x0003);
|
||||
+ tc358768_write(priv, 0x00E8,0x0303);
|
||||
+ tc358768_write(priv, 0x00E8,0x0303);
|
||||
+ tc358768_write(priv, 0x00E8,0x0303);
|
||||
+ tc358768_write(priv, 0x00E8,0x0403);
|
||||
+ tc358768_write(priv, 0x00E8,0x0006);
|
||||
+ tc358768_write(priv, 0x00E0,0xE000);
|
||||
+ msleep(100);
|
||||
+ tc358768_write(priv, 0x00E0,0x2000);
|
||||
+ tc358768_write(priv, 0x00E0,0x0000);
|
||||
+ msleep(10);
|
||||
+ tc358768_write(priv, 0x0008,0x0001);
|
||||
+ tc358768_write(priv, 0x0050,0x0029);
|
||||
+ tc358768_write(priv, 0x0022,0x0015);
|
||||
+ tc358768_write(priv, 0x00E0,0x8000);
|
||||
+ tc358768_write(priv, 0x00E8,0x0BB3);
|
||||
+ tc358768_write(priv, 0x00E8,0x1309);
|
||||
+ tc358768_write(priv, 0x00E8,0x0F11);
|
||||
+ tc358768_write(priv, 0x00E8,0x000D);
|
||||
+ tc358768_write(priv, 0x00E8,0x0000);
|
||||
+ tc358768_write(priv, 0x00E8,0x0003);
|
||||
+ tc358768_write(priv, 0x00E8,0x0303);
|
||||
+ tc358768_write(priv, 0x00E8,0x0303);
|
||||
+ tc358768_write(priv, 0x00E8,0x0303);
|
||||
+ tc358768_write(priv, 0x00E8,0x0503);
|
||||
+ tc358768_write(priv, 0x00E8,0x0007);
|
||||
+ tc358768_write(priv, 0x00E0,0xE000);
|
||||
+ msleep(100);
|
||||
+ tc358768_write(priv, 0x00E0,0x2000);
|
||||
+ tc358768_write(priv, 0x00E0,0x0000);
|
||||
+ msleep(10);
|
||||
+ tc358768_write(priv, 0x0008,0x0001);
|
||||
+ tc358768_write(priv, 0x0050,0x0029);
|
||||
+ tc358768_write(priv, 0x0022,0x000D);
|
||||
+ tc358768_write(priv, 0x00E0,0x8000);
|
||||
+ tc358768_write(priv, 0x00E8,0x54B0);
|
||||
+ tc358768_write(priv, 0x00E8,0x2332);
|
||||
+ tc358768_write(priv, 0x00E8,0x4445);
|
||||
+ tc358768_write(priv, 0x00E8,0x4444);
|
||||
+ tc358768_write(priv, 0x00E8,0x9044);
|
||||
+ tc358768_write(priv, 0x00E8,0x9001);
|
||||
+ tc358768_write(priv, 0x00E8,0x0001);
|
||||
+ tc358768_write(priv, 0x00E0,0xE000);
|
||||
+ msleep(100);
|
||||
+ tc358768_write(priv, 0x00E0,0x2000);
|
||||
+ tc358768_write(priv, 0x00E0,0x0000);
|
||||
+ msleep(10);
|
||||
+ tc358768_write(priv, 0x0008,0x0001);
|
||||
+ tc358768_write(priv, 0x0050,0x0029);
|
||||
+ tc358768_write(priv, 0x0022,0x000D);
|
||||
+ tc358768_write(priv, 0x00E0,0x8000);
|
||||
+ tc358768_write(priv, 0x00E8,0x32B1);
|
||||
+ tc358768_write(priv, 0x00E8,0x0284);
|
||||
+ tc358768_write(priv, 0x00E8,0x0383);
|
||||
+ tc358768_write(priv, 0x00E8,0x6B01);
|
||||
+ tc358768_write(priv, 0x00E8,0x0001);
|
||||
+ tc358768_write(priv, 0x00E0,0xE000);
|
||||
+ msleep(100);
|
||||
+ tc358768_write(priv, 0x00E0,0x2000);
|
||||
+ tc358768_write(priv, 0x00E0,0x0000);
|
||||
+ msleep(10);
|
||||
+ tc358768_write(priv, 0x0602,0x1023);
|
||||
+ tc358768_write(priv, 0x0604,0x0000);
|
||||
+ tc358768_write(priv, 0x0610,0x73B2);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0008,0x0001);
|
||||
+ tc358768_write(priv, 0x0050,0x0029);
|
||||
+ tc358768_write(priv, 0x0022,0x000B);
|
||||
+ tc358768_write(priv, 0x00E0,0x8000);
|
||||
+ tc358768_write(priv, 0x00E8,0x4EBD);
|
||||
+ tc358768_write(priv, 0x00E8,0x500E);
|
||||
+ tc358768_write(priv, 0x00E8,0x2650);
|
||||
+ tc358768_write(priv, 0x00E8,0x001D);
|
||||
+ tc358768_write(priv, 0x00E8,0x4214);
|
||||
+ tc358768_write(priv, 0x00E8,0x0003);
|
||||
+ tc358768_write(priv, 0x00E0,0xE000);
|
||||
+ msleep(100);
|
||||
+ tc358768_write(priv, 0x00E0,0x2000);
|
||||
+ tc358768_write(priv, 0x00E0,0x0000);
|
||||
+ msleep(10);
|
||||
+ tc358768_write(priv, 0x0008,0x0001);
|
||||
+ tc358768_write(priv, 0x0050,0x0029);
|
||||
+ tc358768_write(priv, 0x0022,0x0012);
|
||||
+ tc358768_write(priv, 0x00E0,0x8000);
|
||||
+ tc358768_write(priv, 0x00E8,0x01B7);
|
||||
+ tc358768_write(priv, 0x00E8,0x0901);
|
||||
+ tc358768_write(priv, 0x00E8,0x0D11);
|
||||
+ tc358768_write(priv, 0x00E8,0x1955);
|
||||
+ tc358768_write(priv, 0x00E8,0x2119);
|
||||
+ tc358768_write(priv, 0x00E8,0x001D);
|
||||
+ tc358768_write(priv, 0x00E8,0x0000);
|
||||
+ tc358768_write(priv, 0x00E8,0x0200);
|
||||
+ tc358768_write(priv, 0x00E8,0x3CFF);
|
||||
+ tc358768_write(priv, 0x00E0,0xE000);
|
||||
+ msleep(100);
|
||||
+ tc358768_write(priv, 0x00E0,0x2000);
|
||||
+ tc358768_write(priv, 0x00E0,0x0000);
|
||||
+ msleep(10);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0006);
|
||||
+ tc358768_write(priv, 0x0610,0x23B8);
|
||||
+ tc358768_write(priv, 0x0612,0x3001);
|
||||
+ tc358768_write(priv, 0x0614,0x6334);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0005);
|
||||
+ tc358768_write(priv, 0x0610,0x23B9);
|
||||
+ tc358768_write(priv, 0x0612,0x0022);
|
||||
+ tc358768_write(priv, 0x0614,0x0044);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0003);
|
||||
+ tc358768_write(priv, 0x0610,0x12BA);
|
||||
+ tc358768_write(priv, 0x0612,0x0063);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0007);
|
||||
+ tc358768_write(priv, 0x0610,0x0CC1);
|
||||
+ tc358768_write(priv, 0x0612,0x0416);
|
||||
+ tc358768_write(priv, 0x0614,0x100C);
|
||||
+ tc358768_write(priv, 0x0616,0x0004);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0003);
|
||||
+ tc358768_write(priv, 0x0610,0x11C2);
|
||||
+ tc358768_write(priv, 0x0612,0x0041);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0004);
|
||||
+ tc358768_write(priv, 0x0610,0x22C3);
|
||||
+ tc358768_write(priv, 0x0612,0x0431);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0006);
|
||||
+ tc358768_write(priv, 0x0610,0x05C7);
|
||||
+ tc358768_write(priv, 0x0612,0x6B23);
|
||||
+ tc358768_write(priv, 0x0614,0x0049);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x1023);
|
||||
+ tc358768_write(priv, 0x0604,0x0000);
|
||||
+ tc358768_write(priv, 0x0610,0x00C5);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0004);
|
||||
+ tc358768_write(priv, 0x0610,0x37D0);
|
||||
+ tc358768_write(priv, 0x0612,0xFFFF);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0005);
|
||||
+ tc358768_write(priv, 0x0610,0x63D2);
|
||||
+ tc358768_write(priv, 0x0612,0x080B);
|
||||
+ tc358768_write(priv, 0x0614,0x0088);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0008,0x0001);
|
||||
+ tc358768_write(priv, 0x0050,0x0029);
|
||||
+ tc358768_write(priv, 0x0022,0x000C);
|
||||
+ tc358768_write(priv, 0x00E0,0x8000);
|
||||
+ tc358768_write(priv, 0x00E8,0x01D3);
|
||||
+ tc358768_write(priv, 0x00E8,0x0000);
|
||||
+ tc358768_write(priv, 0x00E8,0x0101);
|
||||
+ tc358768_write(priv, 0x00E8,0x2537);
|
||||
+ tc358768_write(priv, 0x00E8,0x3138);
|
||||
+ tc358768_write(priv, 0x00E8,0x0706);
|
||||
+ tc358768_write(priv, 0x00E0,0xE000);
|
||||
+ msleep(100);
|
||||
+ tc358768_write(priv, 0x00E0,0x2000);
|
||||
+ tc358768_write(priv, 0x00E0,0x0000);
|
||||
+ msleep(10);
|
||||
+ tc358768_write(priv, 0x0008,0x0001);
|
||||
+ tc358768_write(priv, 0x0050,0x0029);
|
||||
+ tc358768_write(priv, 0x0022,0x0027);
|
||||
+ tc358768_write(priv, 0x00E0,0x8000);
|
||||
+ tc358768_write(priv, 0x00E8,0x7CC8);
|
||||
+ tc358768_write(priv, 0x00E8,0x5D6A);
|
||||
+ tc358768_write(priv, 0x00E8,0x5353);
|
||||
+ tc358768_write(priv, 0x00E8,0x4B45);
|
||||
+ tc358768_write(priv, 0x00E8,0x4D35);
|
||||
+ tc358768_write(priv, 0x00E8,0x494A);
|
||||
+ tc358768_write(priv, 0x00E8,0x5366);
|
||||
+ tc358768_write(priv, 0x00E8,0x4A57);
|
||||
+ tc358768_write(priv, 0x00E8,0x3B48);
|
||||
+ tc358768_write(priv, 0x00E8,0x062A);
|
||||
+ tc358768_write(priv, 0x00E8,0x6A7C);
|
||||
+ tc358768_write(priv, 0x00E8,0x535D);
|
||||
+ tc358768_write(priv, 0x00E8,0x4553);
|
||||
+ tc358768_write(priv, 0x00E8,0x354B);
|
||||
+ tc358768_write(priv, 0x00E8,0x4A4D);
|
||||
+ tc358768_write(priv, 0x00E8,0x6649);
|
||||
+ tc358768_write(priv, 0x00E8,0x5753);
|
||||
+ tc358768_write(priv, 0x00E8,0x484A);
|
||||
+ tc358768_write(priv, 0x00E8,0x2A3B);
|
||||
+ tc358768_write(priv, 0x00E8,0x0006);
|
||||
+ tc358768_write(priv, 0x00E8,0x0000);
|
||||
+ tc358768_write(priv, 0x00E0,0xE000);
|
||||
+ msleep(100);
|
||||
+ tc358768_write(priv, 0x00E0,0x2000);
|
||||
+ tc358768_write(priv, 0x00E0,0x0000);
|
||||
+ msleep(10);
|
||||
+ tc358768_write(priv, 0x0008,0x0001);
|
||||
+ tc358768_write(priv, 0x0050,0x0029);
|
||||
+ tc358768_write(priv, 0x0022,0x0009);
|
||||
+ tc358768_write(priv, 0x00E0,0x8000);
|
||||
+ tc358768_write(priv, 0x00E8,0x00C6);
|
||||
+ tc358768_write(priv, 0x00E8,0xFF00);
|
||||
+ tc358768_write(priv, 0x00E8,0x0000);
|
||||
+ tc358768_write(priv, 0x00E8,0x00FF);
|
||||
+ tc358768_write(priv, 0x00E8,0x0000);
|
||||
+ tc358768_write(priv, 0x00E0,0xE000);
|
||||
+ msleep(100);
|
||||
+ tc358768_write(priv, 0x00E0,0x2000);
|
||||
+ tc358768_write(priv, 0x00E0,0x0000);
|
||||
+ msleep(10);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0003);
|
||||
+ tc358768_write(priv, 0x0610,0x08F4);
|
||||
+ tc358768_write(priv, 0x0612,0x0077);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x1023);
|
||||
+ tc358768_write(priv, 0x0604,0x0000);
|
||||
+ tc358768_write(priv, 0x0610,0x1436);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x1023);
|
||||
+ tc358768_write(priv, 0x0604,0x0000);
|
||||
+ tc358768_write(priv, 0x0610,0x0035);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x1023);
|
||||
+ tc358768_write(priv, 0x0604,0x0000);
|
||||
+ tc358768_write(priv, 0x0610,0x0011);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x1023);
|
||||
+ tc358768_write(priv, 0x0604,0x0000);
|
||||
+ tc358768_write(priv, 0x0610,0x0029);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0003);
|
||||
+ tc358768_write(priv, 0x0610,0x5AF1);
|
||||
+ tc358768_write(priv, 0x0612,0x005A);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0602,0x4029);
|
||||
+ tc358768_write(priv, 0x0604,0x0003);
|
||||
+ tc358768_write(priv, 0x0610,0xA5F0);
|
||||
+ tc358768_write(priv, 0x0612,0x00A5);
|
||||
+ tc358768_write(priv, 0x0600,0x0001);
|
||||
+ msleep(50);
|
||||
+ tc358768_write(priv, 0x0500,0x0086);//DSI lane setting, DSI mode=HS
|
||||
+ tc358768_write(priv, 0x0502,0xA300);//bit set
|
||||
+ tc358768_write(priv, 0x0500,0x8000);//Switch to DSI mode
|
||||
+ tc358768_write(priv, 0x0502,0xC300);//
|
||||
+ tc358768_write(priv, 0x0008,0x0037);//DSI-TX Format setting
|
||||
+ tc358768_write(priv, 0x0050,0x003E);//DSI-TX Pixel stream packet Data Type setting
|
||||
+ tc358768_write(priv, 0x0032,0x0000);//HSYNC Polarity
|
||||
+ tc358768_write(priv, 0x0004,0x0044);//Configuration Control Register
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static void LCD_panel_init(struct tc358768_priv *priv)
|
||||
+{
|
||||
+ LCD_power_on(priv);
|
||||
+ msleep(100);
|
||||
+ tc358778_panel_init_mipi(priv);
|
||||
+ msleep(10);
|
||||
+}
|
||||
+
|
||||
+static int cwd686_i2c_probe(struct i2c_client *client,
|
||||
+ const struct i2c_device_id *id)
|
||||
+{
|
||||
+ struct tc358768_priv *priv;
|
||||
+ struct device *dev = &client->dev;
|
||||
+ struct device_node *np = dev->of_node;
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ if (!np)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ dev_set_drvdata(dev, priv);
|
||||
+ priv->dev = dev;
|
||||
+ priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
|
||||
+
|
||||
+ if (IS_ERR(priv->reset_gpio))
|
||||
+ return PTR_ERR(priv->reset_gpio);
|
||||
+
|
||||
+ priv->power_gpio = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_HIGH);
|
||||
+
|
||||
+ if (IS_ERR(priv->power_gpio))
|
||||
+ return PTR_ERR(priv->power_gpio);
|
||||
+
|
||||
+ priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
|
||||
+ if (IS_ERR(priv->regmap)) {
|
||||
+ dev_err(dev, "Failed to init regmap\n");
|
||||
+ return PTR_ERR(priv->regmap);
|
||||
+ }
|
||||
+
|
||||
+ i2c_set_clientdata(client, priv);
|
||||
+
|
||||
+ LCD_panel_init(priv);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
+static const struct of_device_id cwd686_of_match[] = {
|
||||
+ { .compatible = "cw,cwd686" },
|
||||
+ { }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, cwd686_of_match);
|
||||
+
|
||||
+static struct i2c_driver cwd686_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "panel-cwd686",
|
||||
+ .of_match_table = cwd686_of_match,
|
||||
+ },
|
||||
+ .probe = cwd686_i2c_probe,
|
||||
+};
|
||||
+module_i2c_driver(cwd686_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("DRM Driver for cwd686 MIPI DSI panel");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
|
||||
index 585ebe779..b494cede5 100644
|
||||
--- a/drivers/gpu/drm/panel/panel-simple.c
|
||||
+++ b/drivers/gpu/drm/panel/panel-simple.c
|
||||
@@ -4003,6 +4003,29 @@ static const struct panel_desc arm_rtsm = {
|
||||
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
|
||||
};
|
||||
|
||||
+
|
||||
+static const struct drm_display_mode clockwork_cpi3_lcd_mode = {
|
||||
+ .clock = 50000,
|
||||
+ .hdisplay = 480,
|
||||
+ .hsync_start = 480 + 80,
|
||||
+ .hsync_end = 480 + 80 + 20,
|
||||
+ .htotal = 480 + 80 + 20 + 40,
|
||||
+ .vdisplay = 1280,
|
||||
+ .vsync_start = 1280 + 50,
|
||||
+ .vsync_end = 1280 + 50+ 10,
|
||||
+ .vtotal = 1280 + 50 + 10 + 20,
|
||||
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
|
||||
+};
|
||||
+
|
||||
+static const struct panel_desc clockwork_cpi3_lcd = {
|
||||
+ .modes = &clockwork_cpi3_lcd_mode,
|
||||
+ .num_modes = 1,
|
||||
+ .bpc = 6,
|
||||
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
|
||||
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
|
||||
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
|
||||
+};
|
||||
+
|
||||
static const struct of_device_id platform_of_match[] = {
|
||||
{
|
||||
.compatible = "ampire,am-1280800n3tzqw-t00h",
|
||||
@@ -4419,6 +4442,9 @@ static const struct of_device_id platform_of_match[] = {
|
||||
}, {
|
||||
.compatible = "winstar,wf35ltiacd",
|
||||
.data = &winstar_wf35ltiacd,
|
||||
+ }, {
|
||||
+ .compatible = "clockwork,cpi3-lcd",
|
||||
+ .data = &clockwork_cpi3_lcd,
|
||||
}, {
|
||||
/* Must be the last entry */
|
||||
.compatible = "panel-dpi",
|
||||
@ -0,0 +1,309 @@
|
||||
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
|
||||
index d83c87b90..2f1b6105e 100644
|
||||
--- a/drivers/video/backlight/Kconfig
|
||||
+++ b/drivers/video/backlight/Kconfig
|
||||
@@ -456,6 +456,12 @@ config BACKLIGHT_LED
|
||||
If you have a LCD backlight adjustable by LED class driver, say Y
|
||||
to enable this driver.
|
||||
|
||||
+config BACKLIGHT_OCP8178
|
||||
+ tristate "OCP8178 Backlight Driver"
|
||||
+ depends on GPIOLIB
|
||||
+ help
|
||||
+ If you have an OCP8178, say Y to enable the backlight driver.
|
||||
+
|
||||
endif # BACKLIGHT_CLASS_DEVICE
|
||||
|
||||
endmenu
|
||||
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
|
||||
index 685f3f1ca..f1160d626 100644
|
||||
--- a/drivers/video/backlight/Makefile
|
||||
+++ b/drivers/video/backlight/Makefile
|
||||
@@ -57,3 +57,4 @@ obj-$(CONFIG_BACKLIGHT_WM831X) += wm831x_bl.o
|
||||
obj-$(CONFIG_BACKLIGHT_ARCXCNN) += arcxcnn_bl.o
|
||||
obj-$(CONFIG_BACKLIGHT_RAVE_SP) += rave-sp-backlight.o
|
||||
obj-$(CONFIG_BACKLIGHT_LED) += led_bl.o
|
||||
+obj-$(CONFIG_BACKLIGHT_OCP8178) += ocp8178_bl.o
|
||||
diff --git a/drivers/video/backlight/ocp8178_bl.c b/drivers/video/backlight/ocp8178_bl.c
|
||||
new file mode 100644
|
||||
index 000000000..db8db1771
|
||||
--- /dev/null
|
||||
+++ b/drivers/video/backlight/ocp8178_bl.c
|
||||
@@ -0,0 +1,277 @@
|
||||
+/*
|
||||
+ * ocp8178_bl.c - ocp8178 backlight driver
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/backlight.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/fb.h>
|
||||
+#include <linux/gpio.h> /* Only for legacy support */
|
||||
+#include <linux/gpio/consumer.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_gpio.h>
|
||||
+#include <linux/platform_data/gpio_backlight.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/timer.h>
|
||||
+#include <linux/poll.h>
|
||||
+#include <linux/proc_fs.h>
|
||||
+#include <linux/seq_file.h>
|
||||
+#include <linux/sched.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/irq.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/clk.h>
|
||||
+
|
||||
+struct ocp8178_backlight {
|
||||
+ struct device *dev;
|
||||
+ struct device *fbdev;
|
||||
+
|
||||
+ struct gpio_desc *gpiod;
|
||||
+ int def_value;
|
||||
+ int current_value;
|
||||
+};
|
||||
+
|
||||
+#define DETECT_DELAY 200
|
||||
+#define DETECT_TIME 500
|
||||
+#define DETECT_WINDOW_TIME 1000
|
||||
+#define START_TIME 10
|
||||
+#define END_TIME 10
|
||||
+#define SHUTDOWN_TIME 3000
|
||||
+#define LOW_BIT_HIGH_TIME 10
|
||||
+#define LOW_BIT_LOW_TIME 50
|
||||
+#define HIGH_BIT_HIGH_TIME 50
|
||||
+#define HIGH_BIT_LOW_TIME 10
|
||||
+#define MAX_BRIGHTNESS_VALUE 9
|
||||
+
|
||||
+static void entry_1wire_mode(struct ocp8178_backlight *gbl)
|
||||
+{
|
||||
+ unsigned long flags = 0;
|
||||
+ local_irq_save(flags);
|
||||
+ gpiod_set_value(gbl->gpiod, 0);
|
||||
+ mdelay(SHUTDOWN_TIME/1000);
|
||||
+ gpiod_set_value(gbl->gpiod, 1);
|
||||
+ udelay(DETECT_DELAY);
|
||||
+ gpiod_set_value(gbl->gpiod, 0);
|
||||
+ udelay(DETECT_TIME);
|
||||
+ gpiod_set_value(gbl->gpiod, 1);
|
||||
+ udelay(DETECT_WINDOW_TIME);
|
||||
+ local_irq_restore(flags);
|
||||
+}
|
||||
+
|
||||
+static inline void write_bit(struct ocp8178_backlight *gbl, int bit)
|
||||
+{
|
||||
+ if (bit) {
|
||||
+ gpiod_set_value(gbl->gpiod, 0);
|
||||
+ udelay(HIGH_BIT_LOW_TIME);
|
||||
+ gpiod_set_value(gbl->gpiod, 1);
|
||||
+ udelay(HIGH_BIT_HIGH_TIME);
|
||||
+ } else {
|
||||
+ gpiod_set_value(gbl->gpiod, 0);
|
||||
+ udelay(LOW_BIT_LOW_TIME);
|
||||
+ gpiod_set_value(gbl->gpiod, 1);
|
||||
+ udelay(LOW_BIT_HIGH_TIME);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void write_byte(struct ocp8178_backlight *gbl, int byte)
|
||||
+{
|
||||
+ unsigned long flags = 0;
|
||||
+ unsigned char data = 0x72;
|
||||
+ int i;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+
|
||||
+ gpiod_set_value(gbl->gpiod, 1);
|
||||
+ udelay(START_TIME);
|
||||
+ for(i = 0; i < 8; i++) {
|
||||
+ if(data & 0x80) {
|
||||
+ write_bit(gbl, 1);
|
||||
+ } else {
|
||||
+ write_bit(gbl, 0);
|
||||
+ }
|
||||
+ data <<= 1;
|
||||
+ }
|
||||
+ gpiod_set_value(gbl->gpiod, 0);
|
||||
+ udelay(END_TIME);
|
||||
+
|
||||
+ data = byte & 0x1f;
|
||||
+
|
||||
+ gpiod_set_value(gbl->gpiod, 1);
|
||||
+ udelay(START_TIME);
|
||||
+ for(i = 0; i < 8; i++) {
|
||||
+ if(data & 0x80) {
|
||||
+ write_bit(gbl, 1);
|
||||
+ } else {
|
||||
+ write_bit(gbl, 0);
|
||||
+ }
|
||||
+ data <<= 1;
|
||||
+ }
|
||||
+ gpiod_set_value(gbl->gpiod, 0);
|
||||
+ udelay(END_TIME);
|
||||
+ gpiod_set_value(gbl->gpiod, 1);
|
||||
+
|
||||
+ local_irq_restore(flags);
|
||||
+}
|
||||
+
|
||||
+unsigned char ocp8178_bl_table[MAX_BRIGHTNESS_VALUE+1] = {0, 1, 4, 8, 12, 16, 20, 24, 28, 31};
|
||||
+
|
||||
+static int ocp8178_update_status(struct backlight_device *bl)
|
||||
+{
|
||||
+ struct ocp8178_backlight *gbl = bl_get_data(bl);
|
||||
+ int brightness = bl->props.brightness, i;
|
||||
+
|
||||
+ if (bl->props.power != FB_BLANK_UNBLANK ||
|
||||
+ bl->props.fb_blank != FB_BLANK_UNBLANK ||
|
||||
+ bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
|
||||
+ brightness = 0;
|
||||
+
|
||||
+ if(brightness > MAX_BRIGHTNESS_VALUE)
|
||||
+ brightness = MAX_BRIGHTNESS_VALUE;
|
||||
+
|
||||
+ for(i = 0; i < 2; i++) {
|
||||
+ entry_1wire_mode(gbl);
|
||||
+ write_byte(gbl, ocp8178_bl_table[brightness]);
|
||||
+ }
|
||||
+ gbl->current_value = brightness;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ocp8178_get_brightness(struct backlight_device *bl)
|
||||
+{
|
||||
+ struct ocp8178_backlight *gbl = bl_get_data(bl);
|
||||
+ return gbl->current_value;
|
||||
+}
|
||||
+
|
||||
+static int ocp8178_check_fb(struct backlight_device *bl,
|
||||
+ struct fb_info *info)
|
||||
+{
|
||||
+ struct ocp8178_backlight *gbl = bl_get_data(bl);
|
||||
+ return gbl->fbdev == NULL || gbl->fbdev == info->dev;
|
||||
+}
|
||||
+
|
||||
+static const struct backlight_ops ocp8178_backlight_ops = {
|
||||
+ .options = BL_CORE_SUSPENDRESUME,
|
||||
+ .update_status = ocp8178_update_status,
|
||||
+ .get_brightness = ocp8178_get_brightness,
|
||||
+ .check_fb = ocp8178_check_fb,
|
||||
+};
|
||||
+
|
||||
+static int ocp8178_probe_dt(struct platform_device *pdev,
|
||||
+ struct ocp8178_backlight *gbl)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct device_node *np = dev->of_node;
|
||||
+ enum gpiod_flags flags;
|
||||
+ int ret = 0;
|
||||
+ u32 value32;
|
||||
+
|
||||
+ of_property_read_u32(np, "default-brightness", &value32);
|
||||
+ if(value32 > MAX_BRIGHTNESS_VALUE)
|
||||
+ gbl->def_value = MAX_BRIGHTNESS_VALUE;
|
||||
+ else
|
||||
+ gbl->def_value = value32;
|
||||
+ flags = gbl->def_value ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
|
||||
+
|
||||
+ gbl->gpiod = devm_gpiod_get(dev, "backlight-control", flags);
|
||||
+ if (IS_ERR(gbl->gpiod)) {
|
||||
+ ret = PTR_ERR(gbl->gpiod);
|
||||
+
|
||||
+ if (ret != -EPROBE_DEFER) {
|
||||
+ dev_err(dev,
|
||||
+ "Error: The gpios parameter is missing or invalid.\n");
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static struct backlight_device *backlight;
|
||||
+
|
||||
+static int ocp8178_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct backlight_properties props;
|
||||
+ struct backlight_device *bl;
|
||||
+ struct ocp8178_backlight *gbl;
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ int ret;
|
||||
+
|
||||
+ if ( !np) {
|
||||
+ dev_err(&pdev->dev,
|
||||
+ "failed to find platform data or device tree node.\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ gbl = devm_kzalloc(&pdev->dev, sizeof(*gbl), GFP_KERNEL);
|
||||
+ if (gbl == NULL)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ gbl->dev = &pdev->dev;
|
||||
+
|
||||
+ ret = ocp8178_probe_dt(pdev, gbl);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ gbl->current_value = gbl->def_value;
|
||||
+
|
||||
+ memset(&props, 0, sizeof(props));
|
||||
+ props.type = BACKLIGHT_RAW;
|
||||
+ props.max_brightness = MAX_BRIGHTNESS_VALUE;
|
||||
+ bl = devm_backlight_device_register(&pdev->dev, dev_name(&pdev->dev),
|
||||
+ &pdev->dev, gbl, &ocp8178_backlight_ops,
|
||||
+ &props);
|
||||
+ if (IS_ERR(bl)) {
|
||||
+ dev_err(&pdev->dev, "failed to register backlight\n");
|
||||
+ return PTR_ERR(bl);
|
||||
+ }
|
||||
+
|
||||
+// entry_1wire_mode(gbl);
|
||||
+
|
||||
+ bl->props.brightness = gbl->def_value;
|
||||
+ backlight_update_status(bl);
|
||||
+
|
||||
+ platform_set_drvdata(pdev, bl);
|
||||
+
|
||||
+ backlight = bl;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ocp8178_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ocp8178_resume(struct platform_device *pdev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct of_device_id ocp8178_of_match[] = {
|
||||
+ { .compatible = "ocp8178-backlight" },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+
|
||||
+MODULE_DEVICE_TABLE(of, ocp8178_of_match);
|
||||
+
|
||||
+static struct platform_driver ocp8178_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "ocp8178-backlight",
|
||||
+ .of_match_table = of_match_ptr(ocp8178_of_match),
|
||||
+ },
|
||||
+ .probe = ocp8178_probe,
|
||||
+ .suspend = ocp8178_suspend,
|
||||
+ .resume = ocp8178_resume,
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(ocp8178_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("OCP8178 Driver");
|
||||
+MODULE_LICENSE("GPL");
|
||||
@ -0,0 +1,24 @@
|
||||
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
|
||||
index fc3ec3714..05b0e7c8d 100644
|
||||
--- a/drivers/thermal/sun8i_thermal.c
|
||||
+++ b/drivers/thermal/sun8i_thermal.c
|
||||
@@ -139,6 +139,7 @@ static const struct thermal_zone_of_device_ops ths_ops = {
|
||||
};
|
||||
|
||||
static const struct regmap_config config = {
|
||||
+ .name = "thermal",
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
@@ -640,9 +641,9 @@ static const struct ths_thermal_chip sun50i_h5_ths = {
|
||||
static const struct ths_thermal_chip sun50i_h6_ths = {
|
||||
.sensor_num = 2,
|
||||
.has_bus_clk_reset = true,
|
||||
- .ft_deviation = 7000,
|
||||
+ .ft_deviation = -7000,
|
||||
.offset = 187744,
|
||||
- .scale = 672,
|
||||
+ .scale = 550,
|
||||
.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
|
||||
.calibrate = sun50i_h6_ths_calibrate,
|
||||
.init = sun50i_h6_thermal_init,
|
||||
@ -0,0 +1,73 @@
|
||||
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
|
||||
index 3e899253..7f4999fc 100644
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -603,6 +603,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
|
||||
sun50i-h5-orangepi-zero-plus2.dtb
|
||||
dtb-$(CONFIG_MACH_SUN50I_H6) += \
|
||||
sun50i-h6-beelink-gs1.dtb \
|
||||
+ sun50i-h6-clockworkpi-a04.dtb \
|
||||
sun50i-h6-orangepi-3.dtb \
|
||||
sun50i-h6-orangepi-lite2.dtb \
|
||||
sun50i-h6-orangepi-one-plus.dtb \
|
||||
diff --git a/arch/arm/dts/sun50i-h6-clockworkpi-a04.dts b/arch/arm/dts/sun50i-h6-clockworkpi-a04.dts
|
||||
new file mode 100644
|
||||
index 00000000..02651651
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/sun50i-h6-clockworkpi-a04.dts
|
||||
@@ -0,0 +1,38 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
||||
+/*
|
||||
+ * Copyright (C) 2018 Amarula Solutions
|
||||
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "sun50i-h6.dtsi"
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+
|
||||
+/ {
|
||||
+ model = "Clockworkpi A04";
|
||||
+ compatible = "clockwork,devterm-a04", "allwinner,sun50i-h6";
|
||||
+
|
||||
+ aliases {
|
||||
+ serial0 = &uart0;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&mmc0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&mmc0_pins>;
|
||||
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
|
||||
+ bus-width = <4>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart0_ph_pins>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
diff --git a/configs/clockworkpi-a04-h6_defconfig b/configs/clockworkpi-a04-h6_defconfig
|
||||
new file mode 100644
|
||||
index 00000000..4844c725
|
||||
--- /dev/null
|
||||
+++ b/configs/clockworkpi-a04-h6_defconfig
|
||||
@@ -0,0 +1,11 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_ARCH_SUNXI=y
|
||||
+CONFIG_MACH_SUN50I_H6=y
|
||||
+CONFIG_SUNXI_DRAM_H6_LPDDR3=n
|
||||
+CONFIG_SUNXI_DRAM_H6_DDR3_1333=y
|
||||
+CONFIG_DRAM_ODT_EN=y
|
||||
+CONFIG_MMC0_CD_PIN="PF6"
|
||||
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
+CONFIG_HDMI_DDC_EN="PH2"
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-clockworkpi-a04"
|
||||
+CONFIG_SPL=y
|
||||
Loading…
x
Reference in New Issue
Block a user