experimental FunKey DTS

This commit is contained in:
Michel-FK
2019-03-22 13:58:51 +01:00
parent 6edf1b86a5
commit 8b88601d04
17 changed files with 4483 additions and 60 deletions

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@@ -1,4 +1,4 @@
setenv bootargs console=ttyS0,115200 panic=5 console=tty0 rootwait fbcon=map:10 fbcon=font:VGA8x8 root=/dev/mmcblk0p2 earlyprintk rw
load mmc 0:1 0x41000000 zImage
load mmc 0:1 0x41800000 sun8i-v3s-licheepi-zero-dock.dtb
load mmc 0:1 0x41800000 sun8i-v3s-funkey.dtb
bootz 0x41000000 - 0x41800000

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@@ -2,8 +2,7 @@ image boot.vfat {
vfat {
files = {
"zImage",
"sun8i-v3s-licheepi-zero-dock.dtb",
"sun8i-v3s-licheepi-zero.dtb",
"sun8i-v3s-funkey.dtb",
"boot.scr"
}
}

File diff suppressed because it is too large Load Diff

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@@ -0,0 +1,52 @@
From 700384f1f3c204fa989fddd0ae73c2ebe76483a3 Mon Sep 17 00:00:00 2001
From: Michel Stempin <michel.stempin@wanadoo.fr>
Date: Tue, 19 Mar 2019 22:33:32 +0100
Subject: [PATCH 1/9] added uart1 & uart2 pins
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 6 ++++++
arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index b6f3430..18e9503 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -109,6 +109,12 @@
status = "okay";
};
+/*&uart2 {
+ pinctrl-0 = <&uart2_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};*/
+
&usb_otg {
dr_mode = "otg";
status = "okay";
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index e437d3f..6708af1 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -356,6 +356,16 @@
function = "uart0";
};
+ uart1_pins_a: uart1@0 {
+ pins = "PE21", "PE22";
+ function = "uart1";
+ };
+
+ uart2_pins_a: uart2@0 {
+ pins = "PB0", "PB1";
+ function = "uart2";
+ };
+
lcd_rgb666_pins_a: lcd-rgb666-pe {
pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5",
"PE6", "PE7", "PE8", "PE9", "PE10", "PE11",
--
2.7.4

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@@ -0,0 +1,88 @@
From 110d4a501c56aef0986baa5de9e629f11b6ab692 Mon Sep 17 00:00:00 2001
From: Michel Stempin <michel.stempin@wanadoo.fr>
Date: Tue, 19 Mar 2019 22:22:54 +0100
Subject: [PATCH 2/9] disabled LicheePi LEDs
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 4 ++--
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi | 5 +++++
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 11 ++++++-----
3 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
index d8b6833..0afd3af 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
@@ -54,8 +54,8 @@
};*/
leds {
- /* The LEDs use PG0~2 pins, which conflict with MMC1 */
- status = "disbaled";
+ // The LEDs use PG0~2 pins, which conflict with MMC1
+ status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi
index f7ed577..b7d8ff4 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi
@@ -30,6 +30,11 @@
};
};
};
+
+ leds {
+ // The LEDs use PG0~2 pins, which conflict with MMC1
+ status = "disabled";
+ };
};
&de {
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 18e9503..ded54df 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -50,31 +50,32 @@
aliases {
serial0 = &uart0;
+ //serial0 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
- leds {
+ /*leds {
compatible = "gpio-leds";
blue_led {
label = "licheepi:blue:usr";
- gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
+ gpios = <&pio 6 1 GPIO_ACTIVE_LOW 0x1>; // PG1 //
};
green_led {
label = "licheepi:green:usr";
- gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
+ gpios = <&pio 6 0 GPIO_ACTIVE_LOW 0x1>; // PG0 //
default-state = "on";
};
red_led {
label = "licheepi:red:usr";
- gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
+ gpios = <&pio 6 2 GPIO_ACTIVE_LOW 0x1>; // PG2 //
};
- };
+ };*/
};
&ehci0 {
--
2.7.4

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@@ -0,0 +1,35 @@
From 9163e2926190307570c421c5f6e06057fd87a224 Mon Sep 17 00:00:00 2001
From: Michel Stempin <michel.stempin@wanadoo.fr>
Date: Tue, 19 Mar 2019 22:48:08 +0100
Subject: [PATCH 3/9] removed USB OTG
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index ded54df..99785b0 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -116,7 +116,7 @@
status = "okay";
};*/
-&usb_otg {
+/*&usb_otg {
dr_mode = "otg";
status = "okay";
};
@@ -124,7 +124,7 @@
&usbphy {
usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
status = "okay";
-};
+};*/
&spi0 {
status = "okay";
--
2.7.4

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@@ -0,0 +1,76 @@
From c06a4ba80922341138853bf8cedaeef2cd533013 Mon Sep 17 00:00:00 2001
From: Michel Stempin <michel.stempin@wanadoo.fr>
Date: Tue, 19 Mar 2019 22:51:37 +0100
Subject: [PATCH 4/9] replaced backlight with PWM
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 6 ++++++
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi | 6 +++---
arch/arm/boot/dts/sun8i-v3s.dtsi | 5 +++++
3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
index 0afd3af..1c263c2 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
@@ -79,6 +79,12 @@
status = "okay";
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>;
+ status = "okay";
+};
+
&lradc {
vref-supply = <&reg_vcc3v0>;
status = "okay";
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi
index b7d8ff4..ad3fb39 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi
@@ -7,12 +7,12 @@
#include "sun8i-v3s-licheepi-zero.dts"
/ {
- backlight: backlight {
+ /*backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 30 40 50 60 70 100>;
default-brightness-level = <6>;
- };
+ };*/
panel: panel {
#address-cells = <1>;
@@ -20,7 +20,7 @@
port@0 {
reg = <0>;
- backlight = <&backlight>;
+ //backlight = <&backlight>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 6708af1..a61c680 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -351,6 +351,11 @@
function = "pwm0";
};
+ pwm1_pins: pwm1 {
+ pins = "PB5";
+ function = "pwm1";
+ };
+
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
--
2.7.4

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@@ -0,0 +1,34 @@
From fb026dd5d01a07b3fb2b172647924ddad2f2f863 Mon Sep 17 00:00:00 2001
From: Michel Stempin <michel.stempin@wanadoo.fr>
Date: Tue, 19 Mar 2019 22:53:38 +0100
Subject: [PATCH 5/9] remapped buttons
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
index 1c263c2..94657bd 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
@@ -105,14 +105,14 @@
button@600 {
label = "Select";
- linux,code = <KEY_SELECT>;
+ linux,code = <KEY_O>;
channel = <0>;
voltage = <600000>;
};
button@800 {
label = "Start";
- linux,code = <KEY_OK>;
+ linux,code = <KEY_P>;
channel = <0>;
voltage = <800000>;
};
--
2.7.4

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@@ -0,0 +1,32 @@
From a41e4bef4c48ef310617f7ca3a05d6ced241ab26 Mon Sep 17 00:00:00 2001
From: Michel Stempin <michel.stempin@wanadoo.fr>
Date: Tue, 19 Mar 2019 22:54:24 +0100
Subject: [PATCH 6/9] removed lradc
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
index 94657bd..71a8fea 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
@@ -85,7 +85,7 @@
status = "okay";
};
-&lradc {
+/*&lradc {
vref-supply = <&reg_vcc3v0>;
status = "okay";
@@ -116,4 +116,4 @@
channel = <0>;
voltage = <800000>;
};
-};
+};*/
--
2.7.4

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@@ -0,0 +1,31 @@
From 1e9535237bda590eb30e160603d760034aae1721 Mon Sep 17 00:00:00 2001
From: Michel Stempin <michel.stempin@wanadoo.fr>
Date: Tue, 19 Mar 2019 22:56:04 +0100
Subject: [PATCH 7/9] removed tcon0
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi
index ad3fb39..1c16e21 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-with-lcd.dtsi
@@ -47,11 +47,11 @@
status = "okay";
};
-&tcon0 {
+/*&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins_a>;
status = "okay";
-};
+};*/
&tcon0_out {
tcon0_out_lcd: endpoint@0 {
--
2.7.4

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@@ -0,0 +1,28 @@
From cd2a9cb732a65f5986b625d1c62cba7564215db9 Mon Sep 17 00:00:00 2001
From: Michel Stempin <michel.stempin@wanadoo.fr>
Date: Tue, 19 Mar 2019 22:57:35 +0100
Subject: [PATCH 8/9] remapped st7789v LCD GPIOs
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 99785b0..9d3b27f 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -138,8 +138,8 @@
rotate = <0>;
fps = <42>;
buswidth = <8>;
- reset-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>;
- dc-gpios = <&pio 1 5 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; //PE1
+ dc-gpios = <&pio 2 0 GPIO_ACTIVE_LOW>; //PC0 (MISO)
debug = <0>;
};
};
--
2.7.4

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@@ -0,0 +1,80 @@
From 538e97d56bae968580ac046389243383b7559ab9 Mon Sep 17 00:00:00 2001
From: Michel Stempin <michel.stempin@wanadoo.fr>
Date: Tue, 19 Mar 2019 22:26:56 +0100
Subject: [PATCH 9/9] rotated screen 90 degrees CW
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 2 +-
drivers/staging/fbtft/fb_st7789v.c | 13 ++++++++++---
drivers/staging/fbtft/fbtft-core.c | 8 +++++++-
3 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 9d3b27f..7bf06ab 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -135,7 +135,7 @@
spi-max-frequency = <40000000>;
txbuflen = <115200>;
- rotate = <0>;
+ rotate = <90>;
fps = <42>;
buswidth = <8>;
reset-gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; //PE1
diff --git a/drivers/staging/fbtft/fb_st7789v.c b/drivers/staging/fbtft/fb_st7789v.c
index 69f52af..e966993 100644
--- a/drivers/staging/fbtft/fb_st7789v.c
+++ b/drivers/staging/fbtft/fb_st7789v.c
@@ -150,9 +150,6 @@ static int init_display(struct fbtft_par *par)
*/
write_reg(par, PWCTRL1, 0xA4, 0xA1);
- /* Ystart at 80 , Yend at 240 */
- write_reg(par, 0x2B, 0x00, 0x50, 0x00, 0xF0);
-
/* Display Inversion of colors */
write_reg(par, 0x21);
@@ -190,6 +187,16 @@ static int set_var(struct fbtft_par *par)
return -EINVAL;
}
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, madctl_par);
+
+ // All offset operations are done after in fbtft_set_addr_win, not here
+ /* Ystart at 0 , Yend at 239 */
+ //write_reg(par, 0x2B, 0x00, 0x50, 0x00, 0xEF);
+ write_reg(par, 0x2B, 0x00, 0x00, 0x00, 0xEF);
+ //write_reg(par, 0x2B, 0x00, 0x50, 0x01, 0x3F);
+ /* Xstart at 80 , Xend at 319 */
+ write_reg(par, 0x2A, 0x00, 0x50, 0x01, 0x3F);
+ //write_reg(par, 0x2A, 0x00, 0x50, 0x00, 0xEF);
+
return 0;
}
diff --git a/drivers/staging/fbtft/fbtft-core.c b/drivers/staging/fbtft/fbtft-core.c
index 6d0363d..fbb0934 100644
--- a/drivers/staging/fbtft/fbtft-core.c
+++ b/drivers/staging/fbtft/fbtft-core.c
@@ -391,9 +391,15 @@ static void fbtft_update_display(struct fbtft_par *par, unsigned int start_line,
fbtft_par_dbg(DEBUG_UPDATE_DISPLAY, par, "%s(start_line=%u, end_line=%u)\n",
__func__, start_line, end_line);
- if (par->fbtftops.set_addr_win)
+ // Carefull removing this. this will work only if the full screen is updated at once
+ /*if (par->fbtftops.set_addr_win){
par->fbtftops.set_addr_win(par, 0, start_line,
par->info->var.xres - 1, end_line);
+ }*/
+ if (par->fbtftops.set_addr_win){
+ par->fbtftops.set_addr_win(par, 80, start_line,
+ 320 - 1, end_line);
+ }
offset = start_line * par->info->fix.line_length;
len = (end_line - start_line + 1) * par->info->fix.line_length;
--
2.7.4

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@@ -0,0 +1,162 @@
/*
* Copyright (C) 2019 Michel Stempin <michel.stempin@wanadoo.fr>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-v3s.dtsi"
#include "sunxi-common-regulators.dtsi"
#include "axp209.dtsi"
/ {
model = "FunKey";
compatible = "funkey", "allwinner,sun8i-v3s";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <10>;
};
};
&codec {
allwinner,audio-routing =
"Headphone", "HP",
"Headphone", "HPCOM",
"MIC1", "Mic",
"Mic", "HBIAS";
status = "okay";
};
&ehci0 {
status = "okay";
};
&i2c0 {
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
&mmc0 {
pinctrl-0 = <&mmc0_pins_a>;
pinctrl-names = "default";
broken-cd;
bus-width = <4>;
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&ohci0 {
status = "okay";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpu-sys-ephy";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3450000>;
regulator-name = "vcc-io-ephy-mcsi-usb";
};
&reg_ldo1 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3600000>;
regulator-name = "vcc-rtc";
};
&reg_ldo2 {
regulator-always-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "avcc-pll";
};
&spi0 {
status = "okay";
st7789v@0 {
compatible = "sitronix,st7789v";
reg = <0>;
spi-max-frequency = <40000000>;
txbuflen = <115200>;
rotate = <90>;
fps = <42>;
buswidth = <8>;
reset-gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; //PE1
dc-gpios = <&pio 2 0 GPIO_ACTIVE_LOW>; //PC0 (MISO)
debug = <0>;
};
};
&uart0 {
pinctrl-0 = <&uart0_pins_a>;
pinctrl-names = "default";
status = "okay";
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pins>;
status = "okay";
};

View File

@@ -1,10 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
# CONFIG_ARMV7_NONSEC is not set
CONFIG_IDENT_STRING=" FunKey"
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=14779
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-funkey"
CONFIG_BOOTDELAY=0
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL=y