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docs/developer_guide/hardware_reference/cpu.md
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docs/developer_guide/hardware_reference/cpu.md
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The main part in the **FunKey S** device is of course its CPU.
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As discussed in the [Design Constraints section][1], a CPU with
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external DRAM chips would take too much real-estate on the PCB, so we
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had to find a CPU with integrated DRAM.
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There are [several options][2] for integrating RAM in a SoC:
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- use SRAM: not possible because of the small amount of memory
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available (64Mbit max.)
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- embedded DRAM on the same chip: This is the solution used in the
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[Apple M1 chip][3], but this chip is not available for retail and
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no other solutions seems readily available
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- Stacked Chip-on-Chip (PoP): This is the solution used on some
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Raspberry Pi boards, but this solution is only available for custom
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designs, with minimum order quantities not compatible with the
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**FunKey S** low volumes
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- DRAM die in SiP: with capacities ranging from 64Mbit to 1Gbit
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We found only 2 manufacturers providing the last option:
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[Microchip][4] and [Allwinner Technology][5]. Microchip solutions are
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too limited in term of CPU power for our needs (ARM926EJ-S or Cortex
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A5), so we did not consider them.
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And with the exception of the mostly similar Allwinner S3 CPU which
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features the same characteristics but with 128MB DDR3 DRAM in an
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FBGA234 package, the [Allwinner V3s][6] is the CPU with integrated
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DRAM having the highest memory capacity (512Mbit / 64MB DDR2 DRAM):
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Despite its larger package size (16mm x 16mm vs. 11mm x 11mm), we
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selected the V3s over the S3 because of its better availability and
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ease of soldering of the LQFP128 over the FBGA234 package for the
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prototypes.
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The V3s features a rather powerful single-core ARM Cortex A7-A clocked
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@ 1.2GHz with an additional Vector Floating Point Version 4 (vfpv4)
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FPU extension and an SIMD NEON architecture with a 32 × 64-bit
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register file and 64-bit ALU, but unfortunately no GPU or 2D graphic
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engine containing a hardware scaler that could be extremely useful for
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the retro-gaming emulators.
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As a bonus, as the V3s is based on an ARM Cortex A7-A low-power
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architecture, it also features a low power consumption which is
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required by our battery operation.
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These characteristics do not look very impressive compared to a
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Raspberry Pi for example, but using many optimizations and after
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running many tests, we found them nevertheless satisfactory for our
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purpose.
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## CPU Schematics
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Here is the part of the schematics corresponding to the CPU core:
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{.lightbox}
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## SoC Blocks
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As can be seen, there is not much besides the CPU chip **U3**
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itself... The CPU is in fact a SoC (System on Chip) containing a
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collection of built-in peripheral and memory blocks along with the CPU
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itself:
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- the LCD / DSi display peripheral
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- the GPIO port G / SDC1 (SD Card #1) interface
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- the AUDIO codec
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- the LRADC0 (Low-Resolution Analog to Digital Converter)
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- the USB OTG controller
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- the GPIO port F / SDC0 (SD Card #0) / UART0 interface
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- the RTC (Real Time Clock) timer
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- the EPHY (Ethernet PHYsical) interface
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- the MIPI CSi camera interface
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- the built-in 64 MB DDR2 DRAM
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- the GPIO port C / SPI interface
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- the GPIO port B / UART2 / PWM0 / PWM1 / TWI0 (I2C #0) / TWI1 (I2C
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#1)
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Among these, the FunKey device only uses a few blocks:
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- AUDIO
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- USB (as device only)
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- SDC0 (for SD Card)
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- RTC
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- DRAM
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- SPI (for the LCD screen)
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- PWM0 (for backlight)
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- TWI0 (for I2C bus to control the GPIO expander and power management
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chips)
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- A couple of GPIOs to power the audio power amplifier and get
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feedback interrupt signals from the the GPIO expander and power
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management chips
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## CPU Power Supplies
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What is remarkable though is that the V3s requires a lot of different
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voltages for its power supply:
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- +3V3 for the I/O power supply
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- +3V3_AO for the Always-On power supply (RTC timer)
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- +3V0 for analog power supply
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- +1V8 for the DDR2 DRAM power supply
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- +1V25 for the core power supply
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This profusion of different power supplies as well as the high power
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drawn by some of them (1.2A for +3V3, 1.6A for +1.25V) requires a
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sophisticated power management that will be detailed further.
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## LRADC0
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The LRADC0 (Low-Resolution Analog to Digital Converter #0) is designed
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to measure the voltage of a resistor ladder switched by keyboard keys:
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this single input is thus in theory able to manage a keyboard of up to
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10 keys @ 250 Hz.
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Unfortunately, the FunKey has 12 keys (U/D/L/R, A/B/X/Y, RR/RL, Start
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and Fn), and the resulting key detection accuracy is not compatible
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with a gaming usage because of long term stability problems. This is
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the reason why it is not used in the FunKey and just terminated by a
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proper low-pass filter **R6**/**C9** to avoid picking up noise
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glitches.
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## SD Card
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The SD Card interface is almost a direct connection between the chip
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and the dedicated SD Card connector. Only a single series resistor
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**R8** is required on the high-speed clock line in order to [prevent
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ringing][7].
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## Crystals
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The V3s chips requires 2 crystals:
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- one low-frequency [32.768 kHz crystal][8] **Y1** for the RTC clock
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- one high-frequency [24 MHz crystal][9] **Y2** for deriving the 1.2
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GHz clock
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The 24 MHz crystal is used by an internal oscillator to lock the phase
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of the 1.2 GHz oscillator using a PLL (Phase-Locked Loop).
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The 32.768 kHz crystal is used by another internal oscillator to tick
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the RTC (Real-Time Clock) at a standard watch frequency.
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These crystals require 2 load capacitors each (**C12**/**C13** and
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**C14**/**C15** respectively) in order to guarantee that the
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oscillators still start and work with a comfortable operation margin
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taking into account voltage, temperature and aging.
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The 32.768 kHz crystal features an additional high-value resistor
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**R12** in order to limit the internal oscillator's output current and
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thus reduce further the RTC timer power consumption.
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For more details on crystal oscillator design, please check [this
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application note from STM][10].
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## DRAM
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The DRAM within the V3s chip is a [DDR2 one][11], meaning that its
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data lines are clocked using both edges of an up to 400 MHz clock
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signal.
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At these high frequencies, even short wires have a length that is of
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the same order of magnitude as the signal's [wavelength][12] and thus
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each signal should be considered as a [transmission line][13], for
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which impedance must be matched to avoid signal reflections, requiring
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termination resistors on the data lines DQx.
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DDR2 or DDR3 DRAMs feature merged drivers and dynamic on-chip
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termination like this ("VDDQ/2" is labeled "SVREF" in our schematic):
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{.lightbox}
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The V3s DDR2 DRAM has an active termination calibration circuitry and
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procedure called "_ZQ Calibration_" requiring an accurate 1% 240 Ω
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resistor **R11** connected internally like this:
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{.lightbox}
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More information on the DDR2 DRAM ZQ Calibration subject can be found
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in this [Micron Application Note][14].
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[1]: /developers/hardware/design/#design-constraints
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[2]: https://www.electronicsweekly.com/news/products/memory/how-to-guide-for-on-chip-memory-2012-06/
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[3]: https://www.apple.com/mac/m1/
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[4]: https://www.microchip.com/design-centers/32-bit-mpus/sip-som/system-in-package
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[5]: https://www.allwinnertech.com/
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[6]: https://linux-sunxi.org/images/f/f5/Allwinner_V3_Datasheet_V1.1.pdf
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[7]: https://electronics.stackexchange.com/questions/7709/why-put-a-resistor-in-series-with-signal-line
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[8]: https://github.com/FunKey-Project/FunKey-S-Hardware/blob/master/Datasheets/C55208_FC-12M32.768K12.5PF20PPM_2017-01-16.PDF
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[9]: https://github.com/FunKey-Project/FunKey-S-Hardware/blob/master/Datasheets/C270485_24MHZ18PF%C2%B110PPM4PIN-20_%2B70%E2%84%83_2018-08-14.PDF
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[10]: https://www.st.com/content/ccc/resource/technical/document/application_note/c6/eb/5e/11/e3/69/43/eb/CD00221665.pdf/files/CD00221665.pdf/jcr:content/translations/en.CD00221665.pdf
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[11]: https://en.wikipedia.org/wiki/DDR2_SDRAM
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[12]: https://en.wikipedia.org/wiki/Wavelength
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[13]: https://en.wikipedia.org/wiki/Transmission_line
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[14]: https://www.micron.com/-/media/client/global/Documents/Products/Technical%20Note/DRAM/TN4102.pdf
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--8<--
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includes/glossary.md
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--8<--
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