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Reimplement cache invalidation code

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This commit is contained in:
twinaphex
2014-12-11 18:47:48 +01:00
parent 97166d5cbd
commit 5b59ef3acc
8 changed files with 58 additions and 180 deletions
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25
arm/arm_emit.h
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@@ -636,33 +636,8 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
} \
} \
u8 *last_rom_translation_ptr = NULL;
u8 *last_ram_translation_ptr = NULL;
u8 *last_bios_translation_ptr = NULL;
#define translate_invalidate_dcache_one(which) \
if (which##_translation_ptr > last_##which##_translation_ptr) \
{ \
warm_cache_op_range(WOP_D_CLEAN, last_##which##_translation_ptr, \
which##_translation_ptr - last_##which##_translation_ptr); \
warm_cache_op_range(WOP_I_INVALIDATE, last_##which##_translation_ptr, 32);\
last_##which##_translation_ptr = which##_translation_ptr; \
}
#define translate_invalidate_dcache() \
{ \
translate_invalidate_dcache_one(rom) \
translate_invalidate_dcache_one(ram) \
translate_invalidate_dcache_one(bios) \
}
#define invalidate_icache_region(addr, size) \
warm_cache_op_range(WOP_I_INVALIDATE, addr, size)
#define block_prologue_size 0
// It should be okay to still generate result flags, spsr will overwrite them.
// This is pretty infrequent (returning from interrupt handlers, et al) so
// probably not worth optimizing for.

67
arm/warm.c
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@@ -1,67 +0,0 @@
/*
* wARM - exporting ARM processor specific privileged services to userspace
* userspace part
*
* Copyright (c) Gražvydas "notaz" Ignotas, 2009
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the organization nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/syscall.h>
#include <errno.h>
#include "warm.h"
static void sys_cacheflush(void *start, void *end)
{
#ifdef __ARM_EABI__
/* EABI version */
int num = __ARM_NR_cacheflush;
__asm__("mov r0, %0 ;"
"mov r1, %1 ;"
"mov r2, #0 ;"
"mov r7, %2 ;"
"swi 0" : : "r" (start), "r" (end), "r" (num)
: "r0", "r1", "r2", "r3", "r7");
#else
/* OABI */
__asm__("mov r0, %0 ;"
"mov r1, %1 ;"
"mov r2, #0 ;"
"swi %2" : : "r" (start), "r" (end), "i" __ARM_NR_cacheflush
: "r0", "r1", "r2", "r3");
#endif
}
int warm_cache_op_range(int op, void *addr, unsigned long size)
{
sys_cacheflush(addr, (char *)addr + size);
return -1;
}

53
arm/warm.h
View File

@@ -1,53 +0,0 @@
/*
* wARM - exporting ARM processor specific privileged services to userspace
* library functions
*
* Copyright (c) Gražvydas "notaz" Ignotas, 2009
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the organization nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __WARM_H__
#define __WARM_H__ 1
/* cache operations (warm_cache_op_*):
* o clean - write dirty data to memory, but also leave in cache.
* o invalidate - throw away everything in cache, losing dirty data.
*
* Write buffer is always drained, no ops will only drain WB
*/
#define WOP_D_CLEAN (1 << 0)
#define WOP_D_INVALIDATE (1 << 1)
#define WOP_I_INVALIDATE (1 << 2)
#ifdef __cplusplus
extern "C"
{
#endif
int warm_cache_op_range(int ops, void *virt_addr, unsigned long size);
#ifdef __cplusplus
}
#endif
#endif /* __WARM_H__ */