mirror of
https://github.com/FunKey-Project/gpsp_libretro.git
synced 2026-03-18 18:02:45 +01:00
cpu clock setup, save rom dir, cleanups
This commit is contained in:
notaz
@@ -34,7 +34,6 @@ INCLUDES = `$(PREFIX)/bin/sdl-config --cflags` -I$(PREFIX)/include
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LIBS = `$(PREFIX)/bin/sdl-config --libs` \
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-lm -ldl -lpthread -lz
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ifneq ($(WIZ),1)
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OBJS += cpuctrl_mmsp2.o
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LIBS += -static
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endif
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@@ -1,486 +0,0 @@
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/* cpuctrl.c for GP2X (CPU/LCD/RAM-Tuner Version 2.0)
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Copyright (C) 2006 god_at_hell
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original CPU-Overclocker (c) by Hermes/PS2Reality
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the gamma-routine was provided by theoddbot
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parts (c) Rlyehs Work
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/****************************************************************************************************************************************/
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// CPU CONTROL
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/****************************************************************************************************************************************/
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//#include <sys/mman.h>
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#include <math.h>
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#include <stdio.h>
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//#include "gp2xminilib.h"
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#define SYS_CLK_FREQ 7372800
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//from minimal library rlyeh
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//extern unsigned long gp2x_dev[4];
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extern unsigned short *gp2x_memregs;
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// system registers
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static struct
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{
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unsigned short SYSCLKENREG,SYSCSETREG,FPLLVSETREG,DUALINT920,DUALINT940,DUALCTRL940,DISPCSETREG,MEMTIMEX0;
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unsigned short MEMTIMEX1,MEMREFX,MLC_GAMM_BYPATH,MLC_GAMMA_A,MLC_GAMMA_D,YBNKLVL;
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}
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system_reg;
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volatile unsigned short *MEM_REG;
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unsigned MDIV,PDIV,SCALE;
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volatile unsigned *arm940code;
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void cpuctrl_init()
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{
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MEM_REG=&gp2x_memregs[0];
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}
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void save_system_regs()
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{
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system_reg.SYSCSETREG=MEM_REG[0x91c>>1];
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system_reg.FPLLVSETREG=MEM_REG[0x912>>1];
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system_reg.SYSCLKENREG=MEM_REG[0x904>>1];
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system_reg.DUALINT920=MEM_REG[0x3B40>>1];
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system_reg.DUALINT940=MEM_REG[0x3B42>>1];
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system_reg.DUALCTRL940=MEM_REG[0x3B48>>1];
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system_reg.DISPCSETREG=MEM_REG[0x924>>1];
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system_reg.MEMTIMEX0=MEM_REG[0x3802>>1];
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system_reg.MEMTIMEX1=MEM_REG[0x3804>>1];
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system_reg.MEMREFX=MEM_REG[0x3808>>1];
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system_reg.MLC_GAMM_BYPATH=MEM_REG[0x2880>>1];
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system_reg.MLC_GAMMA_A=MEM_REG[0x295C>>1];
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system_reg.MLC_GAMMA_D=MEM_REG[0x295E>>1];
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system_reg.YBNKLVL=MEM_REG[0x283A>>1];
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}
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void load_system_regs()
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{
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MEM_REG[0x91c>>1]=system_reg.SYSCSETREG;
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MEM_REG[0x910>>1]=system_reg.FPLLVSETREG;
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MEM_REG[0x3B40>>1]=system_reg.DUALINT920;
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MEM_REG[0x3B42>>1]=system_reg.DUALINT940;
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MEM_REG[0x3B48>>1]=system_reg.DUALCTRL940;
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MEM_REG[0x904>>1]=system_reg.SYSCLKENREG;
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/* Set UPLLSETVREG to 0x4F02, which gives 80MHz */
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MEM_REG[0x0914>>1] = 0x4F02;
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/* Wait for clock change to start */
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while (MEM_REG[0x0902>>1] & 2);
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/* Wait for clock change to be verified */
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while (MEM_REG[0x0916>>1] != 0x4F02);
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MEM_REG[0x3802>>1]=system_reg.MEMTIMEX0;
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MEM_REG[0x3804>>1]=system_reg.MEMTIMEX1;
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MEM_REG[0x3808>>1]=system_reg.MEMREFX;
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MEM_REG[0x2880>>1]=system_reg.MLC_GAMM_BYPATH;
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MEM_REG[0x295C>>1]=system_reg.MLC_GAMMA_A;
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MEM_REG[0x295E>>1]=system_reg.MLC_GAMMA_D;
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MEM_REG[0x283A>>1]=system_reg.YBNKLVL;
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}
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void set_FCLK(unsigned MHZ)
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{
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printf ("set CPU-Frequency = %uMHz\r\n",MHZ);
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unsigned v;
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unsigned mdiv,pdiv=3,scale=0;
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MHZ*=1000000;
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mdiv=(MHZ*pdiv)/SYS_CLK_FREQ;
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//printf ("Old value = %04X\r",MEM_REG[0x924>>1]," ");
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//printf ("APLL = %04X\r",MEM_REG[0x91A>>1]," ");
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mdiv=((mdiv-8)<<8) & 0xff00;
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pdiv=((pdiv-2)<<2) & 0xfc;
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scale&=3;
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v=mdiv | pdiv | scale;
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MEM_REG[0x910>>1]=v;
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}
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unsigned get_FCLK()
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{
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return MEM_REG[0x910>>1];
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}
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#if 0
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void set_add_FLCDCLK(int addclock)
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{
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//Set LCD controller to use FPLL
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printf ("...set to FPLL-Clockgen...\r\n");
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printf ("set Timing-Prescaler = %i\r\n",addclock);
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MEM_REG[0x924>>1]= 0x5A00 + ((addclock)<<8);
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//If you change the initial timing, don't forget to shift your intervall-borders in "cpu_speed.c"
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}
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void set_add_ULCDCLK(int addclock)
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{
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//Set LCD controller to use UPLL
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printf ("...set to UPLL-Clockgen...\r\n");
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printf ("set Timing-Prescaler = %i\r\n",addclock);
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MEM_REG[0x0924>>1] = 0x8900 + ((addclock)<<8);
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//If you change the initial timing, don't forget to shift your intervall-borders in "cpu_speed.c"
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}
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unsigned get_LCDClk()
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{
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if (MEM_REG[0x0924>>1] < 0x7A01) return((MEM_REG[0x0924>>1] - 0x5A00)>>8);
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else return((MEM_REG[0x0924>>1] - 0x8900)>>8);
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}
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char get_Clkgen()
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{
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if (MEM_REG[0x0924>>1] < 0x7A01) return(0);
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else return(1);
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}
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unsigned get_freq_UCLK()
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{
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unsigned i;
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unsigned reg,mdiv,pdiv,scale;
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i = MEM_REG[0x900>>1];
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i = ((i >> 7) & 1) ;
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if(i) return 0;
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reg=MEM_REG[0x916>>1];
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mdiv = ((reg & 0xff00) >> 8) + 8;
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pdiv = ((reg & 0xfc) >> 2) + 2;
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scale = reg & 3;
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return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale));
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}
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unsigned get_freq_ACLK()
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{
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unsigned i;
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unsigned reg,mdiv,pdiv,scale;
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i = MEM_REG[0x900>>1];
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i = ((i >> 8) & 1) ;
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if(i) return 0;
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reg=MEM_REG[0x918>>1];
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mdiv = ((reg & 0xff00) >> 8) + 8;
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pdiv = ((reg & 0xfc) >> 2) + 2;
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scale = reg & 3;
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return ((SYS_CLK_FREQ * mdiv)/(pdiv << scale));
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}
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unsigned get_freq_920_CLK()
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{
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unsigned i;
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unsigned reg,mdiv,pdiv,scale;
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reg=MEM_REG[0x912>>1];
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mdiv = ((reg & 0xff00) >> 8) + 8;
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pdiv = ((reg & 0xfc) >> 2) + 2;
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scale = reg & 3;
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MDIV=mdiv;
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PDIV=pdiv;
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SCALE=scale;
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i = (MEM_REG[0x91c>>1] & 7)+1;
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return ((SYS_CLK_FREQ * mdiv)/(pdiv << scale))/i;
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}
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unsigned get_freq_940_CLK()
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{
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unsigned i;
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unsigned reg,mdiv,pdiv,scale;
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reg=MEM_REG[0x912>>1];
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mdiv = ((reg & 0xff00) >> 8) + 8;
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pdiv = ((reg & 0xfc) >> 2) + 2;
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scale = reg & 3;
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i = ((MEM_REG[0x91c>>1]>>3) & 7)+1;
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return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale))/i;
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}
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unsigned get_freq_DCLK()
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{
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unsigned i;
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unsigned reg,mdiv,pdiv,scale;
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reg=MEM_REG[0x912>>1];
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mdiv = ((reg & 0xff00) >> 8) + 8;
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pdiv = ((reg & 0xfc) >> 2) + 2;
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scale = reg & 3;
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i = ((MEM_REG[0x91c>>1]>>6) & 7)+1;
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return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale))/i;
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}
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void set_920_Div(unsigned short div)
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{
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printf ("set divider for CPU-Clock = %u\r\n",div+1);
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unsigned short v;
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v = MEM_REG[0x91c>>1] & (~0x3);
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MEM_REG[0x91c>>1] = (div & 0x7) | v;
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}
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unsigned short get_920_Div()
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{
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return (MEM_REG[0x91c>>1] & 0x7);
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}
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void set_940_Div(unsigned short div)
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{
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unsigned short v;
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v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 3)));
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MEM_REG[0x91c>>1] = ((div & 0x7) << 3) | v;
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}
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unsigned short get_940_Div()
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{
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return ((MEM_REG[0x91c>>1] >> 3) & 0x7);
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}
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void set_DCLK_Div( unsigned short div )
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{
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printf ("set divider for RAM-Clock = %u\r\n",div+1);
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unsigned short v;
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v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 6)));
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MEM_REG[0x91c>>1] = ((div & 0x7) << 6) | v;
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}
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unsigned short get_DCLK_Div()
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{
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return ((MEM_REG[0x91c>>1] >> 6) & 0x7);
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}
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unsigned short Disable_Int_920()
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{
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unsigned short ret;
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ret=MEM_REG[0x3B40>>1];
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MEM_REG[0x3B40>>1]=0;
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MEM_REG[0x3B44>>1]=0xffff;
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return ret;
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}
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unsigned short Disable_Int_940()
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{
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unsigned short ret;
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ret=MEM_REG[0x3B42>>1];
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MEM_REG[0x3B42>>1]=0;
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MEM_REG[0x3B46>>1]=0xffff;
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return ret;
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}
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unsigned get_state940()
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{
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return MEM_REG[0x904>>1];
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}
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void Enable_Int_920(unsigned short flag)
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{
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MEM_REG[0x3B40>>1]=flag;
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}
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void Enable_Int_940(unsigned short flag)
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{
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MEM_REG[0x3B42>>1]=flag;
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}
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void Disable_940()
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{
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Disable_Int_940();
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MEM_REG[0x3B48>>1]|= (1 << 7);
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MEM_REG[0x904>>1]&=0xfffe;
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}
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void Load_940_code(unsigned *code,int size)
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{
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unsigned *cp;
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int i;
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arm940code=(unsigned short *)mmap(0, 0x100000, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], 0x03000000);
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Disable_940();
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cp=(unsigned *) code;
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for (i = 0; i < size/4; i ++)
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{
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arm940code[i] = cp[i];
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}
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for (i = 0; i < 64; i ++)
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{
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arm940code[0x3FC0+i] = 0;
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}
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MEM_REG[0x3B48>>1]=(MEM_REG[0x3B48>>1] & 0xFF00) | 0x03; // allow 940
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}
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void clock_940_off()
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{
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MEM_REG[0x904>>1]&=0xfffe;
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}
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void clock_940_on()
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{
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MEM_REG[0x904>>1]|=1;
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}
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#endif
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//--------------
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//Memory Timings
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//--------------
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//get
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unsigned get_CAS()
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{
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return ((MEM_REG[0x3804>>1] >> 12) & 0x1);
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}
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unsigned get_tRC()
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{
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return ((MEM_REG[0x3804>>1] >> 8) & 0xF);
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}
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unsigned get_tRAS()
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{
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return ((MEM_REG[0x3804>>1] >> 4) & 0xF);
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}
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|
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unsigned get_tWR()
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{
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return (MEM_REG[0x3804>>1] & 0xF);
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}
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unsigned get_tMRD()
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{
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return ((MEM_REG[0x3802>>1] >> 12) & 0xF);
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}
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unsigned get_tRFC()
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{
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return ((MEM_REG[0x3802>>1] >> 8) & 0xF);
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}
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|
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unsigned get_tRP()
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{
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return ((MEM_REG[0x3802>>1] >> 4) & 0xF);
|
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}
|
||||
|
||||
unsigned get_tRCD()
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{
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return (MEM_REG[0x3802>>1] & 0xF);
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}
|
||||
|
||||
unsigned get_REFPERD()
|
||||
{
|
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return MEM_REG[0x3808>>1];
|
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}
|
||||
|
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|
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//set
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||||
|
||||
void set_CAS(unsigned short timing)
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||||
{
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printf ("set CAS = %u\r\n",timing+2);
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unsigned short v;
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v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0x1 << 12)));
|
||||
MEM_REG[0x3804>>1] = ((timing & 0x1) << 12) | v;
|
||||
}
|
||||
|
||||
void set_tRC(unsigned short timing)
|
||||
{
|
||||
printf ("set tRC = %u\r\n",timing+1);
|
||||
unsigned short v;
|
||||
v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF << 8)));
|
||||
MEM_REG[0x3804>>1] = ((timing & 0xF) << 8) | v;
|
||||
}
|
||||
|
||||
void set_tRAS(unsigned short timing)
|
||||
{
|
||||
printf ("set tRAS = %u\r\n",timing+1);
|
||||
unsigned short v;
|
||||
v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF << 4)));
|
||||
MEM_REG[0x3804>>1] = ((timing & 0xF) << 4) | v;
|
||||
}
|
||||
|
||||
void set_tWR(unsigned short timing)
|
||||
{
|
||||
printf ("set tWR = %u\r\n",timing+1);
|
||||
unsigned short v;
|
||||
v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF)));
|
||||
MEM_REG[0x3804>>1] = (timing & 0xF) | v;
|
||||
}
|
||||
|
||||
void set_tMRD(unsigned short timing)
|
||||
{
|
||||
printf ("set tMRD = %u\r\n",timing+1);
|
||||
unsigned short v;
|
||||
v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 12)));
|
||||
MEM_REG[0x3802>>1] = ((timing & 0xF) << 12) | v;
|
||||
}
|
||||
|
||||
void set_tRFC(unsigned short timing)
|
||||
{
|
||||
printf ("set tRFC = %u\r\n",timing+1);
|
||||
unsigned short v;
|
||||
v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 8)));
|
||||
MEM_REG[0x3802>>1] = ((timing & 0xF) << 8) | v;
|
||||
}
|
||||
|
||||
void set_tRP(unsigned short timing)
|
||||
{
|
||||
printf ("set tRP = %u\r\n",timing+1);
|
||||
unsigned short v;
|
||||
v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 4)));
|
||||
MEM_REG[0x3802>>1] = ((timing & 0xF) << 4) | v;
|
||||
}
|
||||
|
||||
void set_tRCD(unsigned short timing)
|
||||
{
|
||||
printf ("set tRCD = %u\r\n",timing+1);
|
||||
unsigned short v;
|
||||
v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF)));
|
||||
MEM_REG[0x3802>>1] = (timing & 0xF) | v;
|
||||
}
|
||||
|
||||
void set_REFPERD(unsigned short timing)
|
||||
{
|
||||
printf ("set Refresh Period = %u\r\n",timing+1);
|
||||
MEM_REG[0x3808>>1] = timing;
|
||||
}
|
||||
|
||||
|
||||
//-----
|
||||
//Gamma
|
||||
//-----
|
||||
|
||||
void set_gamma(float gamma)
|
||||
{
|
||||
printf ("set gamma = %f\r\n",gamma);
|
||||
int i;
|
||||
gamma = 1/gamma;
|
||||
|
||||
//enable gamma
|
||||
MEM_REG[0x2880>>1]&=~(1<<12);
|
||||
|
||||
MEM_REG[0x295C>>1]=0;
|
||||
for(i=0; i<256; i++)
|
||||
{
|
||||
unsigned char g;
|
||||
unsigned short s;
|
||||
g =(unsigned char)(255.0*pow(i/255.0,gamma));
|
||||
s = (g<<8) | g;
|
||||
MEM_REG[0x295E>>1]= s;
|
||||
MEM_REG[0x295E>>1]= g;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned get_YBNKLVL()
|
||||
{
|
||||
return (MEM_REG[0x283A>>1] & 0x3FF);
|
||||
}
|
||||
|
||||
void set_YBNKLVL(unsigned short val)
|
||||
{
|
||||
unsigned short temp = (unsigned short)(MEM_REG[0x3808>>1] & (~(0x3FF)));
|
||||
MEM_REG[0x3808>>1] = (val & 0x3FF) | temp;
|
||||
}
|
||||
@@ -1,8 +0,0 @@
|
||||
@ vim:filetype=armasm
|
||||
|
||||
.global gp2x_flush_cache @ beginning_addr, end_addr, flags
|
||||
|
||||
gp2x_flush_cache:
|
||||
swi #0x9f0002
|
||||
mov pc, lr
|
||||
|
||||
94
gp2x/gp2x.c
94
gp2x/gp2x.c
@@ -19,16 +19,17 @@
|
||||
*/
|
||||
|
||||
|
||||
#define _BSD_SOURCE
|
||||
#define _GNU_SOURCE
|
||||
#include <sys/mman.h>
|
||||
#include <sys/ioctl.h>
|
||||
#include <sys/soundcard.h>
|
||||
#include <sys/types.h>
|
||||
#include <unistd.h>
|
||||
#include "../common.h"
|
||||
#include "gp2x.h"
|
||||
#include "warm.h"
|
||||
|
||||
extern int main_cpuspeed(int argc, char *argv[]);
|
||||
extern SDL_Surface* screen;
|
||||
|
||||
u32 gp2x_audio_volume = 74/2;
|
||||
u32 gpsp_gp2x_dev_audio = 0;
|
||||
u32 gpsp_gp2x_dev = 0;
|
||||
@@ -36,24 +37,6 @@ u32 gpsp_gp2x_gpiodev = 0;
|
||||
|
||||
static volatile u16 *gpsp_gp2x_memregs;
|
||||
static volatile u32 *gpsp_gp2x_memregl;
|
||||
unsigned short *gp2x_memregs;
|
||||
|
||||
s32 gp2x_load_mmuhack()
|
||||
{
|
||||
s32 mmufd = open("/dev/mmuhack", O_RDWR);
|
||||
|
||||
if(mmufd < 0)
|
||||
{
|
||||
system("/sbin/insmod mmuhack.o");
|
||||
mmufd = open("/dev/mmuhack", O_RDWR);
|
||||
}
|
||||
|
||||
if(mmufd < 0)
|
||||
return -1;
|
||||
|
||||
close(mmufd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef WIZ_BUILD
|
||||
#include <linux/fb.h>
|
||||
@@ -140,27 +123,55 @@ static void fb_video_exit()
|
||||
|
||||
void gp2x_init()
|
||||
{
|
||||
FILE *f;
|
||||
gpsp_gp2x_dev = open("/dev/mem", O_RDWR);
|
||||
gpsp_gp2x_dev_audio = open("/dev/mixer", O_RDWR);
|
||||
gpsp_gp2x_memregl =
|
||||
(unsigned long *)mmap(0, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED,
|
||||
gpsp_gp2x_dev, 0xc0000000);
|
||||
gpsp_gp2x_memregs = (unsigned short *)gpsp_gp2x_memregl;
|
||||
warm_init();
|
||||
#ifdef WIZ_BUILD
|
||||
gpsp_gp2x_gpiodev = open("/dev/GPIO", O_RDONLY);
|
||||
warm_init();
|
||||
fb_video_init();
|
||||
#endif
|
||||
|
||||
// clear_screen(0);
|
||||
// main_cpuspeed(0, NULL);
|
||||
gp2x_memregs = (void *)gpsp_gp2x_memregs;
|
||||
cpuctrl_init();
|
||||
f = fopen("romdir.txt", "r");
|
||||
if (f != NULL)
|
||||
{
|
||||
char buff[256];
|
||||
char *s = fgets(buff, sizeof(buff) - 1, f);
|
||||
if (s)
|
||||
{
|
||||
int r = strlen(s);
|
||||
while (r > 0 && isspace(buff[r-1]))
|
||||
buff[--r] = 0;
|
||||
chdir(buff);
|
||||
}
|
||||
fclose(f);
|
||||
}
|
||||
|
||||
gp2x_sound_volume(1);
|
||||
}
|
||||
|
||||
#include <errno.h>
|
||||
void gp2x_quit()
|
||||
{
|
||||
char buff[256];
|
||||
FILE *f;
|
||||
|
||||
getcwd(buff, sizeof(buff));
|
||||
chdir(main_path);
|
||||
f = fopen("romdir.txt", "r+");
|
||||
if (f != NULL)
|
||||
{
|
||||
fprintf(f, "%s", buff);
|
||||
fclose(f);
|
||||
truncate("romdir.txt", strlen(buff));
|
||||
sync();
|
||||
}
|
||||
|
||||
warm_finish();
|
||||
#ifdef WIZ_BUILD
|
||||
close(gpsp_gp2x_gpiodev);
|
||||
fb_video_exit();
|
||||
@@ -169,6 +180,7 @@ void gp2x_quit()
|
||||
close(gpsp_gp2x_dev_audio);
|
||||
close(gpsp_gp2x_dev);
|
||||
|
||||
fcloseall();
|
||||
//chdir("/usr/gp2x");
|
||||
//execl("gp2xmenu", "gp2xmenu", NULL);
|
||||
exit(0);
|
||||
@@ -219,13 +231,29 @@ u32 gpsp_gp2x_joystick_read(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef WIZ_BUILD
|
||||
void cpuctrl_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
// Fout = (m * Fin) / (p * 2^s)
|
||||
void set_FCLK(u32 MHZ)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
u32 v;
|
||||
u32 mdiv, pdiv, sdiv = 0;
|
||||
#ifdef WIZ_BUILD
|
||||
#define SYS_CLK_FREQ 27
|
||||
// m = MDIV, p = PDIV, s = SDIV
|
||||
pdiv = 9;
|
||||
mdiv = (MHZ * pdiv) / SYS_CLK_FREQ;
|
||||
mdiv &= 0x3ff;
|
||||
v = (pdiv<<18) | (mdiv<<8) | sdiv;
|
||||
|
||||
gpsp_gp2x_memregl[0xf004>>2] = v;
|
||||
gpsp_gp2x_memregl[0xf07c>>2] |= 0x8000;
|
||||
#else
|
||||
#define SYS_CLK_FREQ 7372800
|
||||
// m = MDIV + 8, p = PDIV + 2, s = SDIV
|
||||
pdiv = 3;
|
||||
mdiv = (MHZ * pdiv * 1000000) / SYS_CLK_FREQ;
|
||||
mdiv &= 0xff;
|
||||
v = ((mdiv-8)<<8) | ((pdiv-2)<<2) | sdiv;
|
||||
gpsp_gp2x_memregs[0x910>>1] = v;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
18
gp2x/gp2x.h
18
gp2x/gp2x.h
@@ -1,6 +1,8 @@
|
||||
#ifndef GP2X_H
|
||||
#define GP2X_H
|
||||
|
||||
#include "warm.h"
|
||||
|
||||
enum
|
||||
{
|
||||
GP2X_UP = 1 << 0,
|
||||
@@ -33,23 +35,9 @@ extern u32 gpsp_gp2x_dev;
|
||||
void gp2x_sound_volume(u32 volume_up);
|
||||
void gp2x_quit();
|
||||
|
||||
// call this at first
|
||||
void cpuctrl_init(void);
|
||||
void save_system_regs(void);
|
||||
void cpuctrl_deinit(void);
|
||||
void set_display_clock_div(unsigned div);
|
||||
|
||||
void set_FCLK(u32 MHZ);
|
||||
// 0 to 7 divider (freq = FCLK / (1 + div))
|
||||
void set_920_Div(u16 div);
|
||||
void set_DCLK_Div(u16 div);
|
||||
|
||||
void Disable_940(void);
|
||||
void gp2x_video_wait_vsync(void);
|
||||
unsigned short get_920_Div();
|
||||
void set_940_Div(u16 div);
|
||||
|
||||
s32 gp2x_load_mmuhack();
|
||||
void upscale_aspect(u16 *dst, u16 *src);
|
||||
|
||||
/* wiz only */
|
||||
extern void *gpsp_gp2x_screen;
|
||||
|
||||
Reference in New Issue
Block a user