[3DS] Fix dynarec prefetch aborts

Similar fix to https://github.com/libretro/pcsx_rearmed/pull/390. The
Nintendo svcBackdoor can cause stack corruption if an interrupt
happens during it, this uses Luma3DS/Rosalina's svcCustomBackdoor instead.
This commit is contained in:
Justin Weiss
2020-02-29 10:50:30 -08:00
parent 4d6846b4b7
commit 6a50b8a68d
5 changed files with 52 additions and 4 deletions

25
3ds/3ds_cache_utils.S Normal file
View File

@@ -0,0 +1,25 @@
.text
.arm
.balign 4
.func ctr_clear_cache_kernel
ctr_clear_cache_kernel:
cpsid aif
mov r0, #0
mcr p15, 0, r0, c7, c10, 0 @ Clean entire data cache
mcr p15, 0, r0, c7, c10, 5 @ Data Memory Barrier
mcr p15, 0, r0, c7, c5, 0 @ Invalidate entire instruction cache / Flush BTB
mcr p15, 0, r0, c7, c10, 4 @ Data Sync Barrier
bx lr
.endfunc
@@ Clear the entire data cache / invalidate the instruction cache. Uses
@@ Rosalina svcCustomBackdoor to avoid svcBackdoor stack corruption
@@ during interrupts.
.global ctr_clear_cache
.func ctr_clear_cache
ctr_clear_cache:
ldr r0, =ctr_clear_cache_kernel
svc 0x80 @ svcCustomBackdoor
bx lr
.endfunc

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@@ -7,6 +7,20 @@
typedef s32 (*ctr_callback_type)(void);
void check_rosalina() {
int64_t version;
uint32_t major;
has_rosalina = false;
if (!svcGetSystemInfo(&version, 0x10000, 0)) {
major = GET_VERSION_MAJOR(version);
if (major >= 8)
has_rosalina = true;
}
}
static void ctr_invalidate_ICache_kernel(void)
{
__asm__ volatile(
@@ -38,6 +52,10 @@ void ctr_flush_DCache(void)
void ctr_flush_invalidate_cache(void)
{
ctr_flush_DCache();
ctr_invalidate_ICache();
if (has_rosalina) {
ctr_clear_cache();
} else {
ctr_flush_DCache();
ctr_invalidate_ICache();
}
}

View File

@@ -7,6 +7,10 @@ void ctr_flush_invalidate_cache(void);
extern __attribute((weak)) unsigned int __ctr_svchax;
bool has_rosalina;
void check_rosalina();
void ctr_clear_cache(void);
void wait_for_input();
#define DEBUG_HOLD() do{printf("%s@%s:%d.\n",__FUNCTION__, __FILE__, __LINE__);fflush(stdout);wait_for_input();}while(0)
#define DEBUG_VAR(X) printf( "%-20s: 0x%08X\n", #X, (u32)(X))