233 Commits

Author	SHA1	Message	Date
kub	79f45561fe	sh2 drc, register cache optimisations	2020-07-04 14:49:26 +02:00
kub	e9a3de1ed4	sh2 drc, block management bugfixes and cleanup	2020-07-04 14:49:26 +02:00
kub	835adf871d	sh2 drc, add detection for in-memory polling	2020-07-04 14:49:26 +02:00
kub	0b520c1014	sh2 drc, add loop detector, handle delay/idle loops	2020-07-04 14:49:26 +02:00
kub	a0bef37586	sh2 drc, code emitter cleanup, add ARM reorder stage to reduce interlock	2020-07-04 14:49:26 +02:00
kub	6caa1fa6e1	sh2 drc, make B/W read functions signed (reduces generated code size)	2020-07-04 14:49:26 +02:00
kub	74385d04c3	sh2 drc, improved constant handling and register allocator	2020-07-04 14:49:26 +02:00
kub	c77e3bf5e7	add literal pool to sh2 drc (for armv[456] without MOVT/W)	2020-07-04 14:49:26 +02:00
kub	87316e5941	sh2 drc, reuse blocks if already previously compiled (speedup for Virtua *)	2020-07-04 14:49:26 +02:00
kub	1f8cc9c081	various small improvements and fixes	2020-07-04 14:49:26 +02:00
kub	48fdcb0390	overhaul of translation cache and sh2 literals handling	2020-07-04 14:49:25 +02:00
kub	65072b8181	added branch cache to sh2 drc to improve cross-tcache jump speed	2020-07-04 14:49:25 +02:00
kub	5f166c638c	sh2 memory interface optimzations	2020-07-04 14:49:25 +02:00
kub	24f21f3b8a	overhaul of the register cache (improves generated code by some 10+%)	2020-07-04 14:49:25 +02:00
kub	2d133c17d6	debug stuff, bug fixing	2020-07-04 14:49:25 +02:00
kub	94eb72693c	move saving SH2 SR into memory access and do so only if needed	2020-07-04 14:49:25 +02:00
kub	38e9622eb6	add 32bit memory access functions for SH2	2020-07-04 14:49:25 +02:00
kub	4eb73cb54b	sh2 drc: sh2 addr modes generalization, more const propagation, code gen optimizations	2020-07-04 14:49:25 +02:00
kub	771d8aca0f	DRC: reworked scan_block (fix register usage masks, better block and literals detection)	2020-07-04 14:49:25 +02:00
kub	59ea3b20f8	kludges for wwf raw, nfl	2020-07-04 14:49:25 +02:00
kub	ac29016a8c	improved sh2 clock handling, bug fixing + small improvement to drc emitters	2020-07-04 14:49:25 +02:00
kub	4766b9309a	sh2 drc host disassembler integration for gp2x	2020-07-04 14:49:25 +02:00
kub	fb13cb3c2e	bfd-less arm disassembler for gph	2020-07-04 14:49:25 +02:00
twinaphex	2a66db8f7b	(MSVC) Should fix MSVC and hopefully not cause regressions	2020-01-07 17:53:43 +01:00
Francisco Javier Trujillo Mata	baacd5e1b6	Make compile libretro for PS2	2019-02-02 00:02:20 +01:00
twinaphex	ad9c4345b3	Update	2019-01-04 19:22:36 +01:00
Alberto Fustinoni	a6f7458471	Using VFS	2018-06-21 16:22:09 +09:00
notaz	6b8652a8a2	32x: implement standard/ssf2 mapper	2018-01-22 19:05:58 +01:00
notaz	fda2f31020	drc: support ms ABI	2018-01-07 01:20:00 +02:00
notaz	48c9e01be8	improve 64bit portability ... for win64 mostly	2018-01-06 21:29:59 +02:00
notaz	898d51a7fd	drc: revive x86 dynarec, support x86-64	2017-12-12 01:45:59 +02:00
notaz	98a3d79ba2	drc: arm: use movw/movt ... it's about time...	2017-12-03 17:44:33 +02:00
notaz	00468b0a9b	drc: do lit check before size_nolit is cleared	2017-12-03 17:44:33 +02:00
notaz	d602fd4f73	drc: ignore cache-through on smc check	2017-12-03 17:44:33 +02:00
notaz	f0ed9e38ad	drc: rm overlapped block entry points ... otherwise we get duplicates in hash tables	2017-12-03 17:44:33 +02:00
notaz	93f9619ed8	rearrange globals ... scripted find/replace gives slightly better code on ARM, less unnecessary asm, ~400 bytes saved	2017-10-20 12:21:09 +03:00
notaz	759c9d3846	pandora: fix build ... Fixes: df9251536de "libretro: satisfy vita's dynarec needs in a cleaner way"	2017-10-20 12:20:59 +03:00
notaz	7669591e08	famec: eliminate global context ptr ... saves like 25-35K of .text current compile resource usage on i5-6600K: cpu mem gcc 5.4.0: 17.0 1.1g clang 3.8: 1686 2.3g FAMEC_NO_GOTOS: gcc 5.4.0: 8.4 0.4g clang 3.8: 20.0 0.15g vs2008/O2: ~1800 ? vs2008/O1: ~720 ?	2017-10-15 03:26:48 +03:00
notaz	12f23dac6f	famec: split fm68k_emulate ... in FAMEC_NO_GOTOS mode at least	2017-10-15 00:45:55 +03:00
notaz	e9a11abb3c	drop some unnecessary inlines ... apparently somebody compiles with msvc?	2017-10-14 00:53:09 +03:00
notaz	b5f5dc1fad	android: make armeabi buildable	2017-10-14 00:53:09 +03:00
notaz	df9251536d	libretro: satisfy vita's dynarec needs in a cleaner way	2017-10-14 00:53:09 +03:00
notaz	bce144211c	some portability cleanups	2017-10-14 00:53:09 +03:00
notaz	c041308933	fame: fix roxr ... also take interrupts on exit, like other cores do	2017-10-14 00:53:08 +03:00
notaz	2b15cea82e	workaround idledet breaking op test	2017-09-20 23:47:09 +03:00
notaz	c6e1e9779a	68k cores: fix bcd instructions ... passing flamewing's test now	2017-09-20 23:47:09 +03:00
notaz	f6aa2456a4	famec: adjust divu timing ... it's wrong, but I need it to be consistent with other cores now	2017-09-20 23:47:09 +03:00
notaz	5c5d89adbb	famec: fix CHK	2017-09-20 23:47:09 +03:00
notaz	8d998330d0	famec: improve trace a bit ... or break it (nobody uses it anyway), just want m68k_opcode_sizes to pass	2017-09-20 23:47:09 +03:00
notaz	a39743e315	musashi: don't generate unneeded handlers ... at least move16 was incorrectly hooked up	2017-09-20 23:47:09 +03:00