PDP_AS(1)

NAME
pdp_as - assembler for PDP 11

SYNOPSIS
/usr/em/lib/pdp_as [options] argument ...

DESCRIPTION
This assembler is made with the general framework described in uni_ass(6).

SYNTAX

registers
    The pdp11 has seven general registers, numbered r0 through r7. Of these, r6 is the stack pointer and can also be referenced to by sp, r7 is the program counter and has pc as synonym. There are also six floating-point registers fr0 through fr5, but the names r0 through r5 can also be used. From the context will be derived what kind of register is meant.

addressing modes
    syntax		meaning (name)
    reg		contents of register reg is operand.
    		(register)
    (reg)		contents of reg is address of operand.
    		(register deferred)
    (reg)+		as (reg), but after the operand is fetched
    		the contents of reg is incremented by the
    		size of the operand. (auto-increment)
    *(reg)+		contents of reg points to address of the operand.
    		after the operand is fetched, reg is incremented
    		by two. (auto-increment deferred)
    -(reg)		as (reg), but before the operand is fetched
    		the contents of reg is decremented by the
    		size of the operand. (auto-decrement)
    *-(reg)		before the operand is fetched, reg is decremented
    		by two. then the contents of reg points to the
    		address of the operand. (auto-decrement deferred)
    expr(reg)	value of expr + contents of reg yields address
    		of operand. (index)
    *expr(reg)	value of expr + contents of reg yields pointer
    		to address of operand. (index deferred)
    $expr		the value of expr is the operand. (immediate)
    *$expr		the value of expr is the address of the operand.
    		(absolute)
    expr		expr is address of operand. (relative)
    *expr		expr points to the address of the operand.
    		(relative deferred)

condition code instructions
    Two or more of the "clear" instructions (clc, cln, clv, clz), or two or more of the "set" instructions (sec, sen, sev, sez) may be or-ed together with `|' to yield a instruction that clears or sets two or more of the condition-bits. Scc and ccc are not predefined.

extended branches
    The assembler recognizes conditional branches with a "j" substituted for the "b". When the target is too remote for a simple branch, a converse branch over a jmp to the target is generated. Likewise jbr assembles into either br or jmp.

floating-point instructions
    The names of several floating-point instructions differ from the names in the handbook mentioned below. Synonyms ending in "d" for instructions ending in "f" are not recognized. Some instructions have different names; the mapping is as below.
    handbook		pdp_as
    ldcif, ldclf,
    ldcid, ldcld		movif
    stcfi, stcfl,
    stcdi, stcdl		movfi
    ldcdf, ldcfd		movof
    stcdf, stcfd		movfo
    ldexp			movie
    stexp			movei
    ldd, ldf		movf
    std, stf		movf
    The movf instruction assembles into stf, when the first operand is one of the first three floating-point registers, otherwise it assembles into ldf.

sys This instruction is synonymous with trap.

EXAMPLE
An example of pdp11 assembly code.
!this is the routine that reads numbers into r0
!the number is terminated by any non digit
!the non digit is left in r1
innum:	clr r3		!r3 will accumulate the number
inloop:	jsr pc,_getchar	!read a character into r0
	cmp r0,$0121	!is it a Q?
	jeq quit
	cmp r0,$48	!is the character a digit?
	jlt indone	!digits 0-9 have codes 060-071 octal
	cmp r0,$56
	jgt indone
	mul $10,r3	!r3 = 10 * r3
	sub $48,r3	!convert ascii code to numerical value
	add r0,r3	!r3 = old sum * 10 + new digi
	jbr inloop
indone:	mov r0,r1	!put the first non digit into r1
	mov r3,r0	!put the number read into r0
	rts pc		!return to caller

SEE ALSO
uni_ass(6), ack(1),
PDP11/60 processor handbook, Digital Equipment Corporation, 1977

BUGS
You cannot use *reg in place of (reg). Likewise *(reg) is not understood as *0(reg).