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Skeleton of VideoCore IV support for the Raspberry Pi.

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--HG--
branch : dtrg-videocore
rename : mach/powerpc/as/.distr => mach/vc4/as/.distr
rename : mach/powerpc/as/mach0.c => mach/vc4/as/mach0.c
rename : mach/powerpc/as/mach1.c => mach/vc4/as/mach1.c
rename : mach/powerpc/as/mach2.c => mach/vc4/as/mach2.c
rename : mach/powerpc/as/mach3.c => mach/vc4/as/mach3.c
rename : mach/powerpc/as/mach4.c => mach/vc4/as/mach4.c
rename : mach/powerpc/as/mach5.c => mach/vc4/as/mach5.c
rename : mach/i86/build.mk => mach/vc4/build.mk
rename : mach/powerpc/libem/powerpc.h => mach/vc4/libem/videocore.h
rename : mach/i86/libend/.distr => mach/vc4/libend/.distr
rename : mach/i86/libend/edata.s => mach/vc4/libend/edata.s
rename : mach/i86/libend/em_end.s => mach/vc4/libend/em_end.s
rename : mach/i86/libend/end.s => mach/vc4/libend/end.s
rename : mach/i86/libend/etext.s => mach/vc4/libend/etext.s
rename : mach/powerpc/ncg/.distr => mach/vc4/ncg/.distr
rename : mach/powerpc/ncg/mach.c => mach/vc4/ncg/mach.c
rename : mach/powerpc/ncg/mach.h => mach/vc4/ncg/mach.h
rename : mach/powerpc/ncg/table => mach/vc4/ncg/table
rename : plat/pc86/descr => plat/rpi/descr
This commit is contained in:
David Given
2013-05-17 00:03:38 +01:00
parent e5f6d5acfa
commit 32ebc502c8
42 changed files with 3355 additions and 0 deletions
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6
mach/vc4/as/.distr Normal file
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mach0.c
mach1.c
mach2.c
mach3.c
mach4.c
mach5.c

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mach/vc4/as/binary.h Normal file
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/*
* VideoCore IV assembler for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
#ifndef BINARY_H
#define BINARY_H
/* This grotesque nonsense allows us to use binary constants from C. */
#define HEX__(n) 0x##n##LU
#define B8__(x) \
((x&0x0000000FLU)?1:0) \
+((x&0x000000F0LU)?2:0) \
+((x&0x00000F00LU)?4:0) \
+((x&0x0000F000LU)?8:0) \
+((x&0x000F0000LU)?16:0) \
+((x&0x00F00000LU)?32:0) \
+((x&0x0F000000LU)?64:0) \
+((x&0xF0000000LU)?128:0)
#define B8(d) \
((unsigned char)B8__(HEX__(d)))
#define B16(dmsb,dlsb) \
(((unsigned short)B8(dmsb)<<8) + B8(dlsb))
#define B32(dmsb,db2,db3,dlsb) \
(((unsigned long)B8(dmsb)<<24) \
+ ((unsigned long)B8(db2)<<16) \
+ ((unsigned long)B8(db3)<<8) \
+ B8(dlsb))
#endif

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/*
* VideoCore IV assembler for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
#define THREE_PASS /* branch and offset optimization */
#define LISTING /* enable listing facilities */
#define RELOCATION /* generate relocatable code */
#define DEBUG 0
#undef valu_t
#define valu_t long
#undef ADDR_T
#define ADDR_T long
#undef word_t
#define word_t long
#undef ALIGNWORD
#define ALIGNWORD 4
#undef ALIGNSECT
#define ALIGNSECT 4
#undef VALWIDTH
#define VALWIDTH 8
#define FIXUPFLAGS (RELBR | RELWR)

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/*
* VideoCore IV assembler for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/

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/*
* VideoCore IV assembler for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
%token <y_word> GPR
%token <y_word> OP
%token <y_word> OP_ONEREG
%token <y_word> OP_ONELREG
%token <y_word> OP_ALU
%token <y_word> OP_MEM
%token <y_word> OP_BREG
%token <y_word> OP_STACK
/* Other token types */
/* %type <y_word> c */
%type <y_word> e16 u8 u7 u6 u5 u4 u2 u1
/* %type <y_word> nb ds bda bdl lia lil */

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/*
* VideoCore IV assembler for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
#include "binary.h"
/* Integer registers */
0, GPR, 0, "r0",
0, GPR, 1, "r1",
0, GPR, 2, "r2",
0, GPR, 3, "r3",
0, GPR, 4, "r4",
0, GPR, 5, "r5",
0, GPR, 6, "r6",
0, GPR, 6, "fp",
0, GPR, 7, "r7",
0, GPR, 8, "r8",
0, GPR, 9, "r9",
0, GPR, 10, "r10",
0, GPR, 11, "r11",
0, GPR, 12, "r12",
0, GPR, 13, "r13",
0, GPR, 14, "r14",
0, GPR, 15, "r15",
0, GPR, 16, "r16",
0, GPR, 17, "r17",
0, GPR, 18, "r18",
0, GPR, 19, "r19",
0, GPR, 20, "r20",
0, GPR, 21, "r21",
0, GPR, 22, "r22",
0, GPR, 23, "r23",
0, GPR, 24, "r24",
0, GPR, 25, "r25",
0, GPR, 25, "sp",
0, GPR, 26, "r26",
0, GPR, 26, "lr",
0, GPR, 27, "r27",
0, GPR, 28, "r28",
0, GPR, 29, "r29",
0, GPR, 30, "r30",
0, GPR, 30, "sr",
0, GPR, 31, "r31",
0, GPR, 31, "pc",
/* Special instructions */
0, OP, B16(00000000,00000001), "nop",
0, OP, B16(00000000,00001010), "rti",
0, OP_ONEREG, B16(00000000,01000000), "b",
0, OP_ONEREG, B16(00000000,01100000), "bl",
0, OP_ONELREG, B16(00000000,10000000), "tbb",
0, OP_ONELREG, B16(00000000,10100000), "tbs",
0, OP_ALU, B8(00000000), "mov",
0, OP_ALU, B8(00000001), "cmn",
0, OP_ALU, B8(00000010), "add",
0, OP_ALU, B8(00000011), "bic",
0, OP_ALU, B8(00000100), "mul",
0, OP_ALU, B8(00000101), "eor",
0, OP_ALU, B8(00000110), "sub",
0, OP_ALU, B8(00000111), "and",
0, OP_ALU, B8(00001000), "mvn",
0, OP_ALU, B8(00001001), "ror",
0, OP_ALU, B8(00001010), "cmp",
0, OP_ALU, B8(00001011), "rsb",
0, OP_ALU, B8(00001100), "btst",
0, OP_ALU, B8(00001101), "or",
0, OP_ALU, B8(00001110), "extu",
0, OP_ALU, B8(00001111), "max",
0, OP_ALU, B8(00010000), "bset",
0, OP_ALU, B8(00010001), "min",
0, OP_ALU, B8(00010010), "bclr",
0, OP_ALU, B8(00010011), "adds2",
0, OP_ALU, B8(00010100), "bchg",
0, OP_ALU, B8(00010101), "adds4",
0, OP_ALU, B8(00010110), "adds8",
0, OP_ALU, B8(00010111), "adds16",
0, OP_ALU, B8(00011000), "exts",
0, OP_ALU, B8(00011001), "neg",
0, OP_ALU, B8(00011010), "lsr",
0, OP_ALU, B8(00011011), "clz",
0, OP_ALU, B8(00011100), "lsl",
0, OP_ALU, B8(00011101), "brev",
0, OP_ALU, B8(00011110), "asr",
0, OP_ALU, B8(00011111), "abs",

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/*
* VideoCore IV assembler for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
#include "binary.h"
operation
: OP { emit2($1); }
| OP_ONEREG GPR
{
emit2($1 | ($2<<0));
}
| OP_ONELREG GPR
{
if ($2 >= 0x10)
serror("cannot use r16+ here");
emit2($1 | ($2<<0));
}
| OP_ALU GPR ',' GPR
{
emit2(B16(01000000, 00000000) | ($1<<8) | ($2<<0) | ($4<<4));
}
| OP_ALU GPR ',' '#' u5
{
if ($1 >= 0x10)
serror("cannot use this ALU operation in 2op form");
emit2(B16(01100000, 00000000) | ($1<<9) | ($2<<0) | ($5<<4));
}
;
e16
: expr
{
DOTVAL += 2;
newrelo($1.typ, RELO2 | FIXUPFLAGS);
DOTVAL -= 2;
$$ = $1.val & 0xFFFF;
}
;
u8
: absexp
{
if (($1 < 0) || ($1 > 0xFF))
serror("8-bit unsigned value out of range");
$$ = $1;
}
;
u7
: absexp
{
if (($1 < 0) || ($1 > 0x7F))
serror("7-bit unsigned value out of range");
$$ = $1;
}
;
u6
: absexp
{
if (($1 < 0) || ($1 > 0x3F))
serror("6-bit unsigned value out of range");
$$ = $1;
}
;
u5
: absexp
{
if (($1 < 0) || ($1 > 0x1F))
serror("5-bit unsigned value out of range");
$$ = $1;
}
;
u4
: absexp
{
if (($1 < 0) || ($1 > 0xF))
serror("4-bit unsigned value out of range");
$$ = $1;
}
;
u1
: absexp
{
if (($1 < 0) || ($1 > 1))
serror("1-bit unsigned value out of range");
$$ = $1;
}
;
u2
: absexp
{
if (($1 < 0) || ($1 > 0x3))
serror("2-bit unsigned value out of range");
$$ = $1;
}
;

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/*
* VideoCore IV assembler for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/

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arch-libem-vc4 := \
dummy.s
arch-libend-vc4 = \
edata.s \
em_end.s \
end.s \
etext.s

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#
/*
* VideoCore IV support library for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
#include "videocore.h"

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#
/*
* VideoCore IV support library for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
! Declare segments (the order is important).
.sect .text
.sect .rom
.sect .data
.sect .bss

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edata.s
em_end.s
end.s
etext.s

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#
/*
* VideoCore IV support library for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
.sect .text
.sect .rom
.sect .data
.sect .bss
.define _edata
.sect .data
_edata:

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#
/*
* VideoCore IV support library for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
.sect .text
.sect .rom
.sect .data
.sect .bss
.sect .end ! only for declaration of _end, __end and endbss.
.define endtext, endrom, enddata, endbss, __end
.sect .text
endtext:
.sect .rom
endrom:
.sect .data
enddata:
.sect .end
__end:
endbss:

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#
/*
* VideoCore IV support library for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
.sect .text
.sect .rom
.sect .data
.sect .bss
.define _end
.sect .end ! only for declaration of _end, __end and endbss.
_end:

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#
/*
* VideoCore IV support library for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
.sect .text
.sect .rom
.sect .data
.sect .bss
.define _etext
.sect .text
_etext:

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mach.c
mach.h
table

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/*
* VideoCore IV code generator for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
#include <stdlib.h>
#include <limits.h>
#ifndef NORCSID
static char rcsid[]= "$Id$" ;
#endif
int framesize;
/*
* machine dependent back end routines for the Zilog Z80.
*/
con_part(int sz, word w)
{
while (part_size % sz)
part_size++;
if (part_size == TEM_WSIZE)
part_flush();
if (sz == 1) {
w &= 0xFF;
w <<= 8*(3-part_size);
part_word |= w;
} else if (sz == 2) {
w &= 0xFFFF;
if (part_size == 0) {
/* Shift 8 for m68k2, 16 otherwise */
w <<= 4 * TEM_WSIZE;
}
part_word |= w;
} else {
assert(sz == TEM_WSIZE);
part_word = w;
}
part_size += sz;
}
con_mult(word sz)
{
if (argval != 4)
fatal("bad icon/ucon size");
fprintf(codefile,".data4 %s\n", str);
}
#define CODE_GENERATOR
#define IEEEFLOAT
#define FL_MSL_AT_LOW_ADDRESS 1
#define FL_MSW_AT_LOW_ADDRESS 1
#define FL_MSB_AT_LOW_ADDRESS 1
#include <con_float>
prolog(full nlocals)
{
int ss = nlocals + 8;
fprintf(codefile, "addi sp, sp, %d\n", -ss);
fprintf(codefile, "stw fp, %d(sp)\n", nlocals);
fprintf(codefile, "mfspr r0, lr\n"
"stw r0, %d(sp)\n", nlocals+4);
fprintf(codefile, "addi fp, sp, %d\n", nlocals);
framesize = nlocals;
}
mes(word type)
{
int argt ;
switch ( (int)type ) {
case ms_ext :
for (;;) {
switch ( argt=getarg(
ptyp(sp_cend)|ptyp(sp_pnam)|sym_ptyp) ) {
case sp_cend :
return ;
default:
strarg(argt) ;
fprintf(codefile,".define %s\n",argstr) ;
break ;
}
}
default :
while ( getarg(any_ptyp) != sp_cend ) ;
break ;
}
}
char *segname[] = {
".sect .text",
".sect .data",
".sect .rom",
".sect .bss"
};
#ifdef REGVARS
static int savedregsi[32];
static int numsaved;
/* Initialise regvar system for one function. */
i_regsave()
{
int i;
fprintf(codefile, "! i_regsave()\n");
for (i=0; i<32; i++)
savedregsi[i] = INT_MAX;
numsaved = 0;
}
/* Mark a register as being saved. */
regsave(const char* regname, full offset, int size)
{
int regnum = atoi(regname+1);
savedregsi[regnum] = offset;
numsaved++;
fprintf(codefile, "! %d is saved in %s\n", offset, regname);
#if 0
fprintf(codefile, "stwu %s, -4(sp)\n", regname);
if (offset >= 0)
fprintf(codefile, "lwz %s, %d(fp)\n", regname, offset);
#endif
}
/* Finish saving ragisters. */
void saveloadregs(const char* ops, const char* opm)
{
int offset = -(framesize + numsaved*4);
int reg = 32;
/* Check for the possibility of a multiple. */
do
{
reg--;
}
while ((reg > 0) && (savedregsi[reg] != INT_MAX));
if (reg < 31)
{
fprintf(codefile, "%s r%d, %d(fp)\n", opm, reg+1, offset);
offset += (31-reg)*4;
}
/* Saved everything else singly. */
while (reg > 0)
{
if (savedregsi[reg] != INT_MAX)
{
fprintf(codefile, "%s r%d, %d(fp)\n", ops, reg, offset);
offset += 4;
}
reg--;
}
}
f_regsave()
{
int i;
fprintf(codefile, "! f_regsave()\n");
fprintf(codefile, "addi sp, sp, %d\n", -numsaved*4);
saveloadregs("stw", "stmw");
for (i=0; i<32; i++)
if ((savedregsi[i] != INT_MAX) && (savedregsi[i] > 0))
fprintf(codefile, "lwz r%d, %d(fp)\n", i, savedregsi[i]);
}
/* Restore all saved registers. */
regreturn()
{
fprintf(codefile, "! regreturn()\n");
saveloadregs("lwz", "lmw");
}
/* Calculate the score of a given register. */
int regscore(full offset, int size, int type, int frequency, int totype)
{
int score;
fprintf(codefile, "! regscore(%ld, %d, %d, %d, %d)\n", offset, size, type, frequency, totype);
if (size != 4)
return -1;
/* Per use: 6 bytes (on average)
* Overhead in prologue: 4 bytes, plus 4 if a parameter
* Overhead in epilogue: 0 bytes
*/
score = frequency*6 - 4 - ((offset>=0) ? 4 : 0);
fprintf(codefile, "! local at offset %d has regvar score %d\n", offset, score);
return score;
}
#endif

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/*
* VideoCore IV code generator for the ACK
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
#define ex_ap(y) fprintf(codefile,".extern %s\n",y)
#define in_ap(y) /* nothing */
#define newilb(x) fprintf(codefile,"%s:\n",x)
#define newdlb(x) fprintf(codefile,"%s:\n",x)
#define dlbdlb(x,y) fprintf(codefile,"%s = %s\n",x,y)
#define newlbss(l,x) fprintf(codefile,".comm %s,%u\n",l,x);
#define cst_fmt "%d"
#define off_fmt "%d"
#define ilb_fmt "I%x_%x"
#define dlb_fmt "_%d"
#define hol_fmt "hol%d"
#define hol_off "%ld+hol%d"
#define con_cst(x) fprintf(codefile,".data4\t%ld\n",x)
#define con_ilb(x) fprintf(codefile,".data4\t%s\n",x)
#define con_dlb(x) fprintf(codefile,".data4\t%s\n",x)
#define fmt_id(sf, st) sprintf(st,"_%s",sf)
#define modhead ".sect .text; .sect .rom; .sect .data; .sect .bss\n"
#define BSS_INIT 0

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#
/*
* VideoCore IV assembler test file
* © 2013 David Given
* This file is redistributable under the terms of the 3-clause BSD license.
* See the file 'Copying' in the root of the distribution for the full text.
*/
.sect .text
.sect .rom
.sect .data
.sect .bss
.sect .text
main:
nop
rti
b r0
b r31
bl r0
bl r31
tbb r0
tbb r15
tbs r0
tbs r15
mov r0, r1
cmn r0, r1
add r0, r1
bic r0, r1
mul r0, r1
eor r0, r1
sub r0, r1
and r0, r1
mvn r0, r1
ror r0, r1
cmp r0, r1
rsb r0, r1
btst r0, r1
or r0, r1
extu r0, r1
max r0, r1
bset r0, r1
min r0, r1
bclr r0, r1
adds2 r0, r1
bchg r0, r1
adds4 r0, r1
adds8 r0, r1
adds16 r0, r1
exts r0, r1
neg r0, r1
lsr r0, r1
clz r0, r1
lsl r0, r1
brev r0, r1
asr r0, r1
abs r0, r1
mov r0, #31
cmn r0, #31
add r0, #31
bic r0, #31
mul r0, #31
eor r0, #31
sub r0, #31
and r0, #31
mvn r0, #31
ror r0, #31
cmp r0, #31
rsb r0, #31
btst r0, #31
or r0, #31
extu r0, #31
max r0, #31