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fixup commit for tag 'distr3'

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66
man/6500_as.1
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.\" $Header$
.TH 6500_AS 1ACK
.SH NAME
6500_as \- assembler for Mostek 6500
.SH SYNOPSIS
~em/lib/6500/as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6). It is an assembler-loader.
.SH "SECTIONS and TYPES"
An additional section, the \fIzeropage\fP, can be started by the
\&\fI.sect .zero\fP pseudo-instruction.
Some adressing-modes require an address between 0 and 255.
Such an address must be defined with the means of the \fI.sect .zero\fP
pseudo-instruction.
A plain number between 0 and 255 is not allowed.
The assembler will complain that it must be a zero page expression.
.IP example
\&.sect .zero
.br
answer: .space 1
.br
\&.text
.br
and (answer, x)
.SH SYNTAX
.IP expressions
An two-byte expression followed by the pseudo-operator \fI.h\fP (\fI.l\fP)
has the value of the higher (lower) byte of the expression.
\&\fI.h\fP and \fI.l\fP bind stronger than all other operators.
E.g. -1.h parses as -[1.h] which has value 0.
You have to write [-1].h to get 0xFF.
.IP "addressing modes"
.nf
.ta 16n 24n 32n 40n 48n
syntax meaning (name)
#expr 8-bit value (immediate)
expr address (direct)
expr, x expr + contents of x
or or
expr, y expr + contents of y
yields address (indexed)
(expr) address of address (only with JMP) (indirect)
.fi
In the next two addressing modes \fIexpr\fP has to be
a zeropage expression.
.nf
(expr, x) expr + contents of x
yields address (pre-indexed indirect)
(expr), y contents of expr + contents of y
yields address (post-indexed indirect)
.fi
.IP instructions
There are two mnemonics that do not map onto one machine-instruction:
\fIadd\fP and \fIsub\fP. \fIAdd mode\fP maps onto \fIclc; adc mode\fP.
\fISub mode\fP maps onto \fIsec; sbc mode\fP.
.SH "SEE ALSO"
uni_ass(6),
ack(1)

55
man/6800_as.1
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.\" $Header$
.TH 6800_AS 1
.ad
.SH NAME
6800_as \- assembler for Motorola 6800
.SH SYNOPSIS
/usr/em/lib/6800_as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6).
.SH SYNTAX
.IP registers
The 6800 has two accumulator registers, A and B. An instruction that refers
to accumulator A, has an "a" as last character. In the same way a "b" means
that the instruction uses B as accumulator.
.IP "addressing modes"
.nf
.ta 8n 16n 24n 32n 40n 48n
syntax meaning (name)
#expr with cpx, ldx, lds a 2-byte value,
otherwise a 1-byte value (immediate)
<expr 1-byte address. Not allowed with:
asl, asr, clr, com, dec, inc, lsl, lsr,
neg, rol, ror, tst (base page direct)
expr 2-byte address (extended direct)
expr, x 1-byte expr + contents of x
yields address (indexed)
.fi
.SH "SEE ALSO"
uni_ass(6),
ack(1),
.br
A. Osborne, 6800 programming for logic design,
Adam Osborne and Associates Inc., 1977
.SH EXAMPLE
An example of Motorola 6800 assembly code.
.sp 2
.nf
.ta 8n 16n 32n 40n 48n 56n 64n
.data
val: 0
.text
ldx <val
com val, x
bhs someplace ! branch on carry clear
sta <val
adda #18 ! add 18 to accumulator A
.fi
.SH BUGS
You have to specify whether an address fits in one byte
with the token \fI<\fP. It should be done automatically.

96
man/6805_as.1
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.\" $Header$
.TH 6805_AS 1
.ad
.SH NAME
6805_as \- assembler for Motorola 6805
.SH SYNOPSIS
/usr/em/lib/6805_as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6).
.SH SYNTAX
.IP registers
The 6805 has an accumulator register A and an index register X. An
instruction (from the read-modify-write group) that references the
A-register has an "a" suffixed to the mnemonic. In a similar way
the X-register, apart from indexing operations, is addressed with
an "x" suffix, i.e. "lsra" and "negx".
.IP "addressing modes"
The assembler automatically selects the shortest opcode if
appropriate and possible. Thus "sub 10" will use the direct
addressing mode whereas "neg 0,x" will use indexed (no offset) mode.
There are sick constructions where the assembler can't find out
the shortest form in time. In those cases the longest form is used.
.br
Branches are handled in much the same way. If a branch is out of
range it is replaced by a reversed condition branch, followed by
a jump, automatically.
.sp
.nf
.ta 8n 16n 24n 32n 40n 48n
syntax meaning (name)
#expr a one byte value (immediate)
<expr 1-byte zero page address. Allowed in
the register/memory and read-modify-
write instruction groups. (direct)
>expr 2-byte address. Allowed in the register
memory group. (extended)
expr 1-byte address if appropriate, 2-byte
in other cases. (auto-direct/extended)
,x indexed with zero offset. (indexed)
<expr,x indexed with 8 bit offset. (indexed-1)
>expr,x indexed with 16 bit offset. (indexed-2)
expr,x indexed with the shortest possible off-
set. (auto indexed)
bit,expr bit number and direct address.
(bit set/clear)
bit,expr,tag bit number, direct address and branch
tag. Automatically changed to reversed
condition branch and jump if appropri-
ate. (bit test and branch)
tag branch tag. Converted to reversed con-
dition branch and jump if appropriate.
(branch)
.fi
.IP "PSEUDO INSTRUCTIONS"
.dram use the zero page ram/io segment.
.dprom use the zero page (ep)rom segment.
.cmos assemble cmos version instructions.
.SH "SEE ALSO"
uni_ass(6),
ack(1),
.br
M6805 HMOS, M146805 CMOS family, Motorola,
Prentice-Hall, Inc., 1983, (ISBN 0-13-541375-3).
.SH EXAMPLE
An example of Motorola 6805 assembly code.
.sp 2
.nf
.ta 8n 16n 32n 40n 48n 56n 64n
.dram
one: .space 1 ! a-port
.dprom
c1: .byte 1
.text
start: ldx #c1 ! load address of c1
txa
sta one
add c1 ! add one
brset 1,one,whoop ! jif bit one of aport
bset 1,one ! set it now
.data
.ascii "unused string"
.text
whoop: nop
.org 0xff8
.word start ! set vector address
.text
nop ! resume code
.fi
.SH AUTHOR
Written by Gijs Mos.
Not a member of the ACK group.
.SH BUGS
The assembler has not been well tested.

147
man/6809_as.1
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.\" $Header$
.TH 6809_AS 1
.ad
.SH NAME
6809_as \- assembler for 6809
.SH SYNOPSIS
/usr/em/lib/6809_as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6).
.SH SYNTAX
.IP registers
The 6809 contains four 8-bit registers registers:
two accumulators (a and b),
a direct page register (dp),
and a condition code register (cc),
and five 16-bit registers:
two index registers (x and y),
a user an a hardware stack pointer (u resp. s),
and a program counter (pc).
The index registers and the stack pointers are indexable.
Accumulators a and b can be concatenated to form
the double accumulator d,
of which a is the high and b is the low byte.
An instruction that refers to accumulator a
has an "a" as last character.
In the same way a "b" means that the instruction
uses b as accumulator.
.IP "pseudo instructions"
The 6809 assembler recognizes one additional instruction
that is not translated into a machine instruction: setdp.
It expects an expression as argument.
This is used for efficient address encoding of some addressing
mode (see below).
.IP "addressing modes"
.nf
.ta 8n 16n 24n 32n 40n 48n
syntax meaning (name)
reg The operand of the instruction is in \fIreg\fP.
reglist \fIreglist\fP is a either list of registers, seperated
by ','s, or the word "all". It encodes in a register
save mask, where "all" means all registers, that can
be used by the push-pull instructions pshs, pshu,
puls, and pulu.
<expr The one-byte value of \fIexpr\fP is an address within
a 256-byte page. The particular page in use is
indicated by the contents of dp, so \fIexpr\fP is the
low byte of the effective address of the operand,
and dp the high byte. (direct)
>expr The two-byte value of \fIexpr\fP is the exact memory
address. Not that this mode always requires one
byte more than "<expr". (extended)
expr The value of \fIexpr\fP is an address.
Except for long branches, this value is examined
first to see if a short encoding is possible.
When the instruction is a short branch, the value
is checked to see if the address is not too remote,
because in that case this branch is automatically
replaced by a long branch. When the instruction is
not a branch, the high byte of the value is compared
with the value of the argument of the last setdp
pseudo. If they are equal, this mode is replaced by
"<expr", else by ">expr".
(relative for branch-instructions)
#expr The value of \fIexpr\fP is one- or two-byte immediate
data. (immediate)
(expr) The value of \fIexpr\fP is a pointer to the address
of the operand. (indirect)
expr, reg The value of \fIexpr\fP added to the contents of \fIreg\fP
(which must be a 16-bit register) yields the
effective address of the operand.
(constant-offset indexed)
, ireg The contents of \fIireg\fP (which must be indexable)
yields the effective address of the operand.
(constant-offset indexed)
(expr, reg) The value of \fIexpr\fP added to the contents of \fIreg\fP
(which must be a 16-bit register) yields a pointer
to the effective address of the operand.
(constant-offset indexed indirect)
(, ireg) The contents of \fIireg\fP (which must be indexable)
yields a pointer to the effective address of the
operand. (constant-offset indexed indirect)
ac, ireg The contents of \fIac\fP (which must be an accumulator)
added to the contents of \fIireg\fP (which must be
indexable) yields the effective address of the
operand. (accumulator indexed)
(ac, ireg) The contents of \fIac\fP (which must be an accumulator)
added to the contents of \fIireg\fP (which must be
indexable) yields a pointer to the effective address
of the operand. (accumulator indexed indirect)
,ireg+
,ireg++ The contents of \fIireg\fP (which must be indexable) is
used as effective address of the operand. After that
it is incremented by 1 (+) or 2 (++).
(auto-increment)
(,ireg++) The contents of \fIireg\fP (which must be indexable) is
used as a pointer to the effective address of the
operand. After that it is incremented by 2.
(auto-increment indirect)
,-ireg
,--ireg \fIireg\fP (which must be indexable) is decremented
by 1 (-) or 2 (--). After that, its contents is used
as effective address of the operand.
(auto-decrement)
(,--ireg) \fIireg\fP (which must be indexable) is decremented by 2.
After that, its contents is used as a pointer to the
effective address of the operand.
(auto-decrement indirect)
.fi
.SH "SEE ALSO"
uni_ass(6),
ack(1),
.br
MC6809 preliminary programming manual, Motorola Inc., First Edition, 1979
.SH EXAMPLE
An example of 6809 assembly code.
.nf
.ta 8n 16n 24n 32n 40n 48n
contby = 80
compgo: lda #contby
ldx #table - 2 !start of table
clrb
co1: addb #2
lsra
bcc co1
jmp (b, x) !accumulator offset indirect
.fi

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man/8080_as.1
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.\" $Header$
.TH 8080_AS 1
.ad
.SH NAME
8080_as \- assembler for Intel 8080 and 8085
.SH SYNOPSIS
/usr/em/lib/8080_as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6).
.SH SYNTAX
.IP registers
The 8080 has seven one-byte registers: a, b, c, d, e, h, l;
and two two-byte registers: sp and psw, respectively the stack pointer
and the processor status word.
.IP "addressing modes"
.nf
.ta 8n 16n 24n 32n 40n 48n
syntax meaning
expr one- or two-byte address or immediate
data, depending on the instruction.
a,b,c,d,e,h,l
sp,psw (lower byte) of register
b,d,h register-pair b-c, d-e, or h-l
m register-pair h-l is address of
(one or two byte) operand
.fi
.SH "SEE ALSO"
uni_ass(1),
ack(1),
.br
System 80/20-4 microcomputer hardware reference manual, 1978 Intel corporation

46
man/a.out.5
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.\" $Header$
.TH A.OUT 5
.SH NAME
a.out \- universal assembler load format
.SH DESCRIPTION
The load files produced by the universal assemblers look very
much alike.
These load files consist of sequences of variable length
records, each describing a part of the initialized memory.
Bss type memory is left uninitialized by the universal assembler
and has to be initialized at run-time.
The EM header em_head will perform this task on most systems.
Each record consists of a \fIcount\fP, an \fIaddress\fP and
\fIcount\fP bytes.
The first byte should be placed at \fIaddress\fP, the second at
\fIaddress+1\fP, etc.
.nf
struct loadf {
unsigned short l_addr[2] ; /* address */
short l_cnt ; /* count */
unsigned char data[] ; /* data */
} ;
.fi
This representation is machine dependent in two ways.
First, the byte order in the first three fields is the byte order
of the machine the universal assembler is running.
Second, the format of the address differs from machine to machine.
.br
For example, for the Intel 8086 the first entry contains a
16-bit offset and the second entry a segment number.
The segment number has to be multiplied by 16 and added to
the addres to obtain the address of the first byte to be
initialized.
.br
The PDP 11 version stores the address in l_addr[0] and the type
of the initialized memory in l_addr[1].
Types 1 and 3 are absolute, 4 is text, 5 is data and 6 BSS.
.br
For all other currently available machines the
array of shorts is 'replaced' by a long.
This long contains the 32-bit address.
.SH "SEE ALSO"
uni_ass(VI)
.SH BUGS

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man/arch.1
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.\" $Header$
.TH ARCH 1
.SH NAME
arch \- archive and library maintainer
.SH SYNOPSIS
.B arch
key [ posname ] afile name ...
.SH DESCRIPTION
.I Arch
maintains groups of files
combined into a single archive file.
Its main use
is to create and update library files as used by a linker.
It can be used, though, for any similar purpose.
The Amsterdam compiler kit provides its own archiver with a
fixed, machine-independent format, much like the UNIX-V7
archive format.
EM programs using libraries assume archives in EM format.
.PP
.I Key
is one character from the set
.B drqtpmx,
optionally concatenated with
one or more of
.B vuaibcl.
.I Afile
is the archive file.
The
.I names
are constituent files in the archive file.
The meanings of the
.I key
characters are:
.TP
.B d
Delete the named files from the archive file.
.TP
.B r
Replace the named files in the archive file.
If the optional character
.B u
is used with
.B r,
then only those files with
modified dates later than
the archive files are replaced.
If an optional positioning character from the set
.B abi
is used, then the
.I posname
argument must be present
and specifies that new files are to be placed
after
.RB ( a )
or before
.RB ( b
or
.BR i )
.IR posname .
Otherwise
new files are placed at the end.
.TP
.B q
Quickly append the named files to the end of the archive file.
Optional positioning characters are invalid.
The command does not check whether the added members
are already in the archive.
Useful only to avoid quadratic behavior when creating a large
archive piece-by-piece.
.TP
.B t
Print a table of contents of the archive file.
If no names are given, all files in the archive are tabled.
If names are given, only those files are tabled.
.TP
.B p
Print the named files in the archive.
.TP
.B m
Move the named files to the end of the archive.
If a positioning character is present,
then the
.I posname
argument must be present and,
as in
.B r,
specifies where the files are to be moved.
.TP
.B x
Extract the named files.
If no names are given, all files in the archive are
extracted.
In neither case does
.B x
alter the archive file.
.TP
.B v
Verbose.
Under the verbose option,
.I arch
gives a file-by-file
description of the making of a
new archive file from the old archive and the constituent files.
When used with
.B t,
it gives a long listing of all information about the files.
When used with
.BR p ,
it precedes each file with a name.
.TP
.B c
Create.
Normally
.I arch
will create
.I afile
when it needs to.
The create option suppresses the
normal message that is produced when
.I afile
is created.
.TP
.B l
Local.
Normally
.I arch
places its temporary files in the directory /tmp.
This option causes them to be placed in the local directory.
.SH FILES
/tmp/v* temporaries
.SH "SEE ALSO"
em_ass(I), arch(V),
.SH BUGS
If the same file is mentioned twice in an argument list,
it may be put in the archive twice.

52
man/arch.5
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.\" $Header$
.TH ARCH 5
.SH NAME
arch \- archive (library) file format
.SH SYNOPSIS
.B #include "/usr/em/h/arch.h"
.SH DESCRIPTION
The archive command
.I arch
is used to combine several files into
one.
Archives are used mainly as libraries to be searched
by the EM assembler/linker em_ass(VI) or the universal
assembler/linker em_unias(VI).
.PP
A file produced by
.I arch
has a magic number at the start,
followed by the constituent files, each preceded by a file header.
The magic number and header layout as described in the
include file are:
.RS
.PP
.nf
.ta \w'#define 'u +\w'ARMAG 'u
.so ../h/arch.h
.fi
.RE
.LP
The name is a null-terminated string;
The sizes of the other entries are determined as follows:
long's are 4 bytes in PDP-11 order, int are 2 bytes, low order
byte first, char's are 1 byte.
The date is in the
form of
.IR time (2);
the user ID and group ID are numbers; the mode is a bit pattern
per
.IR chmod (2);
the size is counted in bytes.
.PP
Each file begins on a even offset;
a null byte is inserted between files if necessary.
Nevertheless the size given reflects the
actual size of the file exclusive of padding.
.PP
Notice there is no provision for empty areas in an archive
file.
.SH "SEE ALSO"
arch(I), em_ass(VI), em_unias(VI)
.SH BUGS
Coding user and group IDs as characters is a botch.

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man/em.1
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.\" $Header$
.TH EM I
.ad
.SH NAME
em \- calling program for em interpreters
.SH SYNOPSIS
em [-t] [+fcp] [loadfile [args ... ...] ]
.SH DESCRIPTION
The loadfile ("e.out" if not specified) is opened to read the first 8 word header.
The format of this header is explained in e.out(V).
One of these 8 words is a flag word
specifying the interpreter options requested at compile time.
The usual setting of these options is +t -f -c -p.
One of these options may be overridden at run time
by the corresponding flag of em.
Based on these options the name of the appropriate interpreter
is constructed.
.PP
This interpreter is first searched for in /usr/em/mach/pdp/int, then in the current
directory.
.PP
The flags control the following options that can be turned off
or on by prepending them with - or + respectively:
.IP t
run time tests for undefined variables, array bounds etc...
This option costs a small amount of memory and some time.
However, it is very useful for debugging.
.IP p
profiling of the entire program. The interpreter maintain tables containing
an estimate of the number of memory cycles used per source line.
This option is expensive in time as well as in memory space.
The result tables made at run time are dumped onto a file named
em_runinf. This file is converted to human readable format
by the program eminform(I) which writes the profiling information
on a file called em_profile.
.IP f
maintain a bit map of all source lines that have been executed.
This map is written also onto the file em_runinf and can be interpreted by eminform(I) which writes in this case the file em_flow.
This option is almost free in time and space.
.IP c
count line usage in tables that
contains for every source line the number of times it
was entered.
These tables are also written onto em_runinf.
Eminform(I) can be used to convert this information into the
file em_count.
Cheap in time, expensive in memory space.
.PP
These flags
give rise to 5 different interpreters which are in the
directory /usr/em/mach/pdp/int
.PP
If the interpreter exits with a non-zero exit status, then the line numbers
of the 64 last executed source lines are dumped on the file
em_runinf
in the current directory. Eminform(I) writes this information
on the human readable file em_last.
.SH "FILES"
.IP /usr/em/mach/pdp/int/em_???? 35
interpreters proper
.PD 0
.IP /usr/em/lib/pdp_int/em_????
source of interpreter
.IP /usr/em/mach/pdp/int/?+
positive option switch
.IP /usr/em/mach/pdp/int/?-
negative option switch
.IP em_runinf
memory dump containing runtime information
.IP em_profile
profile data
.IP em_count
source line count data
.IP em_flow
source line flow data
.IP em_last
last lines executed
.PD
.SH "SEE ALSO"
eminform(I), ack(I), int(I)
.SH BUGS
Most error messages are self explanatory.
The interpreter stops in case of lack of space with an error
message SEGVIO stack overflow.
If runtime flags are turned on it is advisable to try again
with the default options.
Bugs should be reported to Evert Wattel.

40
man/em_decode.6
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.\" $Header$
.TH EM_DECODE VI
.ad
.SH NAME
em_decode,em_encode \- compact to readable EM and v.v.
.SH SYNOPSIS
/usr/em/lib/em_decode [ inputfile [ outputfile ] ]
.br
/usr/em/lib/em_encode [ inputfile [ outputfile ] ]
.SH DESCRIPTION
Most programs involved with the EM project only produce and accept
EM programs in compact form.
These files are only machine readable.
A description of this compact form can be found in [1].
To inspect the code produced by compilers or to patch them for one reason
or another, you need human readable assembly code.
Em_decode will do the job for you.
.PP
Em_decode accepts the normal compact form in both optimized and
unoptimized form
.PP
Sometimes you have to make some special routines directly
in EM, for instance the routines implementing the system calls.
At these times you may use em_encode to produce compact routines
out of these human readable assembly modules.
.PP
The first argument is the input file.
The second argument is the output file.
Both programs can act as a filter.
.SH "SEE ALSO"
.IP [1]
A.S.Tanenbaum, Ed Keizer, Hans van Staveren & J.W.Stevenson
"Description of a machine architecture for use of
block structured languages" Informatica rapport IR-81.
.IP [2]
ack(I)
.SH DIAGNOSTICS
Error messages are intended to be self-explanatory.
.SH AUTHOR
Johan Stevenson, Vrije Universiteit.

51
man/eminform.1
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.\" $Header$
.tr ~
.TH EMINFORM I
.ad
.SH NAME
eminform \- converts runtime information of interpreted em to
human readable form.
.SH SYNOPSIS
eminform
.SH DESCRIPTION
The EM interpreter, em(I), has several debugging features built in.
They can be activated by flag options to em(I).
The EM interpreter collects the information while it runs the program.
When the program is terminated, the interpreter dumps this information onto
a file called em_runinf.
Eminform converts this information in human readable form onto
a set of files with fixed names, the file em_runinf itself is unlinked.
.PP
.in +15
.ti -13
~~em_last~~~~A circular buffer is used to keep track of
the last collection of executed source lines.
.ti -13
~~em_flow~~~~A bit map for all source lines tells which lines
are executed.
.ti -13
~~em_count~~~Count the number of times each source line was entered.
.ti -13
~~em_profile~Estimate the number of memory cycles
spent on each source line.
.in -15
.LP
The most common use of eminform is to print the numbers of the last executed
source lines if an execution error occurred.
No arguments are needed in this case.
.LP
Eminform will create only those files for which there were
interpreter flags turned on. If no runtime error occurred and
no flag was turned on the file em_runinf is not created. In
this case eminform will give the error message "read header
failed".
.SH FILES
em_runinf, em_last, em_flow, em_count, em_profile
.SH "SEE ALSO"
ack(I), int(I), em(I).
.SH BUGS
If an entire procedure is not touched, the the file name in
which this procedure occured is unknown.
If no em_runinf is available the error message is "read header
failed" and a core dump is created.
Bugs should be reported to Evert Wattel

145
man/i86_as.1
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.\" $Header$
.TH I86_AS 1
.ad
.SH NAME
i86_as \- assembler for Intel 8086
.SH SYNOPSIS
/usr/em/lib/i86_as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6).
.SH SYNTAX
.IP segments
An address on the Intel 8086 consists of two pieces:
a segment number and an offset. A memory address is computed as
the segment number shifted left 4 bits + the offset.
Assembly language addresses only give the offset, with the exception of
the address of an inter-segment jump or call (see \fIaddressing modes\fP
below).
For each segment type (.org, .text, .data, or .bss) the segment number
must be given with the .sbase pseudo-instruction.
The syntax is:
.br
.sbase <segment-id> expression
.br
with segment-id one of .org, .text, .data, or .bss.
Example:
.br
.sbase .text 0x1000
.IP registers
The Intel 8086 has the following 16-bit registers:
.br
Four general registers: ax (accumulator), bx (base), cx (count), and dx (data).
The upper halves and lower halves of these registers are separately
addressable as ah, bh, ch, dh, and al, bl, cl, dl respectively.
.br
Two pointer registers: sp (stack pointer) and bp (base pointer).
.br
Two index registers: si (source index) and di (destination index).
.br
Four segment registers: cs (code), ds (data), ss (stack), and es (extra).
.IP "addressing modes"
.nf
.ta 8n 16n 24n 32n 40n 48n
syntax meaning
expr the value of \fIexpr\fP is immediate data or
an address offset. There is no special
notation for immediate data.
register one of the aforementioned general registers
or their upper or lower halves, or one of the
four segment registers.
(expr) the value of expr is the address of the operand.
(reg)
expr (reg) the value of \fIexpr\fP (if present) + the contents of
\fIreg\fP (which must be a pointer or an index register)
is the address of the operand.
(preg) (ireg)
expr (preg) (ireg)
the value of \fIexpr\fP (if present) + the contents of
\fIpreg\fP (which must be a pointer register) + the
contents of \fIireg\fP (which must be an index register)
is the address of the operand.
The next addressing mode is only allowed with the instructions
"callf" or "jmpf".
expr : expr the value of the first \fIexpr\fP is a segment number,
the value of the second \fIexpr\fP is an address offset.
The (absolute) address of the operand is computed
as described above.
.fi
.IP instructions
Each time an address is computed the assembler decide which segment register
to use. You can override the assembler's choice by prefixing the instruction
with one of eseg, cseg, sseg, or dseg; these prefixes indicate that the
assembler should choose es, cs, ss, or ds instead.
.br
Example:
.ti +8
dseg movs
.SH "SEE ALSO"
uni_ass(6),
ack(1),
.br
MCS-86 assembly language reference manual, 1978, Intel Corporation
.SH EXAMPLE
.nf
.ta 8n 16n 24n 32n 40n 48n
An example of Intel 8086 assembly language:
_panic:
push bp
mov bp,sp
.data
_35:
.word 24944
.word 26990
.word 14947
.word 32
.text
call _disable
mov ax,_35
push ax
call _str
pop si
push 4(bp)
call _str
pop si
call _nlcr
call _exit
mov sp,bp
pop bp
ret
.extern _nopanic
_nopanic:
push bp
mov bp,sp
.data
_38:
.word 28526
.word 24944
.word 26990
.word 14947
.word 32
.text
mov ax,_38
push ax
call _str
pop si
push 4(bp)
call _str
pop si
push 6(bp)
call _octal
pop si
mov sp,bp
pop bp
ret
.fi

100
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.\" $Header$
.TH M68K2_AS 1
.ad
.SH NAME
m68k2_as \- assembler for Motorola 68000
.SH SYNOPSIS
/usr/em/lib/m68k2_as [options] argument ...
.br
/usr/em/lib/m68k4_as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6).
.SH SYNTAX
.IP registers
The 68000 has the following registers:
seven data-registers (d1 - d7), seven address-registers (a1 - a6, sp)
of which sp is the system stack pointer, a program counter (pc),
a status register (sr), and a condition codes register (ccr) which is actually
just the low order byte of the status register.
.IP "addressing modes"
.nf
.ta 8n 16n 24n 32n 40n 48n
syntax meaning (name)
reg contents of \fIreg\fP is operand, where \fIreg\fP is
one of the registers mentioned above (register direct)
(areg) contents of \fIareg\fP is address of operand, where
\fIareg\fP is an address-register
(address register indirect)
(areg)+ same as (areg), but after the address is used,
\fIareg\fP is incremented by the operand length
(postincrement)
-(areg) same as (areg), but before the address is used,
\fIareg\fP is decremented by the operand length
(predecrement)
expr(areg)
expr(pc) \fIexpr\fP + the contents of the register yields the
address of the operand (displacement)
expr(areg, ireg)
expr(pc, ireg) \fIexpr\fP + the contents of the register + the contents
of \fIireg\fP yields the address of the operand. \fIireg\fP is
an address- or a data-register.
\fIireg\fP may be followed by .w or .l indicating whether
the size of the index is a word or a long
(displacement with index)
expr \fIexpr\fP is the address of the operand
(absolute address)
#expr \fIexpr\fP is the operand (immediate)
.fi
Some instructions have as operand a register list. This list consists of
one or more ranges of registers separated by '/'s. A register range consists
of either one register (e.g. d3) or two registers separated by a '-'
(e.g. a2-a4, or d4-d5). The two registers must be in the same set (address-
or data-registers) and the first must have a lower number than the second.
.IP instructions
Some instructions can have a byte, word, or longword operand.
This may be indicated by prepending the mnemonic with .b, .w, or .l
respectively. Default is .w.
.SH "SEE ALSO"
uni_ass(6),
ack(1),
.br
MC68000 16-bit microprocessor User's manual, Motorola Inc, 1979
.SH EXAMPLE
.sp 2
.nf
.ta 8n 16n 24n 32n 40n 48n 56n 64n
.define .cii
.text
.cii:
movem.l a0/d0/d1,.savreg
move.l (sp)+,a0 ! return address
move (sp)+,d0 ! destination size
sub (sp)+,d0 ! destination - source size
bgt 1f
sub d0,sp ! pop extra bytes
bra 3f
1:
move (sp),d1
ext.l d1
swap d1
asr #1,d0
2:
move.w d1,-(sp)
sub #1,d0
bgt 2b
3:
move.l a0,-(sp)
movem.l .savreg,a0/d0/d1
rts
.fi

96
man/m68k_int.1
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.\" $Header$
.TH EM I
.ad
.SH NAME
em \- calling program for em interpreters
.SH SYNOPSIS
em [-t] [+fcp] [loadfile [args ... ...] ]
.SH DESCRIPTION
The loadfile ("e.out" if not specified) is opened to read the first 8 word header.
The format of this header is explained in e.out(V).
One of these 8 words is a flag word
specifying the interpreter options requested at compile time.
The usual setting of these options is +t -f -c -p.
These options may be overridden at runtime as follows:
em -t turns the test option of; em +c turns count on ; em +p turns profile
on ; em +c +p turns both count and profile on.
Based on these options the name of the appropriate interpreter
is constructed.
Two versions exist, one for two byte words and four byte pointers and
one for four byte words and pointers.
The information in the header of the e.out file is used by em to select the
right interpreter for the word size of used in the e.out file.
.PP
This interpreter is searched for in /usr/em/lib/int[24]4.
.PP
The flags control the following options that can be turned off
or on by prepending them with - or + respectively:
.IP t
run time tests for undefined variables, array bounds etc...
This option costs a small amount of memory and some time.
However, it is very useful for debugging.
.IP p
profiling of the entire program. The interpreter maintains tables containing
an estimate of the number of processor state cycles used per source line.
A processor state cycle is equal to two internal clock cycles.
This option is expensive in time as well as in memory space.
The result tables made at run time are dumped in a human readable
format onto a file named
em_profile.
.IP f
maintain a bit map of all source lines that have been executed.
This map is written onto a file em_flow .
This option is almost free in time and space.
The file is not easy to read.
Of each procedure only the lines between the first statement and the last
statement are represented in the bit map.
Currently this option is not installed in the em tree.
.IP c
count line usage in tables that
contains for every source line the number of times it
was entered.
These tables are written onto em_count, a human readable file .
This option is cheap in time, but costs some in memory space.
.IP l
dump the line numbers of the last 64 lines entered onto a file named
em_last.
This file will be in a human readable format.
This option is used simultaneously with the test option.
.PP
These flags
give rise to 5 different interpreters which are in the
directory /usr/em/lib/int24 or in /usr/em/lib/int44
for the two byte word or the four byte word options, respectively.
.PP
.SH "FILES"
.IP /usr/em/lib/int[24]4/em_???? 35
interpreters proper
.PD 0
.IP /usr/em/mach/m68k2/int/mloop?
source of interpreter
.IP em_profile
profile data
.IP em_count
source line count data
.IP em_flow
source line flow data
.IP em_last
last lines executed
.PD
.SH "SEE ALSO"
\fIack\fP(I),
\fIint24\fP(I),
\fIint44\fP(I)
.SH BUGS
Most error messages are self explanatory.
If runtime flags are turned on it is advisable to try again
with the default options.
If the interpreter does not work most probably your particular
machine has an other format for the system calls then assumed
in the source.
In that case adapt source file mloopc to your machine.
Also the instruction that causes the machine to allocate stack
space might differ .
In that case adapt the macro \fIclaimstack\fP in deffile.
.SH AUTHOR
Freek van Schagen

66
man/macro.v7
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@@ -1,66 +0,0 @@
.\" $Header$
.de TH
.PD
.br
.bp
.lc
.nr in 5
.de hd
'sp 2
'tl '\\$1(\\$2)'Amsterdam Compiler Kit'\\$1(\\$2)'
'sp 2
\\..
.wh -6 fo
.wh 0 hd
.nr pi 5
..
.de fo
'sp 2
'tl ''- % -''
'bp
..
.de PD
.nr pd 0.5v
.if \\n(.$ .nr pd \\$1
..
.de SH
.nr in 5
.nr pi 5
.in \\n(in
.ti 0
.sp \\n(pdu
.ne 2
.fi
\fB\\$1\fP
.br
..
.de LP
.PP
..
.de PP
.sp \\n(pdu
.ne 2
.in \\n(in
.nr pi 5
.ns
..
.de IP
.if \\n(.$-1 .nr pi \\$2
.sp \\n(pdu
.in \\n(in+\\n(pi
.ta \\n(in \\n(in+\\n(pi
.ti 0
\fB\\$1\fR\c
.if \w'\fB\\$1\fP'-\\n(pin+1n .br
..
.de RS
.nr in +5
.in +5
..
.de RE
.in -5
.nr in -5
..
.de RF
\fI\\$1\fP(\\$2)\\$3
..

148
man/ns_as.1
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.TH NS_ASS VI
.ad
.SH NAME
ns_as \- National Semiconductor 16032 assembler/linker
.SH SYNOPSIS
\&..../lib/ns/as [options] argument ...
.SH DESCRIPTION
The assembler for the National Semiconductor 16032 is based
on the universal assembler \fIuni_ass\fP(VI).
The mnemonics for the instructions are taken from the NS-16000
Programmers Reference Manual.
The syntax of the instruction operands is similar to the syntax used
in that manual,
although the meaning is sometimes quite different.
The cross assembler issued by National Semiconductor
associates a type (sb,..) with each symbol
and automatically generates sb offset mode for symbols of type sb.
This assembler does not record the types,
each symbol simply produces an untyped value.
.sp 1
The possible operands are:
.IP "general registers
These are called r0, r1, r2, r3, r4, r5, r6 and r7.
The symbol REG is used to indicate use of any of these 8 registers
in other operands.
.IP "floating point registers
These are called f0, f1, f2, f3, f4, f5, f6 and f7.
.IP "dedicated registers
All types of dedicated registers can be used with the appropriate instructions.
Examples: sb, fp, intbase, ptb1.
.IP expr(REG)
register relative
.IP expr(fp)
frame pointer relative
.IP expr(sb)
static base relative
.IP expr(sp)
stack pointer relative
.IP expr(pc)
program counter relative,
the expression indicates a location in memory from which the current value
of '.' is subtracted by the assembler.
E.g. "movw label(pc),r0; label: .word ..." moves the contents of the word
at \fIlabel\fP to r0.
.IP expr(expr(fb))
.IP expr(expr(sb))
.IP expr(expr(sp))
memory relative
.IP @expr
absolute
.IP external(expr)+expr
The external mode is provided, although this assembler
does not build a module table.
.IP tos
top of stack.
.PD 0
.sp 1
.PP
Usage of the scaled index operands is allowed.
.br
The convention used to indicate offset length by appending :B, :W or :D
to offsets is not implemented.
The assembler tries to find out the minimal size needed for any constant
in an operand of the instruction placed in the text segment.
Offsets in instructions outside \fI.text\fP are always four bytes.
.PP
All special operands, e.g. register list, configuration list, have
the same format as in the Programmers Reference Manual.
.PP
Whenever possible the assembler automatically uses the short(quick) opcodes for
jsr(jsb), jump(br), add(addq), cmp(cmpq) and mov(movq).
.SH BUGS
The data types floating and packed-decimal are not supported.
.br
Initialization of floating-point numbers is not possible.
.br
The mnemonics of the slave processor instructions are poorly documented,
the format of the NS-16032S-6 data sheet is used.
.br
The documentation gave contradictory information on the format
of a few instructions.
.IP -
Three different schemes are presented for the encoding
of the last operand of the block instructions.
.IP -
Two different values are specified for
the encoding of the msr register in smr and lmr instructions.
.IP -
Two different possibilities are given for the encoding of
the instructions movsu and movus.
.SH EXAMPLE
.nf
.ta 12n 20n 28n 36n
00000000 0E0B02 setcfg [ m ]
label:
00000003 EC3E lprb psr,r7
00000005 2D37 sprw intbase,r6
00000007 EA7C br label
00000009 02803B bsr rout1
0000000C 228044 cxp rout1
0000000F 1204 ret 4
00000011 4204 rett 4
00000013 328044 rxp rout1
00000016 1E0300 rdval r0
00000019 163028 scsr r5
0000001C 3F32 shid r6
0000001E 7F0B bispsrd r1
00000020 7C17 caseb r2
00000022 7FA806 cxpd @6
00000025 021F jsr @rout1
00000027 BEB529 absf f5,f6
0000002A EE0538 movusw r7,r0
0000002D 3E40A101 movbl 1,f5
00000031 CE440003 cmpmb r0,r1,4
00000035 CE4F0800 extsd r1,r1,0,1
00000039 62A0 save [ r5, r7 ]
0000003B 1E0B00 lmr bpr0,r0
0000003E 0E8C04 skpst w
00000041 CC0042 acbb 1,r0,label
00000044 B2 rout1: wait
00000045 7F950C0B adjspd 11(12(sb))
00000049 7CA50D adjspb 13
0000004C 7DB50102 adjspw external(1)+2
00000050 7FBD adjspd tos
00000052 7CED860807 adjspb 7(8(fp))[r6:w]
.fi
.SH "SEE ALSO"
uni_ass(VI)
.br
NS 16000 Programmers Reference Manual. Publ. no. 420306565-001PB
.br
NS16032S-6, NS16032S-4 High Performance Microprocessors, november 1982
.br
publ. no. 420306619-002A.
.PD 0
.SH AUTHOR
Ed Keizer, Vrije Universiteit

138
man/pdp_as.1
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.\" $Header$
.TH PDP_AS 1
.ad
.SH NAME
pdp_as \- assembler for PDP 11
.SH SYNOPSIS
/usr/em/lib/pdp_as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6).
.SH SYNTAX
.IP registers
The pdp11 has seven general registers, numbered r0 through r7.
Of these, r6 is the stack pointer and can also be referenced to by \fIsp\fP,
r7 is the program counter and has \fIpc\fP as synonym. There are also six
floating-point registers fr0 through fr5, but the names r0 through r5 can
also be used. From the context will be derived what kind of register is meant.
.IP "addressing modes"
.nf
.ta 8n 16n 24n 32n 40n 48n
syntax meaning (name)
reg contents of register reg is operand.
(register)
(reg) contents of reg is address of operand.
(register deferred)
(reg)+ as (reg), but after the operand is fetched
the contents of reg is incremented by the
size of the operand. (auto-increment)
*(reg)+ contents of reg points to address of the operand.
after the operand is fetched, reg is incremented
by two. (auto-increment deferred)
-(reg) as (reg), but before the operand is fetched
the contents of reg is decremented by the
size of the operand. (auto-decrement)
*-(reg) before the operand is fetched, reg is decremented
by two. then the contents of reg points to the
address of the operand. (auto-decrement deferred)
expr(reg) value of expr + contents of reg yields address
of operand. (index)
*expr(reg) value of expr + contents of reg yields pointer
to address of operand. (index deferred)
$expr the value of expr is the operand. (immediate)
*$expr the value of expr is the address of the operand.
(absolute)
expr expr is address of operand. (relative)
*expr expr points to the address of the operand.
(relative deferred)
.fi
.IP "condition code instructions"
Two or more of the "clear" instructions (clc, cln, clv, clz), or
two or more of the "set" instructions (sec, sen, sev, sez) may be
or-ed together with `|' to yield a instruction that clears or sets two or more
of the condition-bits. Scc and ccc are not predefined.
.IP "extended branches"
The assembler recognizes conditional branches with a "j" substituted for
the "b". When the target is too remote for a simple branch, a converse branch
over a jmp to the target is generated. Likewise jbr assembles into either br
or jmp.
.IP "floating-point instructions"
The names of several floating-point instructions differ from the names
in the handbook mentioned below. Synonyms ending in "d" for instructions ending
in "f" are not recognized. Some instructions have different names; the mapping
is as below.
.nf
.ta 8n 16n 24n 32n 40n 48n
handbook pdp_as
ldcif, ldclf,
ldcid, ldcld movif
stcfi, stcfl,
stcdi, stcdl movfi
ldcdf, ldcfd movof
stcdf, stcfd movfo
ldexp movie
stexp movei
ldd, ldf movf
std, stf movf
.fi
The movf instruction assembles into stf, when the first operand is one of the
first three floating-point registers, otherwise it assembles into ldf.
.IP sys
This instruction is synonymous with trap.
.SH EXAMPLE
An example of pdp11 assembly code.
.nf
.ta 8n 16n 24n 32n 40n 48n
!this is the routine that reads numbers into r0
!the number is terminated by any non digit
!the non digit is left in r1
innum: clr r3 !r3 will accumulate the number
inloop: jsr pc,_getchar !read a character into r0
cmp r0,$0121 !is it a Q?
jeq quit
cmp r0,$48 !is the character a digit?
jlt indone !digits 0-9 have codes 060-071 octal
cmp r0,$56
jgt indone
mul $10,r3 !r3 = 10 * r3
sub $48,r3 !convert ascii code to numerical value
add r0,r3 !r3 = old sum * 10 + new digi
jbr inloop
indone: mov r0,r1 !put the first non digit into r1
mov r3,r0 !put the number read into r0
rts pc !return to caller
.fi
.SH "SEE ALSO"
uni_ass(6),
ack(1),
.br
PDP11/60 processor handbook, Digital Equipment Corporation, 1977
.SH BUGS
You cannot use *reg in place of (reg). Likewise *(reg) is not understood as
*0(reg).

163
man/z8000_as.1
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.TH Z8000_AS 1
.ad
.SH NAME
z8000_as \- assembler for Zilog z8000 (segmented version)
.SH SYNOPSIS
/usr/em/lib/z8000_as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6).
.SH SYNTAX
.IP instructions
Instruction mnemonics are implemented exactly as described in
\fIZ8000 PLZ/ASM Assembly Language Programming Manual\fP and
\fIAmZ8001/2 Processor Instruction Set\fP.
.IP registers
The z8000 has sixteen 16-bit general purpose registers specified
as R0 through R15. All sixteen registers can be used as accumulators.
In addition to this, fifteen of the sixteen registers may be used
in addressing mode calculations as either indirect, index or
base-address registers. Because the instruction format encoding
uses the value zero to differentiate between various addressing
modes, register R0 (or the register pair RR0) cannot be used as an
indirect, index or base-address register.
It is also possible to address registers as groups of 8, 32 or 64 bits.
These registers are specified as follows.
.nf
.ta 8n 16n 24n 32n 40n 48n
- RH0, RL0, RH1, RL1, ..., RH7, RL7 for 8-bit regis-
ters. (\fIH\fP stands for high-order byte, and \fIL\fP stands
for low-order byte within a word register). These
registers overlap 16-bit registers R0 through R7.
- RR0, RR2, ..., RR14 for 32-bit register pairs.
- RQ0, RQ4, RQ8 and RQ12 for 64-bit register quadruples.
.fi
Besides register pair RR14 is used as stackpointer.
.IP "addressing modes"
.nf
.ta 8n 16n 24n 32n 40n 48n
syntax meaning (name-mnemonic)
$expr the value of expr is the operand.
(immediate-IM)
reg contents of register reg is operand. Any
register as described above is allowed.
(register-R)
*reg32 contents of register pair reg32 is add-
ress of operand. Any register pair can
be used except RR0.
(indirect register-IR)
expr expr is address of operand.
(direct address-DA)
expr(reg16) value of expr + contents of word regis-
ter reg16 yields address of operand.
Any word register can be used except R0.
(indexed address-X)
expr expr is address of operand. This mode
is implied by its instruction. It is
only used by CALR, DJNZ, JR, LDAR and
LDR and is the only mode available to
these instructions. In fact this mode
differs not from the mode DA.
(relative address-RA)
reg32($expr) contents of register pair reg32 + value
of expr yields address of operand. Any
register pair can be used except RR0.
(based address-BA)
reg32(reg16) contents of register pair reg32 + con-
tents of word register reg16 yields
address of operand. Any register pair/
word register can be used except RR0/R0.
(based indexed address-BX)
.fi
.IP "segmented addresses"
Segmented addresses require 23 bits, 7 bits for the segment number
and 16 bits for the offset within a segment.
So segment 0 contains addresses 0-FFFF, segment 1 contains addresses
10000-1FFFF, and so on.
.br
Assembler syntax of addresses and immediate data is as described above
(modes IM, DA and X).
Thus the assembler treats e.g. address 2BC0F as an address in segment 2
with offset BC0F within the segment.
There is also an explicit way to express this using the, more unusual,
syntax <<segment>>offset.
.br
There are two internal representations of segmented addresses
depending on the size of the offset. If the offset fits into 8 bits
the address is stored in one word (the low-order byte containing
the offset, bits 8 to 14 containing the segment number and
bit 15 containing a zero) otherwise the address is stored in two
words (the lower word containing the offset, the upper word as
before but bit 15 containing 1 indicating that the offset is in
the next word).
This is important for instructions which has an operand of mode DA
or X.
.IP "extended branches"
When the target address in a relative jump/call (JR/CALR)
does not fit into the instruction format, the assembler generates
a corresponding `normal' jump/call (JP/CALL).
.SH EXAMPLE
An example of z8000 assembly code.
.nf
.ta 8n 16n 24n 32n 40n 48n
! This z8000 assembly routine converts a positive number
!(in R1) to a string representing the number and puts this
!string into a buffer (R3 contains the starting address of
!this buffer. The base is in R4 determining %x, %d or %o.
convert:
exts RR0 !sign-extend R1
div RR0, R4 !divide by the base
test R1 !R1 contains the quotient
jr EQ, 5f
!if quotient is 0 convert is ready
!else push remainder onto the stack
push *RR14, R0
calr convert !and again...
pop R0, *RR14
5: add R0, $060 !add `0'
cp R0, $071 !compare to `9'
jr LE, 8f
add R0, $7 !in case of %x `A'-`F'
8: ldb 0(R3), RL0 !put character into buffer
inc R3
ret
.fi
.SH "SEE ALSO"
uni_ass(6).
.br
ack(1).
.br
Z8000 PLZ/ASM Assembly Language Programming Manual, april 1979.
.br
AmZ8001/2 Processor Instruction Set, 1979.
.SH BUGS
You cannot use (reg16) instead of 0(reg16).
.br
Condition codes \fIZ\fP (meaning zero), \fIC\fP (meaning carry) and <nothing>
(meaning always false) are not implemented.
The first two because they also represent flags and the third one
because it's useless.
So for \fIZ\fP/\fIC\fP use \fIEQ\fP/\fIULT\fP.
.br
The z8000 assembly instruction set as described in the book
\fIAmZ8001/2 Processor Instruction Set\fP differs from the one
described in the manual \fIZ8000 PLZ/ASM Assembly Language Programming
Manual\fP in that the book includes CLRL, LDL (format F5.1) and
PUSHL (format F5.1) which all in fact do not (!) work.
.br
On the other side the book excludes SIN, SIND, SINDR, SINI, SINIR,
SOUT, SOUTD, SOTDR, SOUTI and SOTIR.
Whether these instructions do work as described in the manual has not
been tested yet.

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man/z80_as.1
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.\" $Header$
.TH z80_AS 1
.ad
.SH NAME
z80_as \- assembler for Zilog z80
.SH SYNOPSIS
/usr/em/lib/z80_as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6).
.SH SYNTAX
.IP registers
The z80 has six general-purpose 8-bit registers: b, c, d, e, h, l;
an 8-bit accumulator: a; an 8-bit flag register: f; an 8-bit interrupt
vector: i; an 8-bit memory refresh register: r; two 16-bit index registers:
ix, iy; a 16-bit stack pointer: sp; and a 16-bit program counter: pc.
The general-purpose registers can be paired to form three registers pairs of
16 bits each: bc, de, hl.
An alternate set of registers is provided that duplicates the accumulator,
the flag register, and the general-purpose registers. The "exx"-instruction
exchanges the contents of the two sets of general-purpose registers; the
contents of the accumulator and flag register can be exchanged with the contents
of their alternates by the "ex af, af2"-instruction.
.IP "addressing modes"
.nf
.ta 8n 16n 24n 32n 40n 48n
syntax meaning
expr dependent on the instruction, the
value of \fIexpr\fP can be immediate
data or the address of the operand.
There is no special notation for
immediate data.
(ireg + expr)
(ireg - expr) the contents of ireg (which must be
one of the index-registers) + or -
the - one byte - value of \fIexpr\fP
yield the address of the operand.
(expr) the value of \fIexpr\fP is the address of
the operand.
reg the contents of \fIreg\fP - one of the above-
mentioned registers - is the operand.
(reg) the contents of \fIreg\fP - one of the 16-bit
registers except pc - is the address of
the operand.
nz, z, nc, c,
po, pe, p, m the letters indicate a condition-code:
nonzero, zero, carry, no carry,
parity odd, parity even, sign positive,
sign negative respectively. Used by conditional
jump, call, and return instructions.
.fi
.IP instructions
The jr-instruction will automatically be replaced by a jp-instruction if the
target is too remote.
.SH "SEE ALSO"
uni_ass(6),
ack(1),
.br
Z80 Users Manual, Joseph J. Carr, Reston Publishing Company, 1980