Update i86 as part.
This commit is contained in:
Godzil
Manoël Trapier
parent
d627b11b98
commit
595e5258aa
@ -20,6 +20,21 @@ extern expr_t exp_1,exp_2;
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extern int rel_1, rel_2;
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extern int rel_1, rel_2;
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#endif
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#endif
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void branch(int opc, expr_t exp);
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void pushop(int opc);
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void addop(int opc);
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void incop(int opc);
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void rolop(int opc);
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void imul(int opc);
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void regsize(int sz);
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void ea_1(int param);
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void ea_2(int param);
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void callop(int opc);
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void xchg(int opc);
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void test(int opc);
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void mov(int opc);
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void indexed();
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#ifndef extern
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#ifndef extern
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extern char sr_m[8];
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extern char sr_m[8];
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#else
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#else
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@ -32,13 +47,13 @@ char sr_m[8] = {
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extern char dr_m[8][8];
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extern char dr_m[8][8];
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#else
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#else
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char dr_m[8][8] = {
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char dr_m[8][8] = {
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-1, -1, -1, -1, -1, -1, -1, -1,
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{ -1, -1, -1, -1, -1, -1, -1, -1 },
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-1, -1, -1, -1, -1, -1, -1, -1,
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{ -1, -1, -1, -1, -1, -1, -1, -1 },
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-1, -1, -1, -1, -1, -1, -1, -1,
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{ -1, -1, -1, -1, -1, -1, -1, -1 },
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-1, -1, -1, -1, -1, -1, 0, 1,
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{ -1, -1, -1, -1, -1, -1, 0, 1 },
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-1, -1, -1, -1, -1, -1, -1, -1,
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{ -1, -1, -1, -1, -1, -1, -1, -1 },
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-1, -1, -1, -1, -1, -1, 2, 3,
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{ -1, -1, -1, -1, -1, -1, 2, 3 },
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-1, -1, -1, -1, -1, -1, -1, -1,
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{ -1, -1, -1, -1, -1, -1, -1, -1 },
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-1, -1, -1, -1, -1, -1, -1, -1
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{ -1, -1, -1, -1, -1, -1, -1, -1 }
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};
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};
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#endif
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#endif
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@ -8,330 +8,330 @@
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* INTEL 8086 keywords
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* INTEL 8086 keywords
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*/
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*/
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0, R16, 0, "ax",
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{ 0, R16, 0, "ax" },
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0, R16, 1, "cx",
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{ 0, R16, 1, "cx" },
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0, R16, 2, "dx",
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{ 0, R16, 2, "dx" },
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0, R16, 3, "bx",
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{ 0, R16, 3, "bx" },
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0, R16, 4, "sp",
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{ 0, R16, 4, "sp" },
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0, R16, 5, "bp",
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{ 0, R16, 5, "bp" },
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0, R16, 6, "si",
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{ 0, R16, 6, "si" },
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0, R16, 7, "di",
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{ 0, R16, 7, "di" },
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0, R8, 0, "al",
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{ 0, R8, 0, "al" },
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0, R8, 1, "cl",
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{ 0, R8, 1, "cl" },
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0, R8, 2, "dl",
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{ 0, R8, 2, "dl" },
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0, R8, 3, "bl",
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{ 0, R8, 3, "bl" },
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0, R8, 4, "ah",
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{ 0, R8, 4, "ah" },
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0, R8, 5, "ch",
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{ 0, R8, 5, "ch" },
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0, R8, 6, "dh",
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{ 0, R8, 6, "dh" },
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0, R8, 7, "bh",
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{ 0, R8, 7, "bh" },
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0, RSEG, 0, "es",
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{ 0, RSEG, 0, "es" },
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0, RSEG, 1, "cs",
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{ 0, RSEG, 1, "cs" },
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0, RSEG, 2, "ss",
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{ 0, RSEG, 2, "ss" },
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0, RSEG, 3, "ds",
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{ 0, RSEG, 3, "ds" },
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0, PREFIX, 046, "eseg",
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{ 0, PREFIX, 046, "eseg" },
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0, PREFIX, 056, "cseg",
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{ 0, PREFIX, 056, "cseg" },
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0, PREFIX, 066, "sseg",
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{ 0, PREFIX, 066, "sseg" },
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0, PREFIX, 076, "dseg",
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{ 0, PREFIX, 076, "dseg" },
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0, PREFIX, 0360, "lock",
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{ 0, PREFIX, 0360, "lock" },
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0, PREFIX, 0363, "rep",
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{ 0, PREFIX, 0363, "rep" },
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0, PREFIX, 0362, "repne",
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{ 0, PREFIX, 0362, "repne" },
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0, PREFIX, 0362, "repnz",
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{ 0, PREFIX, 0362, "repnz" },
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0, PREFIX, 0363, "repe",
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{ 0, PREFIX, 0363, "repe" },
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0, PREFIX, 0363, "repz",
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{ 0, PREFIX, 0363, "repz" },
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0, NOOP_1, 047, "daa",
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{ 0, NOOP_1, 047, "daa" },
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0, NOOP_1, 057, "das",
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{ 0, NOOP_1, 057, "das" },
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0, NOOP_1, 067, "aaa",
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{ 0, NOOP_1, 067, "aaa" },
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0, NOOP_1, 077, "aas",
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{ 0, NOOP_1, 077, "aas" },
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0, NOOP_1, 0220, "nop",
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{ 0, NOOP_1, 0220, "nop" },
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0, NOOP_1, 0230, "cbw",
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{ 0, NOOP_1, 0230, "cbw" },
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0, NOOP_1, 0231, "cwd",
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{ 0, NOOP_1, 0231, "cwd" },
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0, NOOP_1, 0233, "wait",
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{ 0, NOOP_1, 0233, "wait" },
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0, NOOP_1, 0234, "pushf",
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{ 0, NOOP_1, 0234, "pushf" },
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0, NOOP_1, 0235, "popf",
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{ 0, NOOP_1, 0235, "popf" },
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0, NOOP_1, 0236, "sahf",
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{ 0, NOOP_1, 0236, "sahf" },
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0, NOOP_1, 0237, "lahf",
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{ 0, NOOP_1, 0237, "lahf" },
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0, NOOP_1, 0244, "movsb",
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{ 0, NOOP_1, 0244, "movsb" },
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0, NOOP_1, 0245, "movs",
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{ 0, NOOP_1, 0245, "movs" },
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0, NOOP_1, 0245, "movsw",
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{ 0, NOOP_1, 0245, "movsw" },
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0, NOOP_1, 0246, "cmpsb",
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{ 0, NOOP_1, 0246, "cmpsb" },
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0, NOOP_1, 0247, "cmps",
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{ 0, NOOP_1, 0247, "cmps" },
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0, NOOP_1, 0247, "cmpsw",
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{ 0, NOOP_1, 0247, "cmpsw" },
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0, NOOP_1, 0252, "stosb",
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{ 0, NOOP_1, 0252, "stosb" },
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0, NOOP_1, 0253, "stos",
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{ 0, NOOP_1, 0253, "stos" },
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0, NOOP_1, 0253, "stosw",
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{ 0, NOOP_1, 0253, "stosw" },
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0, NOOP_1, 0254, "lodsb",
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{ 0, NOOP_1, 0254, "lodsb" },
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0, NOOP_1, 0255, "lods",
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{ 0, NOOP_1, 0255, "lods" },
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0, NOOP_1, 0255, "lodsw",
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{ 0, NOOP_1, 0255, "lodsw" },
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0, NOOP_1, 0256, "scasb",
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{ 0, NOOP_1, 0256, "scasb" },
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0, NOOP_1, 0257, "scas",
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{ 0, NOOP_1, 0257, "scas" },
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0, NOOP_1, 0257, "scasw",
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{ 0, NOOP_1, 0257, "scasw" },
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0, NOOP_1, 0316, "into",
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{ 0, NOOP_1, 0316, "into" },
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0, NOOP_1, 0317, "iret",
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{ 0, NOOP_1, 0317, "iret" },
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0, NOOP_1, 0327, "xlat",
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{ 0, NOOP_1, 0327, "xlat" },
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0, NOOP_1, 0364, "hlt",
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{ 0, NOOP_1, 0364, "hlt" },
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0, NOOP_1, 0365, "cmc",
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{ 0, NOOP_1, 0365, "cmc" },
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0, NOOP_1, 0370, "clc",
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{ 0, NOOP_1, 0370, "clc" },
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0, NOOP_1, 0371, "stc",
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{ 0, NOOP_1, 0371, "stc" },
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0, NOOP_1, 0372, "cli",
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{ 0, NOOP_1, 0372, "cli" },
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0, NOOP_1, 0373, "sti",
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{ 0, NOOP_1, 0373, "sti" },
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0, NOOP_1, 0374, "cld",
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{ 0, NOOP_1, 0374, "cld" },
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0, NOOP_1, 0375, "std",
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{ 0, NOOP_1, 0375, "std" },
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0, NOOP_2, 0324+012<<8, "aam",
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{ 0, NOOP_2, 0324+012<<8, "aam" },
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0, NOOP_2, 0325+012<<8, "aad",
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{ 0, NOOP_2, 0325+012<<8, "aad" },
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0, JOP, 0340, "loopne",
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{ 0, JOP, 0340, "loopne" },
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0, JOP, 0340, "loopnz",
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{ 0, JOP, 0340, "loopnz" },
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0, JOP, 0341, "loope",
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{ 0, JOP, 0341, "loope" },
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0, JOP, 0341, "loopz",
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{ 0, JOP, 0341, "loopz" },
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0, JOP, 0342, "loop",
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{ 0, JOP, 0342, "loop" },
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0, JOP, 0343, "jcxz",
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{ 0, JOP, 0343, "jcxz" },
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0, JOP, 0160, "jo",
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{ 0, JOP, 0160, "jo" },
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0, JOP, 0161, "jno",
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{ 0, JOP, 0161, "jno" },
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0, JOP, 0162, "jb",
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{ 0, JOP, 0162, "jb" },
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0, JOP, 0162, "jc",
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{ 0, JOP, 0162, "jc" },
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0, JOP, 0162, "jnae",
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{ 0, JOP, 0162, "jnae" },
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0, JOP, 0163, "jae",
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{ 0, JOP, 0163, "jae" },
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0, JOP, 0163, "jnb",
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{ 0, JOP, 0163, "jnb" },
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0, JOP, 0163, "jnc",
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{ 0, JOP, 0163, "jnc" },
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0, JOP, 0164, "je",
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{ 0, JOP, 0164, "je" },
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0, JOP, 0164, "jz",
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{ 0, JOP, 0164, "jz" },
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0, JOP, 0165, "jne",
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{ 0, JOP, 0165, "jne" },
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0, JOP, 0165, "jnz",
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{ 0, JOP, 0165, "jnz" },
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0, JOP, 0166, "jbe",
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{ 0, JOP, 0166, "jbe" },
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0, JOP, 0166, "jna",
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{ 0, JOP, 0166, "jna" },
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0, JOP, 0167, "ja",
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{ 0, JOP, 0167, "ja" },
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0, JOP, 0167, "jnbe",
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{ 0, JOP, 0167, "jnbe" },
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0, JOP, 0170, "js",
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{ 0, JOP, 0170, "js" },
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0, JOP, 0171, "jns",
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{ 0, JOP, 0171, "jns" },
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0, JOP, 0172, "jp",
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{ 0, JOP, 0172, "jp" },
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0, JOP, 0172, "jpe",
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{ 0, JOP, 0172, "jpe" },
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0, JOP, 0173, "jnp",
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{ 0, JOP, 0173, "jnp" },
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0, JOP, 0173, "jpo",
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{ 0, JOP, 0173, "jpo" },
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0, JOP, 0174, "jl",
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{ 0, JOP, 0174, "jl" },
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0, JOP, 0174, "jnge",
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{ 0, JOP, 0174, "jnge" },
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0, JOP, 0175, "jge",
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{ 0, JOP, 0175, "jge" },
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0, JOP, 0175, "jnl",
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{ 0, JOP, 0175, "jnl" },
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0, JOP, 0176, "jle",
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{ 0, JOP, 0176, "jle" },
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0, JOP, 0176, "jng",
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{ 0, JOP, 0176, "jng" },
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0, JOP, 0177, "jg",
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{ 0, JOP, 0177, "jg" },
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0, JOP, 0177, "jnle",
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{ 0, JOP, 0177, "jnle" },
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0, PUSHOP, 0, "push",
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{ 0, PUSHOP, 0, "push" },
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0, PUSHOP, 1, "pop",
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{ 0, PUSHOP, 1, "pop" },
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0, IOOP, 0344, "inb",
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{ 0, IOOP, 0344, "inb" },
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0, IOOP, 0345, "in",
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{ 0, IOOP, 0345, "in" },
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0, IOOP, 0345, "inw",
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{ 0, IOOP, 0345, "inw" },
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0, IOOP, 0346, "outb",
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{ 0, IOOP, 0346, "outb" },
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0, IOOP, 0347, "out",
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{ 0, IOOP, 0347, "out" },
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0, IOOP, 0347, "outw",
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{ 0, IOOP, 0347, "outw" },
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0, ADDOP, 000, "addb",
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{ 0, ADDOP, 000, "addb" },
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0, ADDOP, 001, "add",
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{ 0, ADDOP, 001, "add" },
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0, ADDOP, 010, "orb",
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{ 0, ADDOP, 010, "orb" },
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0, ADDOP, 011, "or",
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{ 0, ADDOP, 011, "or" },
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0, ADDOP, 020, "adcb",
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{ 0, ADDOP, 020, "adcb" },
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0, ADDOP, 021, "adc",
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{ 0, ADDOP, 021, "adc" },
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0, ADDOP, 030, "sbbb",
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{ 0, ADDOP, 030, "sbbb" },
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0, ADDOP, 031, "sbb",
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{ 0, ADDOP, 031, "sbb" },
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0, ADDOP, 040, "andb",
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{ 0, ADDOP, 040, "andb" },
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0, ADDOP, 041, "and",
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{ 0, ADDOP, 041, "and" },
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0, ADDOP, 050, "subb",
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{ 0, ADDOP, 050, "subb" },
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0, ADDOP, 051, "sub",
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{ 0, ADDOP, 051, "sub" },
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0, ADDOP, 060, "xorb",
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{ 0, ADDOP, 060, "xorb" },
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0, ADDOP, 061, "xor",
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{ 0, ADDOP, 061, "xor" },
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0, ADDOP, 070, "cmpb",
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{ 0, ADDOP, 070, "cmpb" },
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0, ADDOP, 071, "cmp",
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{ 0, ADDOP, 071, "cmp" },
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0, ROLOP, 000, "rolb",
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{ 0, ROLOP, 000, "rolb" },
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0, ROLOP, 001, "rol",
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{ 0, ROLOP, 001, "rol" },
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0, ROLOP, 010, "rorb",
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{ 0, ROLOP, 010, "rorb" },
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0, ROLOP, 011, "ror",
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{ 0, ROLOP, 011, "ror" },
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0, ROLOP, 020, "rclb",
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{ 0, ROLOP, 020, "rclb" },
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0, ROLOP, 021, "rcl",
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{ 0, ROLOP, 021, "rcl" },
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0, ROLOP, 030, "rcrb",
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{ 0, ROLOP, 030, "rcrb" },
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0, ROLOP, 031, "rcr",
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{ 0, ROLOP, 031, "rcr" },
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0, ROLOP, 040, "salb",
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{ 0, ROLOP, 040, "salb" },
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0, ROLOP, 040, "shlb",
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{ 0, ROLOP, 040, "shlb" },
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0, ROLOP, 041, "sal",
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{ 0, ROLOP, 041, "sal" },
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0, ROLOP, 041, "shl",
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{ 0, ROLOP, 041, "shl" },
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0, ROLOP, 050, "shrb",
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{ 0, ROLOP, 050, "shrb" },
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0, ROLOP, 051, "shr",
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{ 0, ROLOP, 051, "shr" },
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0, ROLOP, 070, "sarb",
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{ 0, ROLOP, 070, "sarb" },
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0, ROLOP, 071, "sar",
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{ 0, ROLOP, 071, "sar" },
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0, INCOP, 000, "incb",
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{ 0, INCOP, 000, "incb" },
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0, INCOP, 001, "inc",
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{ 0, INCOP, 001, "inc" },
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0, INCOP, 010, "decb",
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{ 0, INCOP, 010, "decb" },
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0, INCOP, 011, "dec",
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{ 0, INCOP, 011, "dec" },
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0, NOTOP, 020, "notb",
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{ 0, NOTOP, 020, "notb" },
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0, NOTOP, 021, "not",
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{ 0, NOTOP, 021, "not" },
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0, NOTOP, 030, "negb",
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{ 0, NOTOP, 030, "negb" },
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0, NOTOP, 031, "neg",
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{ 0, NOTOP, 031, "neg" },
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0, NOTOP, 040, "mulb",
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{ 0, NOTOP, 040, "mulb" },
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0, NOTOP, 041, "mul",
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{ 0, NOTOP, 041, "mul" },
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0, NOTOP, 050, "imulb",
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{ 0, NOTOP, 050, "imulb" },
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0, IMUL, 051, "imul", /* for 80286 */
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{ 0, IMUL, 051, "imul" }, /* for 80286 */
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0, NOTOP, 060, "divb",
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{ 0, NOTOP, 060, "divb" },
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0, NOTOP, 061, "div",
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{ 0, NOTOP, 061, "div" },
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0, NOTOP, 070, "idivb",
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{ 0, NOTOP, 070, "idivb" },
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0, NOTOP, 071, "idiv",
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{ 0, NOTOP, 071, "idiv" },
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0, CALLOP, 020+(0350<<8), "call",
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{ 0, CALLOP, 020+(0350<<8), "call" },
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0, CALLOP, 040+(0351<<8), "jmp",
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{ 0, CALLOP, 040+(0351<<8), "jmp" },
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0, CALFOP, 030+(0232<<8), "callf",
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{ 0, CALFOP, 030+(0232<<8), "callf" },
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0, CALFOP, 050+(0352<<8), "jmpf",
|
{ 0, CALFOP, 050+(0352<<8), "jmpf" },
|
||||||
0, LEAOP, 0215, "lea",
|
{ 0, LEAOP, 0215, "lea" },
|
||||||
0, LEAOP, 0304, "les",
|
{ 0, LEAOP, 0304, "les" },
|
||||||
0, LEAOP, 0305, "lds",
|
{ 0, LEAOP, 0305, "lds" },
|
||||||
0, ESC, 0, "esc",
|
{ 0, ESC, 0, "esc" },
|
||||||
0, INT, 0, "int",
|
{ 0, INT, 0, "int" },
|
||||||
0, RET, 0303, "ret",
|
{ 0, RET, 0303, "ret" },
|
||||||
0, RET, 0313, "retf",
|
{ 0, RET, 0313, "retf" },
|
||||||
0, XCHG, 0, "xchgb",
|
{ 0, XCHG, 0, "xchgb" },
|
||||||
0, XCHG, 1, "xchg",
|
{ 0, XCHG, 1, "xchg" },
|
||||||
0, TEST, 0, "testb",
|
{ 0, TEST, 0, "testb" },
|
||||||
0, TEST, 1, "test",
|
{ 0, TEST, 1, "test" },
|
||||||
0, MOV, 0, "movb",
|
{ 0, MOV, 0, "movb" },
|
||||||
0, MOV, 1, "mov",
|
{ 0, MOV, 1, "mov" },
|
||||||
0, MOV, 1, "movw",
|
{ 0, MOV, 1, "movw" },
|
||||||
|
|
||||||
/* Intel 8087 coprocessor keywords */
|
/* Intel 8087 coprocessor keywords */
|
||||||
|
|
||||||
0, ST, 0, "st",
|
{ 0, ST, 0, "st" },
|
||||||
|
|
||||||
0, FNOOP, FESC+1+(0xF0<<8), "f2xm1",
|
{ 0, FNOOP, FESC+1+(0xF0<<8), "f2xm1" },
|
||||||
0, FNOOP, FESC+1+(0xE1<<8), "fabs",
|
{ 0, FNOOP, FESC+1+(0xE1<<8), "fabs" },
|
||||||
0, FNOOP, FESC+1+(0xE0<<8), "fchs",
|
{ 0, FNOOP, FESC+1+(0xE0<<8), "fchs" },
|
||||||
0, FNOOP, FESC+3+(0xE2<<8), "fclex",
|
{ 0, FNOOP, FESC+3+(0xE2<<8), "fclex" },
|
||||||
0, FNOOP, FESC+6+(0xD9<<8), "fcompp",
|
{ 0, FNOOP, FESC+6+(0xD9<<8), "fcompp" },
|
||||||
0, FNOOP, FESC+1+(0xF6<<8), "fdecstp",
|
{ 0, FNOOP, FESC+1+(0xF6<<8), "fdecstp" },
|
||||||
0, FNOOP, FESC+3+(0xE1<<8), "fdisi",
|
{ 0, FNOOP, FESC+3+(0xE1<<8), "fdisi" },
|
||||||
0, FNOOP, FESC+3+(0xE0<<8), "feni",
|
{ 0, FNOOP, FESC+3+(0xE0<<8), "feni" },
|
||||||
0, FNOOP, FESC+1+(0xF7<<8), "fincstp",
|
{ 0, FNOOP, FESC+1+(0xF7<<8), "fincstp" },
|
||||||
0, FNOOP, FESC+3+(0xE3<<8), "finit",
|
{ 0, FNOOP, FESC+3+(0xE3<<8), "finit" },
|
||||||
0, FNOOP, FESC+1+(0xE8<<8), "fld1",
|
{ 0, FNOOP, FESC+1+(0xE8<<8), "fld1" },
|
||||||
0, FNOOP, FESC+1+(0xEA<<8), "fldl2e",
|
{ 0, FNOOP, FESC+1+(0xEA<<8), "fldl2e" },
|
||||||
0, FNOOP, FESC+1+(0xE9<<8), "fldl2t",
|
{ 0, FNOOP, FESC+1+(0xE9<<8), "fldl2t" },
|
||||||
0, FNOOP, FESC+1+(0xEC<<8), "fldlg2",
|
{ 0, FNOOP, FESC+1+(0xEC<<8), "fldlg2" },
|
||||||
0, FNOOP, FESC+1+(0xED<<8), "fldln2",
|
{ 0, FNOOP, FESC+1+(0xED<<8), "fldln2" },
|
||||||
0, FNOOP, FESC+1+(0xEB<<8), "fldpi",
|
{ 0, FNOOP, FESC+1+(0xEB<<8), "fldpi" },
|
||||||
0, FNOOP, FESC+1+(0xEE<<8), "fldz",
|
{ 0, FNOOP, FESC+1+(0xEE<<8), "fldz" },
|
||||||
0, FNOOP, FESC+1+(0xD0<<8), "fnop",
|
{ 0, FNOOP, FESC+1+(0xD0<<8), "fnop" },
|
||||||
0, FNOOP, FESC+1+(0xF3<<8), "fpatan",
|
{ 0, FNOOP, FESC+1+(0xF3<<8), "fpatan" },
|
||||||
0, FNOOP, FESC+1+(0xF8<<8), "fprem",
|
{ 0, FNOOP, FESC+1+(0xF8<<8), "fprem" },
|
||||||
0, FNOOP, FESC+1+(0xF2<<8), "fptan",
|
{ 0, FNOOP, FESC+1+(0xF2<<8), "fptan" },
|
||||||
0, FNOOP, FESC+1+(0xFC<<8), "frndint",
|
{ 0, FNOOP, FESC+1+(0xFC<<8), "frndint" },
|
||||||
0, FNOOP, FESC+1+(0xFD<<8), "fscale",
|
{ 0, FNOOP, FESC+1+(0xFD<<8), "fscale" },
|
||||||
0, FNOOP, FESC+1+(0xFA<<8), "fsqrt",
|
{ 0, FNOOP, FESC+1+(0xFA<<8), "fsqrt" },
|
||||||
0, FNOOP, FESC+7+(0xE0<<8), "fstswax", /* 80287 */
|
{ 0, FNOOP, FESC+7+(0xE0<<8), "fstswax" }, /* 80287 */
|
||||||
0, FNOOP, FESC+1+(0xE4<<8), "ftst",
|
{ 0, FNOOP, FESC+1+(0xE4<<8), "ftst" },
|
||||||
0, FNOOP, FESC+1+(0xE5<<8), "fxam",
|
{ 0, FNOOP, FESC+1+(0xE5<<8), "fxam" },
|
||||||
0, FNOOP, FESC+1+(0xF4<<8), "fxtract",
|
{ 0, FNOOP, FESC+1+(0xF4<<8), "fxtract" },
|
||||||
0, FNOOP, FESC+1+(0xF1<<8), "fyl2x",
|
{ 0, FNOOP, FESC+1+(0xF1<<8), "fyl2x" },
|
||||||
0, FNOOP, FESC+1+(0xF9<<8), "fyl2pi",
|
{ 0, FNOOP, FESC+1+(0xF9<<8), "fyl2pi" },
|
||||||
|
|
||||||
0, FMEM, FESC+6+(0<<11), "fiadds",
|
{ 0, FMEM, FESC+6+(0<<11), "fiadds" },
|
||||||
0, FMEM, FESC+2+(0<<11), "fiaddl",
|
{ 0, FMEM, FESC+2+(0<<11), "fiaddl" },
|
||||||
0, FMEM, FESC+0+(0<<11), "fadds",
|
{ 0, FMEM, FESC+0+(0<<11), "fadds" },
|
||||||
0, FMEM, FESC+4+(0<<11), "faddd",
|
{ 0, FMEM, FESC+4+(0<<11), "faddd" },
|
||||||
0, FMEM, FESC+7+(4<<11), "fbld",
|
{ 0, FMEM, FESC+7+(4<<11), "fbld" },
|
||||||
0, FMEM, FESC+7+(6<<11), "fbstp",
|
{ 0, FMEM, FESC+7+(6<<11), "fbstp" },
|
||||||
0, FMEM, FESC+6+(2<<11), "ficoms",
|
{ 0, FMEM, FESC+6+(2<<11), "ficoms" },
|
||||||
0, FMEM, FESC+2+(2<<11), "ficoml",
|
{ 0, FMEM, FESC+2+(2<<11), "ficoml" },
|
||||||
0, FMEM, FESC+0+(2<<11), "fcoms",
|
{ 0, FMEM, FESC+0+(2<<11), "fcoms" },
|
||||||
0, FMEM, FESC+4+(2<<11), "fcomd",
|
{ 0, FMEM, FESC+4+(2<<11), "fcomd" },
|
||||||
0, FMEM, FESC+6+(3<<11), "ficomps",
|
{ 0, FMEM, FESC+6+(3<<11), "ficomps" },
|
||||||
0, FMEM, FESC+2+(3<<11), "ficompl",
|
{ 0, FMEM, FESC+2+(3<<11), "ficompl" },
|
||||||
0, FMEM, FESC+0+(3<<11), "fcomps",
|
{ 0, FMEM, FESC+0+(3<<11), "fcomps" },
|
||||||
0, FMEM, FESC+4+(3<<11), "fcompd",
|
{ 0, FMEM, FESC+4+(3<<11), "fcompd" },
|
||||||
0, FMEM, FESC+6+(6<<11), "fidivs",
|
{ 0, FMEM, FESC+6+(6<<11), "fidivs" },
|
||||||
0, FMEM, FESC+2+(6<<11), "fidivl",
|
{ 0, FMEM, FESC+2+(6<<11), "fidivl" },
|
||||||
0, FMEM, FESC+0+(6<<11), "fdivs",
|
{ 0, FMEM, FESC+0+(6<<11), "fdivs" },
|
||||||
0, FMEM, FESC+4+(6<<11), "fdivd",
|
{ 0, FMEM, FESC+4+(6<<11), "fdivd" },
|
||||||
0, FMEM, FESC+6+(7<<11), "fidivrs",
|
{ 0, FMEM, FESC+6+(7<<11), "fidivrs" },
|
||||||
0, FMEM, FESC+2+(7<<11), "fidivrl",
|
{ 0, FMEM, FESC+2+(7<<11), "fidivrl" },
|
||||||
0, FMEM, FESC+0+(7<<11), "fdivrs",
|
{ 0, FMEM, FESC+0+(7<<11), "fdivrs" },
|
||||||
0, FMEM, FESC+4+(7<<11), "fdivrd",
|
{ 0, FMEM, FESC+4+(7<<11), "fdivrd" },
|
||||||
0, FMEM, FESC+7+(5<<11), "fildq",
|
{ 0, FMEM, FESC+7+(5<<11), "fildq" },
|
||||||
0, FMEM, FESC+7+(0<<11), "filds",
|
{ 0, FMEM, FESC+7+(0<<11), "filds" },
|
||||||
0, FMEM, FESC+3+(0<<11), "fildl",
|
{ 0, FMEM, FESC+3+(0<<11), "fildl" },
|
||||||
0, FMEM, FESC+1+(0<<11), "flds",
|
{ 0, FMEM, FESC+1+(0<<11), "flds" },
|
||||||
0, FMEM, FESC+5+(0<<11), "fldd",
|
{ 0, FMEM, FESC+5+(0<<11), "fldd" },
|
||||||
0, FMEM, FESC+3+(5<<11), "fldx",
|
{ 0, FMEM, FESC+3+(5<<11), "fldx" },
|
||||||
0, FMEM, FESC+1+(5<<11), "fldcw",
|
{ 0, FMEM, FESC+1+(5<<11), "fldcw" },
|
||||||
0, FMEM, FESC+1+(4<<11), "fldenv",
|
{ 0, FMEM, FESC+1+(4<<11), "fldenv" },
|
||||||
0, FMEM, FESC+6+(1<<11), "fimuls",
|
{ 0, FMEM, FESC+6+(1<<11), "fimuls" },
|
||||||
0, FMEM, FESC+2+(1<<11), "fimull",
|
{ 0, FMEM, FESC+2+(1<<11), "fimull" },
|
||||||
0, FMEM, FESC+0+(1<<11), "fmuls",
|
{ 0, FMEM, FESC+0+(1<<11), "fmuls" },
|
||||||
0, FMEM, FESC+4+(1<<11), "fmuld",
|
{ 0, FMEM, FESC+4+(1<<11), "fmuld" },
|
||||||
0, FMEM, FESC+5+(4<<11), "frstor",
|
{ 0, FMEM, FESC+5+(4<<11), "frstor" },
|
||||||
0, FMEM, FESC+5+(6<<11), "fsave",
|
{ 0, FMEM, FESC+5+(6<<11), "fsave" },
|
||||||
0, FMEM, FESC+7+(2<<11), "fists",
|
{ 0, FMEM, FESC+7+(2<<11), "fists" },
|
||||||
0, FMEM, FESC+3+(2<<11), "fistl",
|
{ 0, FMEM, FESC+3+(2<<11), "fistl" },
|
||||||
0, FMEM, FESC+1+(2<<11), "fsts",
|
{ 0, FMEM, FESC+1+(2<<11), "fsts" },
|
||||||
0, FMEM, FESC+5+(2<<11), "fstd",
|
{ 0, FMEM, FESC+5+(2<<11), "fstd" },
|
||||||
0, FMEM, FESC+7+(7<<11), "fistpq",
|
{ 0, FMEM, FESC+7+(7<<11), "fistpq" },
|
||||||
0, FMEM, FESC+7+(3<<11), "fistps",
|
{ 0, FMEM, FESC+7+(3<<11), "fistps" },
|
||||||
0, FMEM, FESC+3+(3<<11), "fistpl",
|
{ 0, FMEM, FESC+3+(3<<11), "fistpl" },
|
||||||
0, FMEM, FESC+1+(3<<11), "fstps",
|
{ 0, FMEM, FESC+1+(3<<11), "fstps" },
|
||||||
0, FMEM, FESC+5+(3<<11), "fstpd",
|
{ 0, FMEM, FESC+5+(3<<11), "fstpd" },
|
||||||
0, FMEM, FESC+3+(7<<11), "fstpx",
|
{ 0, FMEM, FESC+3+(7<<11), "fstpx" },
|
||||||
0, FMEM, FESC+1+(7<<11), "fstcw",
|
{ 0, FMEM, FESC+1+(7<<11), "fstcw" },
|
||||||
0, FMEM, FESC+1+(6<<11), "fstenv",
|
{ 0, FMEM, FESC+1+(6<<11), "fstenv" },
|
||||||
0, FMEM, FESC+5+(7<<11), "fstsw",
|
{ 0, FMEM, FESC+5+(7<<11), "fstsw" },
|
||||||
0, FMEM, FESC+6+(4<<11), "fisubs",
|
{ 0, FMEM, FESC+6+(4<<11), "fisubs" },
|
||||||
0, FMEM, FESC+2+(4<<11), "fisubl",
|
{ 0, FMEM, FESC+2+(4<<11), "fisubl" },
|
||||||
0, FMEM, FESC+0+(4<<11), "fsubs",
|
{ 0, FMEM, FESC+0+(4<<11), "fsubs" },
|
||||||
0, FMEM, FESC+4+(4<<11), "fsubd",
|
{ 0, FMEM, FESC+4+(4<<11), "fsubd" },
|
||||||
0, FMEM, FESC+6+(5<<11), "fisubrs",
|
{ 0, FMEM, FESC+6+(5<<11), "fisubrs" },
|
||||||
0, FMEM, FESC+2+(5<<11), "fisubrl",
|
{ 0, FMEM, FESC+2+(5<<11), "fisubrl" },
|
||||||
0, FMEM, FESC+0+(5<<11), "fsubrs",
|
{ 0, FMEM, FESC+0+(5<<11), "fsubrs" },
|
||||||
0, FMEM, FESC+4+(5<<11), "fsubrd",
|
{ 0, FMEM, FESC+4+(5<<11), "fsubrd" },
|
||||||
|
|
||||||
0, FST_I, FESC+1+(0xC0<<8), "fld",
|
{ 0, FST_I, FESC+1+(0xC0<<8), "fld" },
|
||||||
0, FST_I, FESC+5+(0xD0<<8), "fst",
|
{ 0, FST_I, FESC+5+(0xD0<<8), "fst" },
|
||||||
0, FST_I, FESC+5+(0xC8<<8), "fstp",
|
{ 0, FST_I, FESC+5+(0xC8<<8), "fstp" },
|
||||||
0, FST_I, FESC+1+(0xC8<<8), "fxch",
|
{ 0, FST_I, FESC+1+(0xC8<<8), "fxch" },
|
||||||
0, FST_I, FESC+0+(0xD0<<8), "fcom",
|
{ 0, FST_I, FESC+0+(0xD0<<8), "fcom" },
|
||||||
0, FST_I, FESC+0+(0xD8<<8), "fcomp",
|
{ 0, FST_I, FESC+0+(0xD8<<8), "fcomp" },
|
||||||
0, FST_I, FESC+5+(0xC0<<8), "ffree",
|
{ 0, FST_I, FESC+5+(0xC0<<8), "ffree" },
|
||||||
|
|
||||||
0, FST_ST, FESC+0+(0xC0<<8), "fadd",
|
{ 0, FST_ST, FESC+0+(0xC0<<8), "fadd" },
|
||||||
0, FST_ST, FESC+2+(0xC0<<8), "faddp",
|
{ 0, FST_ST, FESC+2+(0xC0<<8), "faddp" },
|
||||||
0, FST_ST2, FESC+0+(0xF0<<8), "fdiv",
|
{ 0, FST_ST2, FESC+0+(0xF0<<8), "fdiv" },
|
||||||
0, FST_ST2, FESC+2+(0xF0<<8), "fdivp",
|
{ 0, FST_ST2, FESC+2+(0xF0<<8), "fdivp" },
|
||||||
0, FST_ST2, FESC+0+(0xF8<<8), "fdivr",
|
{ 0, FST_ST2, FESC+0+(0xF8<<8), "fdivr" },
|
||||||
0, FST_ST2, FESC+2+(0xF8<<8), "fdivrp",
|
{ 0, FST_ST2, FESC+2+(0xF8<<8), "fdivrp" },
|
||||||
0, FST_ST, FESC+0+(0xC8<<8), "fmul",
|
{ 0, FST_ST, FESC+0+(0xC8<<8), "fmul" },
|
||||||
0, FST_ST, FESC+2+(0xC8<<8), "fmulp",
|
{ 0, FST_ST, FESC+2+(0xC8<<8), "fmulp" },
|
||||||
0, FST_ST2, FESC+0+(0xE0<<8), "fsub",
|
{ 0, FST_ST2, FESC+0+(0xE0<<8), "fsub" },
|
||||||
0, FST_ST2, FESC+2+(0xE0<<8), "fsubp",
|
{ 0, FST_ST2, FESC+2+(0xE0<<8), "fsubp" },
|
||||||
0, FST_ST2, FESC+0+(0xE8<<8), "fsubr",
|
{ 0, FST_ST2, FESC+0+(0xE8<<8), "fsubr" },
|
||||||
0, FST_ST2, FESC+2+(0xE8<<8), "fsubrp",
|
{ 0, FST_ST2, FESC+2+(0xE8<<8), "fsubrp" },
|
||||||
|
|
||||||
/* 80286 keywords */
|
/* 80286 keywords */
|
||||||
0, NOOP_1, 0140, "pusha",
|
{ 0, NOOP_1, 0140, "pusha" },
|
||||||
0, NOOP_1, 0141, "popa",
|
{ 0, NOOP_1, 0141, "popa" },
|
||||||
0, NOOP_1, 0154, "insb",
|
{ 0, NOOP_1, 0154, "insb" },
|
||||||
0, NOOP_1, 0155, "ins",
|
{ 0, NOOP_1, 0155, "ins" },
|
||||||
0, NOOP_1, 0155, "insw",
|
{ 0, NOOP_1, 0155, "insw" },
|
||||||
0, NOOP_1, 0156, "outsb",
|
{ 0, NOOP_1, 0156, "outsb" },
|
||||||
0, NOOP_1, 0157, "outs",
|
{ 0, NOOP_1, 0157, "outs" },
|
||||||
0, NOOP_1, 0157, "outsw",
|
{ 0, NOOP_1, 0157, "outsw" },
|
||||||
|
|
||||||
0, ARPLOP, 0143, "arpl",
|
{ 0, ARPLOP, 0143, "arpl" },
|
||||||
0, ENTER, 0310, "enter",
|
{ 0, ENTER, 0310, "enter" },
|
||||||
0, NOOP_1, 0311, "leave",
|
{ 0, NOOP_1, 0311, "leave" },
|
||||||
0, LEAOP, 0142, "bound",
|
{ 0, LEAOP, 0142, "bound" },
|
||||||
|
|
||||||
0, NOOP_2, 017+06<<8, "clts",
|
{ 0, NOOP_2, 017+06<<8, "clts" },
|
||||||
|
|
||||||
0, EXTOP, 0002, "lar",
|
{ 0, EXTOP, 0002, "lar" },
|
||||||
0, EXTOP, 0003, "lsl",
|
{ 0, EXTOP, 0003, "lsl" },
|
||||||
|
|
||||||
0, EXTOP1, 0021, "lgdt",
|
{ 0, EXTOP1, 0021, "lgdt" },
|
||||||
0, EXTOP1, 0001, "sgdt",
|
{ 0, EXTOP1, 0001, "sgdt" },
|
||||||
0, EXTOP1, 0031, "lidt",
|
{ 0, EXTOP1, 0031, "lidt" },
|
||||||
0, EXTOP1, 0011, "sidt",
|
{ 0, EXTOP1, 0011, "sidt" },
|
||||||
0, EXTOP1, 0020, "lldt",
|
{ 0, EXTOP1, 0020, "lldt" },
|
||||||
0, EXTOP1, 0000, "sldt",
|
{ 0, EXTOP1, 0000, "sldt" },
|
||||||
0, EXTOP1, 0030, "ltr",
|
{ 0, EXTOP1, 0030, "ltr" },
|
||||||
0, EXTOP1, 0010, "str",
|
{ 0, EXTOP1, 0010, "str" },
|
||||||
0, EXTOP1, 0061, "lmsw",
|
{ 0, EXTOP1, 0061, "lmsw" },
|
||||||
0, EXTOP1, 0041, "smsw",
|
{ 0, EXTOP1, 0041, "smsw" },
|
||||||
0, EXTOP1, 0050, "verw",
|
{ 0, EXTOP1, 0050, "verw" },
|
||||||
0, EXTOP1, 0040, "verr",
|
{ 0, EXTOP1, 0040, "verr" },
|
||||||
|
|||||||
@ -8,8 +8,8 @@
|
|||||||
* INTEL 8086 special routines
|
* INTEL 8086 special routines
|
||||||
*/
|
*/
|
||||||
|
|
||||||
ea_1(param) {
|
void ea_1(int param)
|
||||||
|
{
|
||||||
if ((mrg_1 & 070) || (param & ~070)) {
|
if ((mrg_1 & 070) || (param & ~070)) {
|
||||||
serror("bad operand");
|
serror("bad operand");
|
||||||
}
|
}
|
||||||
@ -41,16 +41,17 @@ ea_1(param) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
ea_2(param) {
|
void ea_2(int param)
|
||||||
|
{
|
||||||
mrg_1 = mrg_2;
|
mrg_1 = mrg_2;
|
||||||
exp_1 = exp_2;
|
exp_1 = exp_2;
|
||||||
RELOMOVE(rel_1, rel_2);
|
RELOMOVE(rel_1, rel_2);
|
||||||
ea_1(param);
|
ea_1(param);
|
||||||
}
|
}
|
||||||
|
|
||||||
reverse() {
|
void reverse()
|
||||||
register m, r; expr_t e;
|
{
|
||||||
|
int m, r; expr_t e;
|
||||||
|
|
||||||
m = mrg_1; mrg_1 = mrg_2; mrg_2 = m;
|
m = mrg_1; mrg_1 = mrg_2; mrg_2 = m;
|
||||||
e = exp_1; exp_1 = exp_2; exp_2 = e;
|
e = exp_1; exp_1 = exp_2; exp_2 = e;
|
||||||
@ -59,13 +60,14 @@ reverse() {
|
|||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
badsyntax() {
|
void badsyntax()
|
||||||
|
{
|
||||||
serror("bad operands");
|
serror("bad operands");
|
||||||
}
|
}
|
||||||
|
|
||||||
regsize(sz) register sz; {
|
void regsize(int sz)
|
||||||
register bit;
|
{
|
||||||
|
int bit;
|
||||||
|
|
||||||
sz <<= 3;
|
sz <<= 3;
|
||||||
bit = 010;
|
bit = 010;
|
||||||
@ -77,7 +79,8 @@ regsize(sz) register sz; {
|
|||||||
mrg_2 &= ~bit;
|
mrg_2 &= ~bit;
|
||||||
}
|
}
|
||||||
|
|
||||||
indexed() {
|
void indexed()
|
||||||
|
{
|
||||||
int sm1, sm2;
|
int sm1, sm2;
|
||||||
|
|
||||||
if (mrg_2 & ~7)
|
if (mrg_2 & ~7)
|
||||||
@ -98,8 +101,9 @@ indexed() {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
branch(opc,exp) register opc; expr_t exp; {
|
void branch(int opc, expr_t exp)
|
||||||
register sm,dist;
|
{
|
||||||
|
int sm,dist;
|
||||||
int saving = opc == 0353 ? 1 : 3;
|
int saving = opc == 0353 ? 1 : 3;
|
||||||
|
|
||||||
dist = exp.val - (DOTVAL + 2);
|
dist = exp.val - (DOTVAL + 2);
|
||||||
@ -132,8 +136,8 @@ branch(opc,exp) register opc; expr_t exp; {
|
|||||||
emit1(dist);
|
emit1(dist);
|
||||||
}
|
}
|
||||||
|
|
||||||
pushop(opc) register opc; {
|
void pushop(int opc)
|
||||||
|
{
|
||||||
regsize(1);
|
regsize(1);
|
||||||
if (mrg_1 & 020) {
|
if (mrg_1 & 020) {
|
||||||
if ( (mrg_1&3) == 1 && opc==1 ) badsyntax() ;
|
if ( (mrg_1&3) == 1 && opc==1 ) badsyntax() ;
|
||||||
@ -161,8 +165,8 @@ pushop(opc) register opc; {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
addop(opc) register opc; {
|
void addop(int opc)
|
||||||
|
{
|
||||||
regsize(opc);
|
regsize(opc);
|
||||||
if (mrg_2 >= 0300) {
|
if (mrg_2 >= 0300) {
|
||||||
emit1(opc); ea_1((mrg_2&7)<<3);
|
emit1(opc); ea_1((mrg_2&7)<<3);
|
||||||
@ -197,8 +201,9 @@ addop(opc) register opc; {
|
|||||||
badsyntax();
|
badsyntax();
|
||||||
}
|
}
|
||||||
|
|
||||||
rolop(opc) register opc; {
|
void rolop(int opc)
|
||||||
register cmrg;
|
{
|
||||||
|
int cmrg;
|
||||||
|
|
||||||
cmrg = mrg_2;
|
cmrg = mrg_2;
|
||||||
mrg_2 = mrg_1;
|
mrg_2 = mrg_1;
|
||||||
@ -217,8 +222,8 @@ rolop(opc) register opc; {
|
|||||||
badsyntax();
|
badsyntax();
|
||||||
}
|
}
|
||||||
|
|
||||||
incop(opc) register opc; {
|
void incop(int opc)
|
||||||
|
{
|
||||||
regsize(opc);
|
regsize(opc);
|
||||||
if ((opc&1) && mrg_1>=0300) {
|
if ((opc&1) && mrg_1>=0300) {
|
||||||
emit1(0100 | (opc&010) | (mrg_1&7));
|
emit1(0100 | (opc&010) | (mrg_1&7));
|
||||||
@ -228,8 +233,8 @@ incop(opc) register opc; {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
callop(opc) register opc; {
|
void callop(int opc)
|
||||||
|
{
|
||||||
regsize(1);
|
regsize(1);
|
||||||
if (mrg_1 & 040) {
|
if (mrg_1 & 040) {
|
||||||
if (opc == (040+(0351<<8))) {
|
if (opc == (040+(0351<<8))) {
|
||||||
@ -249,8 +254,8 @@ callop(opc) register opc; {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
xchg(opc) register opc; {
|
void xchg(int opc)
|
||||||
|
{
|
||||||
regsize(opc);
|
regsize(opc);
|
||||||
if (mrg_2 == 0300 || mrg_1 < 0300)
|
if (mrg_2 == 0300 || mrg_1 < 0300)
|
||||||
reverse();
|
reverse();
|
||||||
@ -262,8 +267,8 @@ xchg(opc) register opc; {
|
|||||||
badsyntax();
|
badsyntax();
|
||||||
}
|
}
|
||||||
|
|
||||||
test(opc) register opc; {
|
void test(int opc)
|
||||||
|
{
|
||||||
regsize(opc);
|
regsize(opc);
|
||||||
if ((mrg_1 & 040) || mrg_2 >= 0300)
|
if ((mrg_1 & 040) || mrg_2 >= 0300)
|
||||||
reverse();
|
reverse();
|
||||||
@ -288,8 +293,8 @@ test(opc) register opc; {
|
|||||||
badsyntax();
|
badsyntax();
|
||||||
}
|
}
|
||||||
|
|
||||||
mov(opc) register opc; {
|
void mov(int opc)
|
||||||
|
{
|
||||||
regsize(opc);
|
regsize(opc);
|
||||||
if (mrg_1 & 020) {
|
if (mrg_1 & 020) {
|
||||||
emit1(0216); ea_2((mrg_1&3)<<3);
|
emit1(0216); ea_2((mrg_1&3)<<3);
|
||||||
@ -334,8 +339,7 @@ mov(opc) register opc; {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
imul(opc)
|
void imul(int opc)
|
||||||
int opc;
|
|
||||||
{
|
{
|
||||||
regsize(opc);
|
regsize(opc);
|
||||||
if (exp_2.typ != S_ABS || ((mrg_2 & 040) == 0)) {
|
if (exp_2.typ != S_ABS || ((mrg_2 & 040) == 0)) {
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user