From cdce394b6c4fd85c53e015cf26f36deecddb4bd3 Mon Sep 17 00:00:00 2001
From: David Given <dg@cowlark.com>
Date: Wed, 22 May 2013 11:02:46 +0100
Subject: [PATCH] Generate ld rd, (rs) instructions properly.

--HG--
branch : dtrg-videocore
---
 mach/vc4/as/mach5.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mach/vc4/as/mach5.c b/mach/vc4/as/mach5.c
index f3671bf64..53ec3464c 100644
--- a/mach/vc4/as/mach5.c
+++ b/mach/vc4/as/mach5.c
@@ -254,7 +254,7 @@ void mem_instr(quad opcode, int cc, int rd, long offset, int rs)
 
 		if ((rs < 0x10) && (rd < 0x10) && (offset == 0))
 		{
-			emit2(B16(00001000,00000000) | (opcode<<8) | (rs<<4) | (rd<<4));
+			emit2(B16(00001000,00000000) | (opcode<<8) | (rs<<4) | (rd<<0));
 			return;
 		}