diff --git a/3rd_party/libdisasm/INTEL_BUGS b/3rd_party/libdisasm/INTEL_BUGS new file mode 100644 index 0000000..c80949c --- /dev/null +++ b/3rd_party/libdisasm/INTEL_BUGS @@ -0,0 +1,68 @@ +PMOVMSKB +Gd, Pq1H +PMOVMSKB +(66) +Gd, Vdq1H + +should be + +PMOVMSKB +Gd, Qq1H +PMOVMSKB +(66) +Gd, Wdq1H + +The instruction represented by this opcode expression does not support any +operand to be a memory location. + +MASKMOVQ +Pq, Pq1H +MASKMOVDQU +(66) +Vdq, Vdq1H + +should be + +MASKMOVQ +Pq, Pq1H +MASKMOVDQU +(66) +Vdq, Wdq1H + +MOVMSKPS +Gd, Vps1H +MOVMSKPD +(66) +Gd, Vpd1H + +should be + +MOVMSKPS +Gd, Wps1H +MOVMSKPD +(66) +Gd, Wpd1H + +The opcode table entries for LFS, LGS, and LSS + +L[FGS]S +Mp + +should be + +L[FGS]S +Gv,Mp + +MOVHLPS +Vps, Vps + +MOVLHPS +Vps, Vps + +should be + +MOVHLPS +Vps, Wps + +MOVLHPS +Vps, Wps diff --git a/3rd_party/libdisasm/LICENSE b/3rd_party/libdisasm/LICENSE new file mode 100644 index 0000000..c563828 --- /dev/null +++ b/3rd_party/libdisasm/LICENSE @@ -0,0 +1,137 @@ + + + + + The "Clarified Artistic License" + + Preamble + +The intent of this document is to state the conditions under which a +Package may be copied, such that the Copyright Holder maintains some +semblance of artistic control over the development of the package, +while giving the users of the package the right to use and distribute +the Package in a more-or-less customary fashion, plus the right to make +reasonable modifications. + +Definitions: + + "Package" refers to the collection of files distributed by the + Copyright Holder, and derivatives of that collection of files + created through textual modification. + + "Standard Version" refers to such a Package if it has not been + modified, or has been modified in accordance with the wishes + of the Copyright Holder as specified below. + + "Copyright Holder" is whoever is named in the copyright or + copyrights for the package. + + "You" is you, if you're thinking about copying or distributing + this Package. + + "Distribution fee" is a fee you charge for providing a copy of this + Package to another party. + + "Freely Available" means that no fee is charged for the right to use + the item, though there may be fees involved in handling the item. + +1. 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Aggregation of the Standard Version of the Package with a commercial +distribution is always permitted provided that the use of this Package is +embedded; that is, when no overt attempt is made to make this Package's +interfaces visible to the end user of the commercial distribution. +Such use shall not be construed as a distribution of this Package. + +9. The name of the Copyright Holder may not be used to endorse or promote +products derived from this software without specific prior written permission. + +10. THIS PACKAGE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + + The End diff --git a/3rd_party/libdisasm/NAMESPACE.TXT b/3rd_party/libdisasm/NAMESPACE.TXT new file mode 100644 index 0000000..8fbccf6 --- /dev/null +++ b/3rd_party/libdisasm/NAMESPACE.TXT @@ -0,0 +1,12 @@ + +The rewritten libdisasm code uses the following namespaces: + + + Prefix Namespace +---------------------------------------------------- + x86_ Global 'libdisasm' namespace + ia32_ Internal IA32 ISA namespace + ia64_ Internal IA64 ISA namespace + ix64_ Internal X86-64 ISA namespace + +Note that the 64-bit ISAs are not yet supported/written. diff --git a/3rd_party/libdisasm/README b/3rd_party/libdisasm/README new file mode 100644 index 0000000..aa7b6a8 --- /dev/null +++ b/3rd_party/libdisasm/README @@ -0,0 +1,2 @@ +This is a cut-up version of libdisasm originally from the bastard project http://bastard.sourceforge.net/ + diff --git a/3rd_party/libdisasm/TODO b/3rd_party/libdisasm/TODO new file mode 100644 index 0000000..148addf --- /dev/null +++ b/3rd_party/libdisasm/TODO @@ -0,0 +1,43 @@ +x86_format.c +------------ +intel: jmpf -> jmp, callf -> call +att: jmpf -> ljmp, callf -> lcall + +opcode table +------------ +finish typing instructions +fix flag clear/set/toggle types + +ix64 stuff +---------- +document output file formats in web page +features doc: register aliases, implicit operands, stack mods, +ring0 flags, eflags, cpu model/isa + +ia32_handle_* implementation + +fix operand 0F C2 +CMPPS + +* sysenter, sysexit as CALL types -- preceded by MSR writes +* SYSENTER/SYSEXIT stack : overwrites SS, ESP +* stos, cmps, scas, movs, ins, outs, lods -> OP_PTR +* OP_SIZE in implicit operands +* use OP_SIZE to choose reg sizes! + +DONE?? : +implicit operands: provide action ? +e.g. add/inc for stach, write, etc +replace table numbers in opcodes.dat with +#defines for table names + +replace 0 with INSN_INVALID [or maybe FF for imnvalid and 00 for Not Applicable */ +no wait that is only for prefix tables -- n/p + +if ( prefx) only use if insn != invalid + +these should cover all the wacky disasm exceptions + +for the rep one we can chet, match only a 0x90 + +todo: privilege | ring diff --git a/3rd_party/libdisasm/ia32_fixup.cpp b/3rd_party/libdisasm/ia32_fixup.cpp new file mode 100644 index 0000000..b82bf1d --- /dev/null +++ b/3rd_party/libdisasm/ia32_fixup.cpp @@ -0,0 +1,36 @@ +#include + +static const char * mem_fixup[256] = { + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 00 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 08 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 10 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 18 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 20 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 28 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 30 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 38 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 40 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 48 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 50 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 58 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 60 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 68 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 70 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 78 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 80 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 88 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 90 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 98 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* A0 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* A8 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* B0 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* B8 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* C0 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* C8 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* D0 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* D8 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* E0 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* E8 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* F0 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL /* F8 */ +}; diff --git a/3rd_party/libdisasm/ia32_opcode.dat b/3rd_party/libdisasm/ia32_opcode.dat new file mode 100644 index 0000000..af3965c --- /dev/null +++ b/3rd_party/libdisasm/ia32_opcode.dat @@ -0,0 +1,3206 @@ +# IA32 OPCODE MAP +# Tab-delimited file of Intel Opcode Tables + +# Each table begins with the line +# ^TABLE $NAME\tindex $INDEX\ttype $TYPE\tshift $SHIFT\tmask $MASK\tminlim $MIN\tmaxlim $MAX\tname $NAME +# and ends with the line +# END TABLE + +# Each instruction is formed of the line +# ^INSN $TABLE\t$MFLAG\t$DFLAG\t$SFLAG\t$AFLAG\t$CPU +# \t$MNEM\t$DEST\t$SRC\t$AUX\t$EFLAGS\t$COMMENT +# Note that this is a single line: the newline in the above is for clarity. +# The fields are: +# TABLE : index of next lookup table if appropriate +# MFLAG : mnemonic (instruction) flags +# DFLAG : destination (1st) operand flags +# SFLAG : source (2nd) operand flags +# AFLAG : aux (3rd) operand flags +# CPU : minimum CPU version supporting this insn +# MNEM : ASCII mnemonic +# DEST : hard-coded destination operand +# SRC : hard-coded source operand +# AUX : hard-coded aux operand +# EFLAGS : cpu flags effected by instruction +# IMPLICIT: implicit operands +# CMT : comment : usually the byte or index in the table + + +# Obviously blank lines and lines beginning with '#' are ignored. +PREFIX ia32 + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_Main tbl_opcode shift 0 mask 255 minlim 0 maxlim 255 "One-byte Opcodes" +#______________________________________________________________________________ +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_ADD ADDRMETH_G | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_ADD ADDRMETH_G | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_ADD ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_ADD ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 0 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RS | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 0 0 0 0 33 +INSN 0 INS_OR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_OR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_OR ADDRMETH_G | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_OR ADDRMETH_G | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_OR ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_OR ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 1 0 0 0 33 +INSN idx_0F 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_ADD ADDRMETH_G | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_ADD ADDRMETH_G | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_ADD ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_ADD ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 2 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RS | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 2 0 0 0 33 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_SUB ADDRMETH_G | OPTYPE_b | OP_W | OP_SIGNED | OP_R ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_SUB ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_SUB ADDRMETH_RR | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_SUB ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 3 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RS | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 3 0 0 0 33 +INSN 0 INS_AND ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_AND ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_AND ADDRMETH_G | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_AND ADDRMETH_G | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_AND ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_AND ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_NOTE_PREFIX | PREFIX_ES ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_BCDCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "daa" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_CARRY|INS_SET_PARITY|INS_TEST_CARRY 12 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SUB ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SUB ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SUB ADDRMETH_RR | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SUB ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_NOTE_PREFIX | PREFIX_CS | PREFIX_NOTTAKEN ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_BCDCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "das" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_CARRY|INS_SET_PARITY|INS_TEST_CARRY 0 +INSN 0 INS_XOR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_XOR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_XOR ADDRMETH_G | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_XOR ADDRMETH_G | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_XOR ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_XOR ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_NOTE_PREFIX | PREFIX_SS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_BCDCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "aaa" 0 0 0 INS_SET_CARRY 1 +INSN 0 INS_CMP ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_CMP ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_CMP ADDRMETH_G | OPTYPE_b | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_CMP ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_CMP ADDRMETH_RR | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_CMP ADDRMETH_RR | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_NOTE_PREFIX | PREFIX_DS | PREFIX_TAKEN ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_BCDCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "aas" 0 0 0 INS_SET_CARRY 0 +INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 1 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 2 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 3 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 4 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 5 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 6 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 7 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 1 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 2 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 3 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 4 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 5 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 6 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 7 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 0 0 0 0 33 +INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 1 0 0 0 33 +INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 2 0 0 0 33 +INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 3 0 0 0 33 +INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 4 0 0 0 33 +INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 5 0 0 0 33 +INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 6 0 0 0 33 +INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 7 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 0 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 1 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 2 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 3 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 4 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 5 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 6 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 7 0 0 0 33 +INSN 0 INS_PUSHREGS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "pushad" 0 0 0 0 36 +INSN 0 INS_POPREGS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "popad" 0 0 0 0 34 +INSN 0 INS_BOUNDS ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_M | OPTYPE_a | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "bound" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_R ADDRMETH_G | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "arpl" 0 0 0 INS_SET_ZERO 0 +INSN 0 INS_NOTE_PREFIX | PREFIX_FS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_NOTE_PREFIX | PREFIX_GS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_66 INS_NOTE_PREFIX | PREFIX_OP_SIZE ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_NOTE_PREFIX | PREFIX_ADDR_SIZE ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_PUSH ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 0 0 0 0 33 +INSN 0 INS_MUL ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R cpu_80386 | isa_GP "imul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 0 +INSN 0 INS_PUSH ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 0 0 0 0 33 +INSN 0 INS_MUL ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R cpu_80386 | isa_GP "imul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 0 +INSN 0 INS_IN ADDRMETH_Y | OPTYPE_b | OP_W ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "insb" 0 2 0 0 0 +INSN 0 INS_IN ADDRMETH_Y | OPTYPE_v | OP_W ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "insd" 0 2 0 0 0 +INSN 0 INS_OUT ADDRMETH_RR | OPTYPE_b | OP_R ADDRMETH_X | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "outsb" 2 0 0 0 0 +INSN 0 INS_OUT ADDRMETH_RR | OPTYPE_v | OP_R ADDRMETH_X | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "outsb" 2 0 0 0 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jo" 0 0 0 INS_TEST_OFLOW 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jno" 0 0 0 INS_TEST_NOFLOW 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jc" 0 0 0 INS_TEST_CARRY 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jnc" 0 0 0 INS_TEST_NCARRY 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jz" 0 0 0 INS_TEST_ZERO 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jnz" 0 0 0 INS_TEST_NZERO 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jbe" 0 0 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "ja" 0 0 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "js" 0 0 0 INS_TEST_SIGN 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jns" 0 0 0 INS_TEST_NSIGN 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jpe" 0 0 0 INS_TEST_PARITY 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jpo" 0 0 0 INS_TEST_NPARITY 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jl" 0 0 0 INS_TEST_SFNEOF 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jge" 0 0 0 INS_TEST_SFEQOF 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jle" 0 0 0 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jg" 0 0 0 INS_TEST_NZERO|INS_TEST_SFEQOF 0 +INSN idx_80 0 ADDRMETH_E | OPTYPE_b ADDRMETH_I | OPTYPE_b ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_81 0 ADDRMETH_E | OPTYPE_v ADDRMETH_I | OPTYPE_v ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_82 0 ADDRMETH_E | OPTYPE_b ADDRMETH_I | OPTYPE_b ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_83 0 ADDRMETH_E | OPTYPE_v ADDRMETH_I | OPTYPE_b ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_TEST ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_TEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_XCHG ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 0 0 0 0 +INSN 0 INS_XCHG ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_E | OPTYPE_b | OP_W ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_E | OPTYPE_v | OP_W ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_b | OP_W ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_E | OPTYPE_w | OP_W ADDRMETH_S | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_m | OP_R ARG_NONE cpu_80386 | isa_GP "lea" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_S | OPTYPE_w | OP_W ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_POP ADDRMETH_E | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 0 0 0 0 33 +INSN 0 INS_NOP ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "nop" 0 0 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 1 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 2 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 3 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 4 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 5 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 6 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 7 0 0 0 +INSN 0 INS_SZCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "cwde" 0 0 0 0 5 +INSN 0 INS_SZCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "cdq" 0 0 0 0 11 +INSN 0 INS_CALL ADDRMETH_A | OPTYPE_p | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "callf" 0 0 0 0 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "wait" 0 0 0 0 0 +INSN 0 INS_PUSHFLAGS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "pushfd" 0 0 0 0 37 +INSN 0 INS_POPFLAGS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "popfd" 0 0 0 0 35 +INSN 0 INS_MOV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "sahf" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 43 +INSN 0 INS_MOV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "lahf" 0 0 0 0 24 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_O | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_O | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_O | OPTYPE_b | OP_W ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_O | OPTYPE_v | OP_W ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_STRMOV ADDRMETH_Y | OPTYPE_b | OP_W ADDRMETH_X | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "movsb" 0 0 0 0 0 +INSN 0 INS_STRMOV ADDRMETH_Y | OPTYPE_v | OP_W ADDRMETH_X | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "movsd" 0 0 0 0 0 +INSN 0 INS_STRCMP ADDRMETH_Y | OPTYPE_b | OP_R ADDRMETH_X | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "cmpsb" 0 0 0 0 0 +INSN 0 INS_STRCMP ADDRMETH_X | OPTYPE_v | OP_R ADDRMETH_Y | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "cmpsd" 0 0 0 0 0 +INSN 0 INS_TEST ADDRMETH_RR | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_TEST ADDRMETH_RR | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_STRSTOR ADDRMETH_Y | OPTYPE_b | OP_W ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "stosb" 0 0 0 0 0 +INSN 0 INS_STRSTOR ADDRMETH_Y | OPTYPE_v | OP_W ADDRMETH_RR | OPTYPE_v |OP_R ARG_NONE cpu_80386 | isa_GP "stosd" 0 0 0 0 0 +INSN 0 INS_STRLOAD ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_X| OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "lodsb" 0 0 0 0 0 +INSN 0 INS_STRLOAD ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_X| OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "lodsd" 0 0 0 0 0 +INSN 0 INS_STRCMP ADDRMETH_RR | OPTYPE_b | OP_R ADDRMETH_Y | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "scasb" 0 0 0 0 0 +INSN 0 INS_STRCMP ADDRMETH_RR | OPTYPE_v | OP_R ADDRMETH_Y | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "scasd" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 1 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 2 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 3 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 4 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 5 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 6 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 7 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 1 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 2 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 3 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 4 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 5 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 6 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 7 0 0 0 0 +INSN idx_C0 0 ADDRMETH_E | OPTYPE_b ADDRMETH_I | OPTYPE_b ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_C1 0 ADDRMETH_E | OPTYPE_v ADDRMETH_I | OPTYPE_b ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_RET ADDRMETH_I | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "ret" 0 0 0 0 3 +INSN 0 INS_RET ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "ret" 0 0 0 0 3 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_p | OP_R ARG_NONE cpu_80386 | isa_GP "les" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_p | OP_R ARG_NONE cpu_80386 | isa_GP "lds" 0 0 0 0 0 +INSN idx_C6 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_C7 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_ENTER ADDRMETH_I | OPTYPE_w | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "enter" 0 0 0 0 15 +INSN 0 INS_LEAVE ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "leave" 0 0 0 0 26 +INSN 0 INS_RET ADDRMETH_I | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "retf" 0 0 0 0 3 +INSN 0 INS_RET ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "retf" 0 0 0 0 3 +INSN 0 INS_DEBUG ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "int3" 0 0 0 0 0 +INSN 0 INS_TRAP ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "int" 0 0 0 0 0 +INSN 0 INS_OFLOW ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "into" 0 0 0 INS_TEST_OFLOW 0 +INSN 0 INS_TRET ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "iret" 0 0 0 INS_SET_ALL|INS_SET_DIR 0 +INSN idx_D0 0 ADDRMETH_E | OPTYPE_b ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 1 0 0 0 +INSN idx_D1 0 ADDRMETH_E | OPTYPE_v ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 1 0 0 0 +INSN idx_D2 0 ADDRMETH_E | OPTYPE_b ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 1 0 0 0 +INSN idx_D3 0 ADDRMETH_E | OPTYPE_v ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 1 0 0 0 +INSN 0 INS_BCDCONV ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "aam" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_BCDCONV ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "aad" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 2 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_XLAT ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "xlat" 0 0 0 0 53 +INSN idx_D8 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_D9 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_DA 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_DB 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_DC 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_DD 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_DE 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_DF 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "loopnz" 0 0 0 INS_TEST_NZERO 31 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "loopz" 0 0 0 INS_TEST_ZERO 31 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "loop" 0 0 0 0 31 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jcxz" 0 0 0 0 31 +INSN 0 INS_IN ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "in" 0 0 0 0 0 +INSN 0 INS_IN ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "in" 0 0 0 0 0 +INSN 0 INS_OUT ADDRMETH_I | OPTYPE_b | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "out" 0 0 0 0 0 +INSN 0 INS_OUT ADDRMETH_I | OPTYPE_b | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "out" 0 0 0 0 0 +INSN 0 INS_CALL ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "call" 0 0 0 0 3 +INSN 0 INS_BRANCH ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jmp" 0 0 0 0 0 +INSN 0 INS_BRANCH ADDRMETH_A | OPTYPE_p | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jmpf" 0 0 0 0 0 +INSN 0 INS_BRANCH ADDRMETH_J | OPTYPE_b | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jmp" 0 0 0 0 0 +INSN 0 INS_IN ADDRMETH_RR | OPTYPE_b| OP_W ADDRMETH_RR | OPTYPE_w| OP_R ARG_NONE cpu_80386 | isa_GP "in" 0 2 0 0 0 +INSN 0 INS_IN ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_RR | OPTYPE_w| OP_R ARG_NONE cpu_80386 | isa_GP "in" 0 2 0 0 0 +INSN 0 INS_OUT ADDRMETH_RR | OPTYPE_w| OP_R ADDRMETH_RR | OPTYPE_b| OP_R ARG_NONE cpu_80386 | isa_GP "out" 2 0 0 0 0 +INSN 0 INS_OUT ADDRMETH_RR | OPTYPE_w| OP_R ADDRMETH_RR | OPTYPE_v| OP_R ARG_NONE cpu_80386 | isa_GP "out" 2 0 0 0 0 +INSN 0 INS_NOTE_PREFIX | PREFIX_LOCK ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_F2 INS_NOTE_PREFIX | PREFIX_REPNZ ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_F3 INS_NOTE_PREFIX | PREFIX_REPZ ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_HALT ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "hlt" 0 0 0 0 0 +INSN 0 INS_TOGCF ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "cmc" 0 0 0 INS_SET_CARRY 0 +INSN idx_F6 0 ADDRMETH_E | OPTYPE_b ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_F7 0 ADDRMETH_E | OPTYPE_v ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_CLEARCF ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "clc" 0 0 0 INS_SET_NCARRY 0 +INSN 0 INS_SETCF ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "stc" 0 0 0 INS_SET_CARRY 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "cli" 0 0 0 0 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "sti" 0 0 0 0 0 +INSN 0 INS_CLEARDF ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "cld" 0 0 0 INS_SET_NDIR 0 +INSN 0 INS_SETDF ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "std" 0 0 0 INS_SET_DIR 0 +INSN idx_FE 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_FF 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_66 tbl_prefix shift 0 mask 255 minlim 15 maxlim 15 "SIMD 66 one-byte Opcodes" +#______________________________________________________________________________ +INSN idx_660F 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +# Table truncated +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_F2 tbl_prefix shift 0 mask 255 minlim 15 maxlim 15 "SIMD F2 one-byte Opcodes" +#______________________________________________________________________________ +INSN idx_F20F 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +# Table truncated +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +# TODO +# lookup: if ( >= minlin && <= maxlim ) idx -= minlim; +# 0x90 == 1001 0000 ; val >> 4 ; 1000 - 1001 +TABLE tbl_F3 tbl_prefix shift 0 mask 255 minlim 15 maxlim 144 "SIMD F3 one-byte Opcodes" +#______________________________________________________________________________ +INSN idx_F30F 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "pause" 0 0 0 0 0 +# Table truncated +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0F tbl_opcode shift 0 mask 255 minlim 0 maxlim 255 "Two-byte Opcodes" +#______________________________________________________________________________ +INSN idx_0F00 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN idx_0F01 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "lar" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "lsl" 0 0 0 INS_SET_ZERO 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_CLTS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "clts" 0 0 0 0 6 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80486 | isa_GP "invd" 0 0 0 0 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80486 | isa_GP "wbinvd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ARG_NONE ARG_NONE ARG_NONE cpu_PENTPRO | isa_GP "ud2" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "prefetchw" 0 0 0 0 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "femms" 0 0 0 0 0 +INSN idx_0F0F INS_NOTE_SUFFIX ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movups" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_W | OPTYPE_ps | OP_W ADDRMETH_V | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movups" 0 0 0 0 0 +INSN idx_0F12 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movlps" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "unpcklps" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "unpckhps" 0 0 0 0 0 +INSN idx_0F16 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_q | OP_W ADDRMETH_V | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movhps" 0 0 0 0 0 +INSN idx_0F18 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_R | OPTYPE_d | OP_W ADDRMETH_C | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_R | OPTYPE_d | OP_W ADDRMETH_D | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_C | OPTYPE_d | OP_W ADDRMETH_R | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_D | OPTYPE_d | OP_W ADDRMETH_R | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_R | OPTYPE_d | OP_W ADDRMETH_T | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_T | OPTYPE_d | OP_W ADDRMETH_R | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movaps" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_W | OPTYPE_ps | OP_W ADDRMETH_V | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movaps" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "cvtpi2ps" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_W | OPTYPE_ps | OP_W ADDRMETH_V | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movntps" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "cvttps2pi" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "cvtps2pi" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ss | OP_W ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "ucomiss" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ss | OP_W ARG_NONE cpu_PENTIUM2 | isa_GP "comiss" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "wrmsr" 0 0 0 0 52 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "rdtsc" 0 0 0 0 40 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "rdmsr" 0 0 0 0 38 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTPRO | isa_GP "rdpmc" 0 0 0 0 39 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "sysenter" 0 0 0 0 50 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "sysexit" 0 0 0 0 51 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovo" 0 0 0 INS_TEST_OFLOW 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovno" 0 0 0 INS_TEST_NOFLOW 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovc" 0 0 0 INS_TEST_CARRY 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovnc" 0 0 0 INS_TEST_NCARRY 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovz" 0 0 0 INS_TEST_ZERO 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovnz" 0 0 0 INS_TEST_NZERO 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovbe" 0 0 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmova" 0 0 0 INS_TEST_NZERO|INS_TEST_NCARRY 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovs" 0 0 0 INS_TEST_SIGN 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovns" 0 0 0 INS_TEST_NSIGN 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovp" 0 0 0 INS_TEST_PARITY 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovnp" 0 0 0 INS_TEST_NPARITY 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovl" 0 0 0 INS_TEST_SFNEOF 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovge" 0 0 0 INS_TEST_SFEQOF 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovle" 0 0 0 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 0 +INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovg" 0 0 0 INS_TEST_NZERO|INS_TEST_SFEQOF 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_d | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movmskps" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "sqrtps" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "rsqrtps" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "rcpps" 0 0 0 0 0 +INSN 0 INS_AND ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "andps" 0 0 0 0 0 +INSN 0 INS_AND ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "andnps" 0 0 0 0 0 +INSN 0 INS_OR ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "orps" 0 0 0 0 0 +INSN 0 INS_XOR ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "xorps" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "addps" 0 0 0 0 0 +INSN 0 INS_MUL ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "mulps" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_pd ADDRMETH_W | OPTYPE_q ARG_NONE cpu_PENTIUM4 | isa_GP "cvtps2pd" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtdq2ps" 0 0 0 0 0 +INSN 0 INS_SUB ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "subps" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "minps" 0 0 0 0 0 +INSN 0 INS_DIV ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "divps" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "maxps" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpcklbw" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpcklwd" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpckldq" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "packsswb" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpgtb" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpgtw" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpgtd" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "packuswb" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpckhbw" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpckhwd" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpckhdq" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "packssdw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_P | OPTYPE_d | OP_W ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "movd" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "movq" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM2 | isa_GP "pshufw" 0 0 0 0 0 +INSN idx_0F71 0 ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "" 0 0 0 0 0 +INSN idx_0F72 0 ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "" 0 0 0 0 0 +INSN idx_0F73 0 ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpeqb" 0 0 0 0 0 +INSN 0 INS_CMP ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpeqw" 0 0 0 0 0 +INSN 0 INS_CMP ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpeqd" 0 0 0 0 0 +INSN 0 INS_OTHER ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "emms" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_E | OPTYPE_d | OP_W ADDRMETH_P | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "movd" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_Q | OPTYPE_q | OP_W ADDRMETH_P | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "movq" 0 0 0 0 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jo" 0 0 0 INS_TEST_OFLOW 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jno" 0 0 0 INS_TEST_NOFLOW 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jc" 0 0 0 INS_TEST_CARRY 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jnc" 0 0 0 INS_TEST_NCARRY 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jz" 0 0 0 INS_TEST_ZERO 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jnz" 0 0 0 INS_TEST_NZERO 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jbe" 0 0 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "ja" 0 0 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "js" 0 0 0 INS_TEST_SIGN 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jns" 0 0 0 INS_TEST_NSIGN 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jpe" 0 0 0 INS_TEST_PARITY 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jpo" 0 0 0 INS_TEST_NPARITY 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jl" 0 0 0 INS_TEST_SFNEOF 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jge" 0 0 0 INS_TEST_SFEQOF 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jle" 0 0 0 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 0 +INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jg" 0 0 0 INS_TEST_NZERO|INS_TEST_SFEQOF 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "seto" 0 0 0 INS_TEST_OFLOW 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setno" 0 0 0 INS_TEST_OFLOW 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setc" 0 0 0 INS_TEST_CARRY 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setnc" 0 0 0 INS_TEST_NCARRY 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setz" 0 0 0 INS_TEST_ZERO 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setnz" 0 0 0 INS_TEST_NZERO 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setbe" 0 0 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "seta" 0 0 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "sets" 0 0 0 INS_TEST_SIGN 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setns" 0 0 0 INS_TEST_NSIGN 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setpe" 0 0 0 INS_TEST_PARITY 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setpo" 0 0 0 INS_TEST_NPARITY 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setl" 0 0 0 INS_TEST_SFNEOF 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setge" 0 0 0 INS_TEST_SFEQOF 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setle" 0 0 0 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 0 +INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setg" 0 0 0 INS_TEST_NZERO|INS_TEST_SFEQOF 0 +INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 4 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RS | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 4 0 0 0 33 +INSN 0 INS_CPUID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "cpuid" 0 0 0 0 10 +INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "bt" 0 0 0 INS_SET_CARRY 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_80386 | isa_GP "shld" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_I | OP_R | OPTYPE_b | ADDRMETH_RR cpu_80386 | isa_GP "shld" 0 0 1 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 5 0 0 0 33 +INSN 0 INS_POP ADDRMETH_RS | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 5 0 0 0 33 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "rsm" 0 0 0 INS_SET_ALL|INS_SET_DIR 42 +INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "bts" 0 0 0 INS_SET_CARRY 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_80386 | isa_GP "shrd" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_RR | OP_R | OPTYPE_b cpu_80386 | isa_GP "shrd" 0 0 1 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN idx_0FAE 0 ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_MUL ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "imul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY +INSN 0 INS_XCHGCC ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_W ARG_NONE cpu_80486 | isa_GP "cmpxchg" 0 0 0 INS_SET_ALL 8 +INSN 0 INS_XCHGCC ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_W ARG_NONE cpu_80486 | isa_GP "cmpxchg" 0 0 0 INS_SET_ALL 7 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_p | OP_W ARG_NONE cpu_80386 | isa_GP "lss" 0 0 0 0 0 +INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "btr" 0 0 0 INS_SET_CARRY 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_p | OP_W ARG_NONE cpu_80386 | isa_GP "lfs" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_p | OP_W ARG_NONE cpu_80386 | isa_GP "lgs" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "movzx" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "movzx" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "ud1" 0 0 0 0 0 +INSN idx_0FBA 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "btc" 0 0 0 INS_SET_CARRY 0 +INSN 0 INS_BITTEST ADDRMETH_G | OPTYPE_v | OP_R | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "bsf" 0 0 0 INS_SET_ZERO 0 +INSN 0 INS_BITTEST ADDRMETH_G | OPTYPE_v | OP_R | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "bsr" 0 0 0 INS_SET_ZERO 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "movsx" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "movsx" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_W ARG_NONE cpu_80486 | isa_GP "xadd" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "xadd" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_CMP ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "cmpps" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_M | OPTYPE_d | OP_W ADDRMETH_G | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movnti" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_E | OPTYPE_w | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM2 | isa_GP "pinsrw" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_G | OPTYPE_d | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM2 | isa_GP "pextrw" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM2 | isa_GP "shufps" 0 0 0 0 0 +INSN 0 INS_XCHGCC ADDRMETH_M | OPTYPE_q | OP_R | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "cmpxchg8b" 0 0 0 0 9 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 0 0 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 1 0 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 2 0 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 3 0 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 4 0 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 5 0 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 6 0 0 0 0 +INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 7 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlw" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrld" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlq" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_R | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddq" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pmullw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_G | OPTYPE_d | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pmovmskb" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubusb" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubusw" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pminub" 0 0 0 0 0 +INSN 0 INS_AND ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pand" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddusb" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddusw" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pmaxub" 0 0 0 0 0 +INSN 0 INS_AND ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pandn" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pavgb" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psraw" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrad" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pavgw" 0 0 0 0 0 +INSN 0 INS_MUL ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pmulhuw" 0 0 0 0 0 +INSN 0 INS_MUL ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pmulhw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_W | OPTYPE_q | OP_W ADDRMETH_V | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movntq" 0 0 0 0 0 +INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubsb" 0 0 0 0 0 +INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubsw" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pminsw" 0 0 0 0 0 +INSN 0 INS_OR ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "por" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddsb" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddsw" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pmaxsw" 0 0 0 0 0 +INSN 0 INS_XOR ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pxor" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllw" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pslld" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllq" 0 0 0 0 0 +INSN 0 INS_MUL ADDRMETH_P | OPTYPE_q | OP_R | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmuludq" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pmaddwd" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "psadbw" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_P | OPTYPE_pi | OP_W ADDRMETH_Q | OPTYPE_pi | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "maskmovq" 0 0 0 0 0 +INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubb" 0 0 0 0 0 +INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubw" 0 0 0 0 0 +INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubd" 0 0 0 0 0 +INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_R | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubq" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddb" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddw" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_660F tbl_prefix shift 0 mask 255 minlim 16 maxlim 255 "SIMD 66 Two-byte Opcodes" +#______________________________________________________________________________ +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movupd" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_W | OPTYPE_pd | OP_R ADDRMETH_V | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movupd" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_R ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movlpd" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_M | OPTYPE_q | OP_R ADDRMETH_V | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movlpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "unpcklpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "unpckhpd" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_R ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movhpd" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_M | OPTYPE_q | OP_R ADDRMETH_V | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movhpd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movapd" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_W | OPTYPE_pd | OP_R ADDRMETH_V | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movapd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtpi2pd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_M | OPTYPE_pd | OP_R ADDRMETH_V | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movntpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_P | OPTYPE_q | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvttpd2pi" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_P | OPTYPE_q | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtpd2pi" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "ucomisd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "comisd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movmskpd" 0 0 0 0 0 +INSN 0 INS_FSQRT ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "sqrtpd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_AND ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "andpd" 0 0 0 0 0 +INSN 0 INS_AND ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "andnpd" 0 0 0 0 0 +INSN 0 INS_OR ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "orpd" 0 0 0 0 0 +INSN 0 INS_XOR ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "xorpd" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "addpd" 0 0 0 0 0 +INSN 0 INS_MUL ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "mulpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtpd2ps" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtps2dq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "subpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "minpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "divpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "maxpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpcklbw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpcklwd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpckldq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "packsswb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpgtb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpgtw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpgtd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "packuswb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_Q | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpckhbw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_Q | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpckhwd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_Q | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpckhdq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_Q | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "packssdw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpcklqdq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpckhqdq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_d | OP_R ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movdqa" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "pshufd" 0 0 0 0 0 +INSN idx_660F71 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN idx_660F72 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN idx_660F73 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpeqb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpeqw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpeqd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "haddpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "hsubpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_E | OPTYPE_d | OP_R ADDRMETH_V | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_W | OPTYPE_dq | OP_R ADDRMETH_V | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movdqa" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "cmppd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_w | OP_R ADDRMETH_E | OPTYPE_w | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "pinsrw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_w | OP_R ADDRMETH_W | OPTYPE_w | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "pextrw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "shufpd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "addsubpd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psrlw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psrld" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psrlq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmullw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_W | OPTYPE_q | OP_R ADDRMETH_V | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmovmskb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubusb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubusw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pminub" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pand" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddusb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddusw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmaxub" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pandn" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pavgb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psraw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psrad" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pavgw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmulhuw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmulhw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvttpd2dq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_M | OPTYPE_dq | OP_R ADDRMETH_V | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movntdq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubsb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubsw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pminsw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "por" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddsb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddsw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmaxsw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pxor" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psllw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pslld" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psllq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmuludq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmaddwd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psadbw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "maskmovdqu" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddb" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddw" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_F20F tbl_prefix shift 0 mask 255 minlim 16 maxlim 255 "SIMD F2 Two-byte Opcodes" +#______________________________________________________________________________ +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movsd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_W | OPTYPE_sd | OP_R ADDRMETH_V | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movsd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_q | OP_R ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movddup" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtsi2sd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvttsd2si" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtsd2si" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "sqrtsd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "addsd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "mulsd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtsd2ss" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "subsd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "minsd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "divsd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "maxsd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "pshuflw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "haddps" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "hsubps" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "cmpsd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "addsubps" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_P | OPTYPE_q | OP_R ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movdq2q" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtpd2dq" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_M | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "lddqu" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_F30F tbl_prefix shift 0 mask 255 minlim 16 maxlim 255 "SIMD F3 Two-byte Opcodes" +#______________________________________________________________________________ +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movss" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_W | OPTYPE_ss | OP_R ADDRMETH_V | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movss" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movsldup" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movshdup" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtsi2ss" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvttss2si" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtss2si" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "sqrtss" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "rsqrtss" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "rcpss" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "addss" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "mulss" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtss2sd" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvttps2dq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "subss" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "minss" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "divss" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "maxss" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movdqu" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "pshufhw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_q | OP_R ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movq" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_W | OPTYPE_dq | OP_R ADDRMETH_V | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movdqu" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "cmpss" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movq2dq" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtdq2pd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0F00 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 6" +#______________________________________________________________________________ +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sldt" 0 0 0 0 46 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "str" 0 0 0 0 49 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lldt" 0 0 0 0 29 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "ltr" 0 0 0 0 32 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "verr" 0 0 0 INS_SET_ZERO 0 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "verw" 0 0 0 INS_SET_ZERO 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0F01 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 7" +#______________________________________________________________________________ +# Mod 00 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sgdt" 0 0 0 0 44 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sidt" 0 0 0 0 45 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lgdt" 0 0 0 0 27 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lidt" 0 0 0 0 28 +INSN 0 INS_SMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "smsw" 0 0 0 0 47 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_LMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lmsw" 0 0 0 0 30 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "invlpg" 0 0 0 0 0 +# Mod 01 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sgdt" 0 0 0 0 44 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sidt" 0 0 0 0 45 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lgdt" 0 0 0 0 27 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lidt" 0 0 0 0 28 +INSN 0 INS_SMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "smsw" 0 0 0 0 47 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_LMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lmsw" 0 0 0 0 30 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "invlpg" 0 0 0 0 0 +# Mod 10 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sgdt" 0 0 0 0 44 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sidt" 0 0 0 0 45 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lgdt" 0 0 0 0 27 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lidt" 0 0 0 0 28 +INSN 0 INS_SMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "smsw" 0 0 0 0 47 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_LMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lmsw" 0 0 0 0 30 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "invlpg" 0 0 0 0 0 +# Mod 11 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN idx_0F0111 0 ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_SMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "smsw" 0 0 0 0 47 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_LMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lmsw" 0 0 0 0 30 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +# This table is a weird one. In addition to the Reg field *and* the Mod field +# of the ModR/M byte being used as an opcode extension, this insn uses the +# R/M field as well. +TABLE tbl_0F0111 tbl_ext_ext shift 0 mask 1 minlim 0 maxlim 1 "Monitor/MWait opcode" +#______________________________________________________________________________ +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "monitor" 0 0 0 0 54 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "mwait" 0 0 0 0 55 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +# TODO +TABLE tbl_0F12 tbl_extension shift 6 mask 3 minlim 0 maxlim 3 "Movlps Opcode" +# A semi-weird table. This insn mnemonic changes when the Mod field of the +# ModR/M byte denotes a register. +#______________________________________________________________________________ +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movlps" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movlps" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movlps" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_R | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movhlps" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +# TODO +TABLE tbl_0F16 tbl_extension shift 6 mask 3 minlim 0 maxlim 3 "Movhps Opcode" +# Insn mnemonic changes when the Mod field denotes a register. +#______________________________________________________________________________ +INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movhps" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movhps" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movhps" 0 0 0 0 0 +INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_R | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movlhps" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0F18 tbl_extension shift 3 mask 31 minlim 0 maxlim 19 "Group 16" +#______________________________________________________________________________ +# Mod 00 +INSN 0 INS_SYSTEM OP_W | OPTYPE_b | ADDRMETH_M ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetchnta" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht0" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht1" 1 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht2" 2 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 10 +INSN 0 INS_SYSTEM OP_W | OPTYPE_b | ADDRMETH_M ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetchnta" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht0" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht1" 1 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht2" 2 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 01 +INSN 0 INS_SYSTEM OP_W | OPTYPE_b | ADDRMETH_M ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetchnta" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht0" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht1" 1 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht2" 2 0 0 0 0 +# table truncated +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0F71 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 12" +#______________________________________________________________________________ +# Mod 00 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 01 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 10 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 11 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psraw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_660F71 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 12 SSE" +#______________________________________________________________________________ +# Mod 00 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 01 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 10 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 11 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psraw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0F72 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 13" +#______________________________________________________________________________ +# Mod 00 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 01 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 10 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 11 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrld" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrad" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pslld" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +#______________________________________________________________________________ +TABLE tbl_660F72 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 13 SSE" +# Mod 00 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 01 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 10 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 11 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrld" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrad" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pslld" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0F73 tbl_extension shift 0 mask 0 minlim 0 maxlim 0 "Group 14" +#______________________________________________________________________________ +# Mod 00 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 01 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 10 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 11 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlq" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllq" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +# TODO: last 2 opcodes +#______________________________________________________________________________ +TABLE tbl_660F73 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 14 SSE" +#______________________________________________________________________________ +# Mod 00 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 01 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 10 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 11 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlq" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrldq" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllq" 0 0 0 0 0 +INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pslldq" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +#TODO: fill in opcodes +TABLE tbl_0FAE tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 15" +#______________________________________________________________________________ +# Mod 00 +INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxsave" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_R ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxrstor" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE ARG_NONE cpu_PENTIUM2 "ldmxcsr" 0 0 0 0 25 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 "stmxcsr" 0 0 0 0 48 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "clflush" 0 0 0 0 0 +# Mod 01 +INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxsave" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_R ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxrstor" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE ARG_NONE cpu_PENTIUM2 "ldmxcsr" 0 0 0 0 25 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 "stmxcsr" 0 0 0 0 48 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "clflush" 0 0 0 0 0 +# Mod 10 +INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxsave" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_R ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxrstor" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE ARG_NONE cpu_PENTIUM2 "ldmxcsr" 0 0 0 0 25 +INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 "stmxcsr" 0 0 0 0 48 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "clflush" 0 0 0 0 0 +# Mod 11 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE 0 "lfence" 0 0 0 0 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE 0 "mfence" 0 0 0 0 0 +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE 0 "sfence" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0FBA tbl_extension shift 3 mask 7 minlim 4 maxlim 7 "Group 8" +#______________________________________________________________________________ +INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "bt" 0 0 0 INS_SET_CARRY 0 +INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "bts" 0 0 0 INS_SET_CARRY 0 +INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "btr" 0 0 0 INS_SET_CARRY 0 +INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "btc" 0 0 0 INS_SET_CARRY 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0FC7 tbl_extension shift 3 mask 31 minlim 0 maxlim 17 "Group 9" +#______________________________________________________________________________ +# Mod 00 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_XCHGCC ADDRMETH_M | OPTYPE_q | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "cmpxch8b" 0 0 0 0 9 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 01 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_XCHGCC ADDRMETH_M | OPTYPE_q | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "cmpxch8b" 0 0 0 0 9 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +# Mod 10 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0 +INSN 0 INS_XCHGCC ADDRMETH_M | OPTYPE_q | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "cmpxch8b" 0 0 0 0 9 +# Table truncated +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0FB9 tbl_extension shift 3 mask 7 minlim 0 maxlim 0 "Group 10" +#______________________________________________________________________________ +INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE 0 "fxsave" 0 0 0 0 0 +# Table truncated +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_C6 tbl_extension shift 3 mask 7 minlim 0 maxlim 0 "Group 11a" +#______________________________________________________________________________ +INSN 0 INS_MOV ADDRMETH_E | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +# Table truncated +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_C7 tbl_extension shift 3 mask 7 minlim 0 maxlim 0 "Group 11b" +INSN 0 INS_MOV ADDRMETH_E | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0 +# Table truncated +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_80 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 1a" +#______________________________________________________________________________ +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_OR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_AND ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_XOR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_CMP ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_81 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 1b" +#______________________________________________________________________________ +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_OR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_AND ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_XOR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_CMP ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_82 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 1c" +#______________________________________________________________________________ +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_OR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_AND ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_XOR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_CMP ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_83 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 1d" +#______________________________________________________________________________ +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_OR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0 +INSN 0 INS_AND ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_XOR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_CMP ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_C0 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2a" +#______________________________________________________________________________ +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 0 0 INS_SET_ALL 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_C1 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2b" +#______________________________________________________________________________ +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 0 0 INS_SET_ALL 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_D0 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2c" +#______________________________________________________________________________ +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 1 0 INS_SET_ALL 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_D1 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2d" +#______________________________________________________________________________ +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 1 0 INS_SET_ALL 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_D2 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2e" +#______________________________________________________________________________ +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 1 0 INS_SET_ALL 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_D3 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2f" +#______________________________________________________________________________ +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0 +INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 1 0 INS_SET_ALL 0 +INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 1 0 INS_SET_ALL 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_F6 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 3a" +#______________________________________________________________________________ +INSN 0 INS_TEST ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_TEST ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_NOT ADDRMETH_E | OPTYPE_b | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "not" 0 0 0 0 0 +INSN 0 INS_NEG ADDRMETH_E | OPTYPE_b | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "neg" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_MUL OPTYPE_b | ADDRMETH_RR | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 22 +INSN 0 INS_MUL OPTYPE_b | ADDRMETH_RR | OP_W | OP_SIGNED | OP_R ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "imul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 22 +INSN 0 INS_DIV ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "div" 0 0 0 0 13 +INSN 0 INS_DIV ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "idiv" 0 0 0 0 13 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_F7 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 3b" +#______________________________________________________________________________ +INSN 0 INS_TEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_TEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_NOT ADDRMETH_E | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "not" 0 0 0 0 0 +INSN 0 INS_NEG ADDRMETH_E | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "neg" 0 0 0 INS_SET_ALL 0 +INSN 0 INS_MUL ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 23 +INSN 0 INS_MUL ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "imul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 23 +INSN 0 INS_DIV ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "div" 0 0 0 0 14 +INSN 0 INS_DIV ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "idiv" 0 0 0 0 14 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_FE tbl_extension shift 3 mask 7 minlim 0 maxlim 1 "Group 4" +#______________________________________________________________________________ +INSN 0 INS_INC ADDRMETH_E | OPTYPE_b | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_DEC ADDRMETH_E | OPTYPE_b | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_FF tbl_extension shift 3 mask 7 minlim 0 maxlim 6 "Group 5" +#______________________________________________________________________________ +INSN 0 INS_INC ADDRMETH_E | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_DEC ADDRMETH_E | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0 +INSN 0 INS_CALL ADDRMETH_E | OPTYPE_v | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "call" 0 0 0 0 3 +INSN 0 INS_CALL ADDRMETH_E | OPTYPE_p | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "callf" 0 0 0 0 0 +INSN 0 INS_BRANCH ADDRMETH_E | OPTYPE_v | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jmp" 0 0 0 0 0 +INSN 0 INS_BRANCH ADDRMETH_E | OPTYPE_p | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jmpf" 0 0 0 0 0 +INSN 0 INS_PUSH ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 0 0 0 0 33 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_D8 tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU D8" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fadd" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fmul" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcom" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsub" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_D8C0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU D8 C0" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 1 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 2 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 3 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 4 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 5 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 6 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 7 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 1 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 2 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 3 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 4 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 5 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 6 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 7 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 1 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 2 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 3 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 4 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 5 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 6 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 7 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 1 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 2 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 3 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 4 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 5 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 6 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 7 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 1 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 2 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 3 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 4 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 5 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 6 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 7 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 1 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 2 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 3 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 4 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 5 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 6 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 7 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 1 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 2 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 3 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 4 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 5 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 6 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 7 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 1 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 2 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 3 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 4 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 5 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 6 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 7 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_D9 tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU D9" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fld" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fv|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldenv" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldcw" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fv|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnstenv" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnstcw" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_D9C0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU D9 C0" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 1 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 2 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 3 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 4 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 5 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 6 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 7 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 1 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 2 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 3 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 4 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 5 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 6 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 7 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnop" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fchs" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fabs" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ftst" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fxam" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fld1" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldl2t" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldl2e" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldpi" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldlg2" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldln2" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldz" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "f2xm1" 0 0 0 0 16 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fyl2x" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fptan" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fpatan" 0 0 0 0 18 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fxtract" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fprem1" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fdecstp" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fincstp" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fprem" 0 0 0 0 19 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fyl2xp1" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsqrt" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsincos" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "frndint" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fscale" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsin" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcos" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DA tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DA" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fiadd" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fimul" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ficom" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ficomp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fisub" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fisubr" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fidiv" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fidivr" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DAC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DA C0" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 0 0 INS_TEST_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 1 0 INS_TEST_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 2 0 INS_TEST_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 3 0 INS_TEST_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 4 0 INS_TEST_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 5 0 INS_TEST_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 6 0 INS_TEST_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 7 0 INS_TEST_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 0 0 INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 1 0 INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 2 0 INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 3 0 INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 4 0 INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 5 0 INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 6 0 INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 7 0 INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 0 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 1 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 2 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 3 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 4 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 5 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 6 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 7 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 0 0 INS_TEST_PARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 1 0 INS_TEST_PARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 2 0 INS_TEST_PARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 3 0 INS_TEST_PARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 4 0 INS_TEST_PARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 5 0 INS_TEST_PARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 6 0 INS_TEST_PARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 7 0 INS_TEST_PARITY 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fucompp" 0 0 0 0 21 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DB tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DB" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fild" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "fisttp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fist" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fistp" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fe|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fld" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fe|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DBC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DB C0" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 0 0 INS_TEST_NCARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 1 0 INS_TEST_NCARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 2 0 INS_TEST_NCARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 3 0 INS_TEST_NCARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 4 0 INS_TEST_NCARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 5 0 INS_TEST_NCARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 6 0 INS_TEST_NCARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 7 0 INS_TEST_NCARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 0 0 INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 1 0 INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 2 0 INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 3 0 INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 4 0 INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 5 0 INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 6 0 INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 7 0 INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 0 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 1 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 2 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 3 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 4 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 5 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 6 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 7 0 INS_TEST_NCARRY|INS_TEST_NZERO 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 0 0 INS_TEST_NPARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 1 0 INS_TEST_NPARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 2 0 INS_TEST_NPARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 3 0 INS_TEST_NPARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 4 0 INS_TEST_NPARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 5 0 INS_TEST_NPARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 6 0 INS_TEST_NPARITY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 7 0 INS_TEST_NPARITY 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnclex" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fninit" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 1 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 2 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 3 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 4 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 5 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 6 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 7 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 1 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 2 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 3 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 4 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 5 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 6 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 7 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DC tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DC" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fadd" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fmul" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcom" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsub" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DCC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DC C0" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 7 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 7 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 7 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 7 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 7 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 7 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DD tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DD" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fld" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_q|OP_W ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "fisttp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_ft|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "frstor" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_ft|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnsave" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnstsw" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DDC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DD C0" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 7 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 7 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 7 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 7 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 7 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DE tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DE" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fiadd" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fimul" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ficom" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ficomp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fisub" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fisubr" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fidiv" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fidivr" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DEC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DE C0" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 0 0 0 0 20 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 1 0 0 0 20 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 2 0 0 0 20 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 3 0 0 0 20 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 4 0 0 0 20 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 5 0 0 0 20 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 6 0 0 0 20 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 7 0 0 0 20 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 7 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcompp" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 7 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 7 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 7 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 1 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 2 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 3 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 4 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 5 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 6 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 7 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DF tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DF" +#______________________________________________________________________________ +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fild" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "fisttp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fist" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fistp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fb|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fbld" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_q|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fild" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fb|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fbstp" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_M|OPTYPE_q|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fistp" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_DFC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DF C0" +#______________________________________________________________________________ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RR | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnstsw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 0 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 1 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 2 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 3 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 4 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 5 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 6 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 7 0 0 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 1 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 2 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 3 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 4 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 5 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 6 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 7 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#+++++++++++++++++++---------------------------------++++++++++++++++++++ +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +TABLE tbl_0F0F tbl_suffix shift 0 mask 255 minlim 0 maxlim 191 "3D Now! 0F Suffix" +#______________________________________________________________________________ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 00 */ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_CONV ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pi2fd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 10 */ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_CONV ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pf2id" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 20 */ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 30 */ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 40 */ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 50 */ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 60 */ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 70 */ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 80 */ +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_CMP ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfcmpge" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_MIN ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfmin" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfrcp" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfrsqrt" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_SUB ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfsub" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfadd" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_CMP ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfcmpgt" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_MAX ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfmax" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfrcpit1" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfrsqit1" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_SUB ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfsubr" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_ADD ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfacc" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_CMP ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfcmpeq" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_MUL ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfmul" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfrcpit2" 0 0 0 0 0 +INSN 0 INS_MUL ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pmulhrw" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 +INSN 0 INS_AVG ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pavgusb" 0 0 0 0 0 +#______________________________________________________________________________ +END TABLE + + + +#======================================================================= +# TODO: +# + Support only three flags types: set, clear, and toggle. Move specific flag +# into flags set. +# + Finish typing 'unknown' instructions, esp ps and pd instructions. +#======================================================================= +# CPU Ver: +#mmx: (data xfer) movd, movq, (conversion) packsswb, packssdw, packuswb, +#punpckhbw, punpckhwd, punpckhdq, punpcklbw, punpcklwd, punpckldq, +#(arith) paddb, paddw, paddd, paddsb, paddsw, paddusb, paddusw, +#psubb, psubw, psubd, psubsb, psubsw, psubusb, psubusw, pmulhw, pmullw, pmaddwd, +#(cmp) PCMPEQB PCMPEQW PCMPEQD PCMPGTB PCMPGTW PCMPGTD, +#(logic) PAND PANDN POR PXOR, (shift/rot) PSLLW PSLLD PSLLQ PSRLW PSRLD +#PSRLQ PSRAW PSRAD, (sys) emms + +#sse: (data xfer) MOVAPS MOVUPS MOVHPS, MOVHLPS MOVLPS MOVLHPS MOVMSKPS MOVSS, +#(arith) ADDPS ADDSS SUBPS SUBSS MULPS MULSS DIVPS DIVSS RCPPS RCPSS SQRTPS +#SQRTSS RSQRTPS RSQRTSS MAXPS MAXSS MINPS MINSS, (cmp) CMPPS CMPSS COMISS +#UCOMISS, (logic) ANDPS ANDNPS ORPS XORPS, (misc) SHUFPS UNPCKHPS UNPCKLPS, +#(convert) CVTPI2PS CVTSI2SS CVTPS2PI CVTTPS2PI CVTSS2SI CVTTSS2SI, +#(sys) LDMXCSR STMXCSR, (misc) PAVGB PAVGW PEXTRW PINSRW PMAXUB PMAXSW PMINUB +#PMINSW, PMOVMSKB PMULHUW PSADBW PSHUFW, (sys) MASKMOVQ MOVNTQ MOVNTPS +# PREFETCHh SFENCE + +#sse2: (data xfer) MOVAPD MOVUPD MOVHPD MOVLPD MOVMSKPD MOVSD (arith) +#ADDPD ADDSD SUBPD SUBSD MULPD MULSD, DIVPD DIVSD SQRTPD SQRTSD MAXPD , +#MAXSD MINPD MINSD (logic) ANDPD ANDNPD ORPD XORPD, (cmp) CMPPD CMPSD COMISD +#UCOMISD, (misc) SHUFPD UNPCKHPD UNPCKLPD, (c0nvert) CVTPD2PI CVTTPD2PI +#CVTPI2PD CVTPD2DQ CVTTPD2DQ CVTDQ2PD CVTPS2PD CVTPD2PS CVTSS2SD CVTSD2SS +#CVTSD2SI CVTTSD2SI CVTSI2SD (fp) CVTDQ2PS CVTPS2DQ CVTTPS2DQ, (...) +#MOVDQA MOVDQU MOVQ2DQ MOVDQ2Q PMULUDQ PADDQ PSUBQ PSHUFLW PSHUFHW PSHUFD +#PSLLDQ PSRLDQ PUNPCKHQDQ PUNPCKLQDQ, (sys) CLFLUSH LFENCE MFENCE PAUSE +#MASKMOVDQU MOVNTPD MOVNTDQ MOVNTI + +#sse3: (convert) FISTTP, (data xfer) LDDQU, (arith) ADDSUBPS ADDSUBPD, +#HADDPS HSUBPS HADDPD HSUBPD, (data xfer) MOVSHDUP MOVSLDUP MOVDDUP, +#(sys) MONITOR MWAIT +#sys/ring0: LGDT SGDT LLDT SLDT LTR STR LIDT SIDT MOV LMSW +#SMSW CLTS ARPL LAR LSL VERR VERW MOV INVD WBINVD INVLPG LOCK HLT RSM RDMSR +#WRMSR RDPMC RDTSC SYSENTER SYSEXIT + +#386: lss, lfs, lgs, long disp jcc, single-bit insn, bit scan insns, +#double shift, byte set on cond, mov w/ sign ext, generalized multiply, +#mov to/from control reg, move to/from test reg, mov to/from debug reg, +#rsm + +# exceptions : bitmask them, return exception name? +#TABLE tbl_DA tbl_fpu shift 3 mask 15 minlim 0 maxlim 15 "FPU DA" +#TABLE tbl_DAC0 tbl_fpu_ext shift 0 mask 31 minlim 0 maxlim 31 "FPU DA C0" diff --git a/3rd_party/libdisasm/libdisasm.def b/3rd_party/libdisasm/libdisasm.def new file mode 100644 index 0000000..4972c67 --- /dev/null +++ b/3rd_party/libdisasm/libdisasm.def @@ -0,0 +1,49 @@ +;libdisasm.def : Declares the module parameters + +LIBRARY "libdisasm.dll" +DESCRIPTION "libdisasm exported functions" +EXPORTS + x86_addr_size @1 + x86_cleanup @2 + x86_disasm @3 + x86_disasm_forward @4 + x86_disasm_range @5 + x86_endian @6 + x86_format_header @7 + x86_format_insn @8 + x86_format_mnemonic @9 + x86_format_operand @10 + x86_fp_reg @11 + x86_get_branch_target @12 + x86_get_imm @13 + x86_get_options @14 + x86_get_raw_imm @15 + x86_get_rel_offset @16 + x86_imm_signsized @17 + x86_imm_sized @18 + x86_init @19 + x86_insn_is_tagged @20 + x86_insn_is_valid @21 + x86_invariant_disasm @22 + x86_ip_reg @23 + x86_max_insn_size @24 + x86_op_size @25 + x86_operand_1st @26 + x86_operand_2nd @27 + x86_operand_3rd @28 + x86_operand_count @29 + x86_operand_foreach @30 + x86_operand_new @31 + x86_operand_size @32 + x86_oplist_free @33 + x86_reg_from_id @34 + x86_report_error @35 + x86_set_insn_addr @36 + x86_set_insn_block @37 + x86_set_insn_function @38 + x86_set_insn_offset @39 + x86_set_options @40 + x86_set_reporter @41 + x86_size_disasm @42 + x86_sp_reg @43 + x86_tag_insn @44 \ No newline at end of file diff --git a/CMakeLists.txt b/CMakeLists.txt index c908034..849691b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -12,7 +12,7 @@ IF(CMAKE_BUILD_TOOL MATCHES "(msdev|devenv|nmake)") ADD_DEFINITIONS(/W4) ELSE() #-D_GLIBCXX_DEBUG - SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall --std=c++11") + SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -std=c++11") SET(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} " ) #--coverage ENDIF() @@ -46,9 +46,9 @@ set(dcc_LIB_SOURCES src/control.cpp src/dataflow.cpp src/disassem.cpp + src/DccFrontend.cpp src/error.cpp src/fixwild.cpp - src/frontend.cpp src/graph.cpp src/hlicode.cpp src/hltype.cpp @@ -77,6 +77,7 @@ set(dcc_LIB_SOURCES src/symtab.cpp src/udm.cpp src/BasicBlock.cpp + src/dcc_interface.cpp ) set(dcc_SOURCES src/dcc.cpp @@ -85,6 +86,7 @@ set(dcc_HEADERS include/ast.h include/bundle.h include/BinaryImage.h + include/DccFrontend.h include/dcc.h include/disassem.h include/dosdcc.h @@ -113,18 +115,21 @@ set(dcc_HEADERS include/Procedure.h include/StackFrame.h include/BasicBlock.h + include/dcc_interface.h ) SOURCE_GROUP(Source FILES ${dcc_SOURCES}) SOURCE_GROUP(Headers FILES ${dcc_HEADERS}) ADD_LIBRARY(dcc_lib STATIC ${dcc_LIB_SOURCES} ${dcc_HEADERS}) +qt5_use_modules(dcc_lib Core) #cotire(dcc_lib) ADD_EXECUTABLE(dcc_original ${dcc_SOURCES} ${dcc_HEADERS}) ADD_DEPENDENCIES(dcc_original dcc_lib) TARGET_LINK_LIBRARIES(dcc_original dcc_lib disasm_s ${REQ_LLVM_LIBRARIES} ncurses LLVMSupport) qt5_use_modules(dcc_original Core) +#ADD_SUBDIRECTORY(gui) if(dcc_build_tests) ADD_SUBDIRECTORY(src) endif() diff --git a/CMakeScripts/cotire.cmake b/CMakeScripts/cotire.cmake index 3cd4c05..ddfe4bf 100644 --- a/CMakeScripts/cotire.cmake +++ b/CMakeScripts/cotire.cmake @@ -3,7 +3,7 @@ # See the cotire manual for usage hints. # #============================================================================= -# Copyright 2012 Sascha Kratky +# Copyright 2012-2014 Sascha Kratky # # Permission is hereby granted, free of charge, to any person # obtaining a copy of this software and associated documentation @@ -32,40 +32,45 @@ if(__COTIRE_INCLUDED) endif() set(__COTIRE_INCLUDED TRUE) +# call cmake_minimum_required, but prevent modification of the CMake policy stack in include mode +# cmake_minimum_required also sets the policy version as a side effect, which we have to avoid +if (NOT CMAKE_SCRIPT_MODE_FILE) + cmake_policy(PUSH) +endif() # we need the CMake variables CMAKE_SCRIPT_MODE_FILE and CMAKE_ARGV available since 2.8.5 # we need APPEND_STRING option for set_property available since 2.8.6 cmake_minimum_required(VERSION 2.8.6) +if (NOT CMAKE_SCRIPT_MODE_FILE) + cmake_policy(POP) +endif() set (COTIRE_CMAKE_MODULE_FILE "${CMAKE_CURRENT_LIST_FILE}") -set (COTIRE_CMAKE_MODULE_VERSION "1.1.2") +set (COTIRE_CMAKE_MODULE_VERSION "1.6.1") include(CMakeParseArguments) +include(ProcessorCount) function (cotire_determine_compiler_version _language _versionPrefix) if (NOT ${_versionPrefix}_VERSION) - if (MSVC) - # use CMake's predefined version variable for MSVC, if available - if (DEFINED MSVC_VERSION) - set (${_versionPrefix}_VERSION "${MSVC_VERSION}") - else() - # cl.exe messes with the output streams unless the environment variable VS_UNICODE_OUTPUT is cleared - unset (ENV{VS_UNICODE_OUTPUT}) - string (STRIP "${CMAKE_${_language}_COMPILER_ARG1}" _compilerArg1) - execute_process (COMMAND ${CMAKE_${_language}_COMPILER} ${_compilerArg1} - ERROR_VARIABLE _versionLine OUTPUT_QUIET TIMEOUT 10) - string (REGEX REPLACE ".*Version *([0-9]+(\\.[0-9]+)*).*" "\\1" - ${_versionPrefix}_VERSION "${_versionLine}") - endif() + # use CMake's predefined compiler version variable (available since CMake 2.8.8) + if (DEFINED CMAKE_${_language}_COMPILER_VERSION) + set (${_versionPrefix}_VERSION "${CMAKE_${_language}_COMPILER_VERSION}") + elseif (WIN32) + # cl.exe messes with the output streams unless the environment variable VS_UNICODE_OUTPUT is cleared + unset (ENV{VS_UNICODE_OUTPUT}) + string (STRIP "${CMAKE_${_language}_COMPILER_ARG1}" _compilerArg1) + execute_process (COMMAND ${CMAKE_${_language}_COMPILER} ${_compilerArg1} + ERROR_VARIABLE _versionLine OUTPUT_QUIET TIMEOUT 10) + string (REGEX REPLACE ".*Version *([0-9]+(\\.[0-9]+)*).*" "\\1" ${_versionPrefix}_VERSION "${_versionLine}") else() - # use CMake's predefined compiler version variable (available since CMake 2.8.8) - if (DEFINED CMAKE_${_language}_COMPILER_VERSION) - set (${_versionPrefix}_VERSION "${CMAKE_${_language}_COMPILER_VERSION}") - else() - # assume GCC like command line interface - string (STRIP "${CMAKE_${_language}_COMPILER_ARG1}" _compilerArg1) - execute_process (COMMAND ${CMAKE_${_language}_COMPILER} ${_compilerArg1} "-dumpversion" - OUTPUT_VARIABLE ${_versionPrefix}_VERSION - OUTPUT_STRIP_TRAILING_WHITESPACE TIMEOUT 10) + # assume GCC like command line interface + string (STRIP "${CMAKE_${_language}_COMPILER_ARG1}" _compilerArg1) + execute_process (COMMAND ${CMAKE_${_language}_COMPILER} ${_compilerArg1} "-dumpversion" + OUTPUT_VARIABLE ${_versionPrefix}_VERSION + RESULT_VARIABLE _result + OUTPUT_STRIP_TRAILING_WHITESPACE TIMEOUT 10) + if (_result) + set (${_versionPrefix}_VERSION "") endif() endif() if (${_versionPrefix}_VERSION) @@ -118,9 +123,15 @@ function (cotire_filter_language_source_files _language _sourceFilesVar _exclude else() set (_ignoreExtensions "") endif() + if (COTIRE_UNITY_SOURCE_EXCLUDE_EXTENSIONS) + set (_excludeExtensions "${COTIRE_UNITY_SOURCE_EXCLUDE_EXTENSIONS}") + else() + set (_excludeExtensions "") + endif() if (COTIRE_DEBUG) message (STATUS "${_language} source file extensions: ${_languageExtensions}") message (STATUS "${_language} ignore extensions: ${_ignoreExtensions}") + message (STATUS "${_language} exclude extensions: ${_excludeExtensions}") endif() foreach (_sourceFile ${ARGN}) get_source_file_property(_sourceIsHeaderOnly "${_sourceFile}" HEADER_FILE_ONLY) @@ -131,10 +142,20 @@ function (cotire_filter_language_source_files _language _sourceFilesVar _exclude if (NOT _sourceIsHeaderOnly AND NOT _sourceIsExternal AND NOT _sourceIsSymbolic) cotire_get_source_file_extension("${_sourceFile}" _sourceExt) if (_sourceExt) - list (FIND _languageExtensions "${_sourceExt}" _sourceIndex) list (FIND _ignoreExtensions "${_sourceExt}" _ignoreIndex) - if (_sourceIndex GREATER -1 AND _ignoreIndex LESS 0) - set (_sourceIsFiltered TRUE) + if (_ignoreIndex LESS 0) + list (FIND _excludeExtensions "${_sourceExt}" _excludeIndex) + if (_excludeIndex GREATER -1) + list (APPEND _excludedSourceFiles "${_sourceFile}") + else() + list (FIND _languageExtensions "${_sourceExt}" _sourceIndex) + if (_sourceIndex GREATER -1) + set (_sourceIsFiltered TRUE) + elseif ("${_sourceLanguage}" STREQUAL "${_language}") + # add to excluded sources, if file is not ignored and has correct language without having the correct extension + list (APPEND _excludedSourceFiles "${_sourceFile}") + endif() + endif() endif() endif() endif() @@ -146,7 +167,7 @@ function (cotire_filter_language_source_files _language _sourceFilesVar _exclude get_source_file_property(_sourceIsCotired "${_sourceFile}" COTIRE_TARGET) get_source_file_property(_sourceCompileFlags "${_sourceFile}" COMPILE_FLAGS) if (COTIRE_DEBUG) - message (STATUS "${_sourceFile} excluded=${_sourceIsExcluded} cotired=${_sourceIsCotired}") + message (STATUS "${_sourceFile} excluded=${_sourceIsExcluded} cotired=${_sourceIsCotired} compileFlags=${_sourceCompileFlags}") endif() if (_sourceIsCotired) list (APPEND _cotiredSourceFiles "${_sourceFile}") @@ -207,7 +228,7 @@ function (cotire_get_source_file_property_values _valuesVar _property) set (${_valuesVar} ${_values} PARENT_SCOPE) endfunction() -function (cotrie_resolve_config_properites _configurations _propertiesVar) +function (cotire_resolve_config_properites _configurations _propertiesVar) set (_properties "") foreach (_property ${ARGN}) if ("${_property}" MATCHES "") @@ -223,8 +244,8 @@ function (cotrie_resolve_config_properites _configurations _propertiesVar) set (${_propertiesVar} ${_properties} PARENT_SCOPE) endfunction() -function (cotrie_copy_set_properites _configurations _type _source _target) - cotrie_resolve_config_properites("${_configurations}" _properties ${ARGN}) +function (cotire_copy_set_properites _configurations _type _source _target) + cotire_resolve_config_properites("${_configurations}" _properties ${ARGN}) foreach (_property ${_properties}) get_property(_isSet ${_type} ${_source} PROPERTY ${_property} SET) if (_isSet) @@ -234,8 +255,8 @@ function (cotrie_copy_set_properites _configurations _type _source _target) endforeach() endfunction() -function (cotire_filter_compile_flags _flagFilter _matchedOptionsVar _unmatchedOptionsVar) - if (MSVC) +function (cotire_filter_compile_flags _language _flagFilter _matchedOptionsVar _unmatchedOptionsVar) + if (WIN32 AND CMAKE_${_language}_COMPILER_ID MATCHES "MSVC|Intel") set (_flagPrefix "[/-]") else() set (_flagPrefix "--?") @@ -296,13 +317,36 @@ function (cotire_get_target_compile_flags _config _language _directory _target _ if (_target) # add option from CMake target type variable get_target_property(_targetType ${_target} TYPE) - if (_targetType STREQUAL "MODULE_LIBRARY") - # flags variable for module library uses different name SHARED_MODULE - # (e.g., CMAKE_SHARED_MODULE_C_FLAGS) - set (_targetType SHARED_MODULE) + if (POLICY CMP0018) + # handle POSITION_INDEPENDENT_CODE property introduced with CMake 2.8.9 if policy CMP0018 is turned on + cmake_policy(GET CMP0018 _PIC_Policy) + else() + # default to old behavior + set (_PIC_Policy "OLD") endif() - if (CMAKE_${_targetType}_${_language}_FLAGS) - set (_compileFlags "${_compileFlags} ${CMAKE_${_targetType}_${_language}_FLAGS}") + if (COTIRE_DEBUG) + message(STATUS "CMP0018=${_PIC_Policy}") + endif() + if (_PIC_Policy STREQUAL "NEW") + # NEW behavior: honor the POSITION_INDEPENDENT_CODE target property + get_target_property(_targetPIC ${_target} POSITION_INDEPENDENT_CODE) + if (_targetPIC) + if (_targetType STREQUAL "EXECUTABLE" AND CMAKE_${_language}_COMPILE_OPTIONS_PIE) + set (_compileFlags "${_compileFlags} ${CMAKE_${_language}_COMPILE_OPTIONS_PIE}") + elseif (CMAKE_${_language}_COMPILE_OPTIONS_PIC) + set (_compileFlags "${_compileFlags} ${CMAKE_${_language}_COMPILE_OPTIONS_PIC}") + endif() + endif() + else() + # OLD behavior or policy not set: use the value of CMAKE_SHARED_LIBRARY__FLAGS + if (_targetType STREQUAL "MODULE_LIBRARY") + # flags variable for module library uses different name SHARED_MODULE + # (e.g., CMAKE_SHARED_MODULE_C_FLAGS) + set (_targetType SHARED_MODULE) + endif() + if (CMAKE_${_targetType}_${_language}_FLAGS) + set (_compileFlags "${_compileFlags} ${CMAKE_${_targetType}_${_language}_FLAGS}") + endif() endif() endif() if (_directory) @@ -318,6 +362,10 @@ function (cotire_get_target_compile_flags _config _language _directory _target _ if (_targetflags) set (_compileFlags "${_compileFlags} ${_targetflags}") endif() + get_target_property(_targetOptions ${_target} COMPILE_OPTIONS) + if (_targetOptions) + set (_compileFlags "${_compileFlags} ${_targetOptions}") + endif() endif() if (UNIX) separate_arguments(_compileFlags UNIX_COMMAND "${_compileFlags}") @@ -335,13 +383,19 @@ function (cotire_get_target_compile_flags _config _language _directory _target _ foreach (_arch ${_architectures}) list (APPEND _compileFlags "-arch" "${_arch}") endforeach() - if (CMAKE_OSX_SYSROOT AND CMAKE_OSX_SYSROOT_DEFAULT AND CMAKE_${_language}_HAS_ISYSROOT) - if (NOT "${CMAKE_OSX_SYSROOT}" STREQUAL "${CMAKE_OSX_SYSROOT_DEFAULT}") + if (CMAKE_OSX_SYSROOT) + if (CMAKE_${_language}_SYSROOT_FLAG) + list (APPEND _compileFlags "${CMAKE_${_language}_SYSROOT_FLAG}" "${CMAKE_OSX_SYSROOT}") + else() list (APPEND _compileFlags "-isysroot" "${CMAKE_OSX_SYSROOT}") endif() endif() - if (CMAKE_OSX_DEPLOYMENT_TARGET AND CMAKE_${_language}_OSX_DEPLOYMENT_TARGET_FLAG) - list (APPEND _compileFlags "${CMAKE_${_language}_OSX_DEPLOYMENT_TARGET_FLAG}${CMAKE_OSX_DEPLOYMENT_TARGET}") + if (CMAKE_OSX_DEPLOYMENT_TARGET) + if (CMAKE_${_language}_OSX_DEPLOYMENT_TARGET_FLAG) + list (APPEND _compileFlags "${CMAKE_${_language}_OSX_DEPLOYMENT_TARGET_FLAG}${CMAKE_OSX_DEPLOYMENT_TARGET}") + else() + list (APPEND _compileFlags "-mmacosx-version-min=${CMAKE_OSX_DEPLOYMENT_TARGET}") + endif() endif() endif() if (COTIRE_DEBUG AND _compileFlags) @@ -350,21 +404,22 @@ function (cotire_get_target_compile_flags _config _language _directory _target _ set (${_flagsVar} ${_compileFlags} PARENT_SCOPE) endfunction() -function (cotire_get_target_include_directories _config _language _directory _target _includeDirsVar) +function (cotire_get_target_include_directories _config _language _targetSourceDir _targetBinaryDir _target _includeDirsVar) set (_includeDirs "") # default include dirs if (CMAKE_INCLUDE_CURRENT_DIR) - list (APPEND _includeDirs "${CMAKE_CURRENT_BINARY_DIR}") - list (APPEND _includeDirs "${CMAKE_CURRENT_SOURCE_DIR}") + list (APPEND _includeDirs "${_targetBinaryDir}") + list (APPEND _includeDirs "${_targetSourceDir}") endif() # parse additional include directories from target compile flags - cotire_get_target_compile_flags("${_config}" "${_language}" "${_directory}" "${_target}" _targetFlags) - cotire_filter_compile_flags("I" _dirs _ignore ${_targetFlags}) + set (_targetFlags "") + cotire_get_target_compile_flags("${_config}" "${_language}" "${_targetSourceDir}" "${_target}" _targetFlags) + cotire_filter_compile_flags("${_language}" "I" _dirs _ignore ${_targetFlags}) if (_dirs) list (APPEND _includeDirs ${_dirs}) endif() # target include directories - get_directory_property(_dirs DIRECTORY "${_directory}" INCLUDE_DIRECTORIES) + get_directory_property(_dirs DIRECTORY "${_targetSourceDir}" INCLUDE_DIRECTORIES) if (_target) get_target_property(_targetDirs ${_target} INCLUDE_DIRECTORIES) if (_targetDirs) @@ -377,7 +432,12 @@ function (cotire_get_target_include_directories _config _language _directory _ta if (CMAKE_INCLUDE_DIRECTORIES_PROJECT_BEFORE) cotire_check_is_path_relative_to("${_dir}" _isRelative "${CMAKE_SOURCE_DIR}" "${CMAKE_BINARY_DIR}") if (_isRelative) - list (INSERT _includeDirs _projectInsertIndex "${_dir}") + list (LENGTH _includeDirs _len) + if (_len EQUAL _projectInsertIndex) + list (APPEND _includeDirs "${_dir}") + else() + list (INSERT _includeDirs _projectInsertIndex "${_dir}") + endif() math (EXPR _projectInsertIndex "${_projectInsertIndex} + 1") else() list (APPEND _includeDirs "${_dir}") @@ -397,11 +457,15 @@ function (cotire_get_target_include_directories _config _language _directory _ta endfunction() macro (cotire_make_C_identifier _identifierVar _str) - # mimic CMake SystemTools::MakeCindentifier behavior - if ("${_str}" MATCHES "^[0-9].+$") - set (_str "_${str}") + if (CMAKE_VERSION VERSION_LESS "2.8.12") + # mimic CMake SystemTools::MakeCindentifier behavior + if ("${_str}" MATCHES "^[0-9].+$") + set (_str "_${str}") + endif() + string (REGEX REPLACE "[^a-zA-Z0-9]" "_" ${_identifierVar} "${_str}") + else() + string (MAKE_C_IDENTIFIER "${_identifierVar}" "${_str}") endif() - string (REGEX REPLACE "[^a-zA-Z0-9]" "_" ${_identifierVar} "${_str}") endmacro() function (cotire_get_target_export_symbol _target _exportSymbolVar) @@ -451,8 +515,9 @@ function (cotire_get_target_compile_definitions _config _language _directory _ta endif() # parse additional compile definitions from target compile flags # and don't look at directory compile definitions, which we already handled + set (_targetFlags "") cotire_get_target_compile_flags("${_config}" "${_language}" "" "${_target}" _targetFlags) - cotire_filter_compile_flags("D" _definitions _ignore ${_targetFlags}) + cotire_filter_compile_flags("${_language}" "D" _definitions _ignore ${_targetFlags}) if (_definitions) list (APPEND _configDefinitions ${_definitions}) endif() @@ -465,10 +530,12 @@ endfunction() function (cotire_get_target_compiler_flags _config _language _directory _target _compilerFlagsVar) # parse target compile flags omitting compile definitions and include directives + set (_targetFlags "") cotire_get_target_compile_flags("${_config}" "${_language}" "${_directory}" "${_target}" _targetFlags) - cotire_filter_compile_flags("[ID]" _ignore _compilerFlags ${_targetFlags}) - if (COTIRE_DEBUG AND _compileFlags) - message (STATUS "Target ${_target} compiler flags ${_compileFlags}") + set (_compilerFlags "") + cotire_filter_compile_flags("${_language}" "[ID]" _ignore _compilerFlags ${_targetFlags}) + if (COTIRE_DEBUG AND _compilerFlags) + message (STATUS "Target ${_target} compiler flags ${_compilerFlags}") endif() set (${_compilerFlagsVar} ${_compilerFlags} PARENT_SCOPE) endfunction() @@ -503,7 +570,7 @@ function (cotire_get_source_extra_properties _sourceFile _pattern _resultVar) math (EXPR _len "${_len} - 1") foreach (_index RANGE ${_index} ${_len}) list (GET _extraProperties ${_index} _value) - if ("${_value}" MATCHES "${_pattern}") + if (_value MATCHES "${_pattern}") list (APPEND _result "${_value}") else() break() @@ -579,6 +646,9 @@ endfunction() macro (cotire_set_cmd_to_prologue _cmdVar) set (${_cmdVar} "${CMAKE_COMMAND}") + if (COTIRE_DEBUG) + list (APPEND ${_cmdVar} "--warn-uninitialized") + endif() list (APPEND ${_cmdVar} "-DCOTIRE_BUILD_TYPE:STRING=$") if (COTIRE_VERBOSE) list (APPEND ${_cmdVar} "-DCOTIRE_VERBOSE:BOOL=ON") @@ -589,7 +659,7 @@ endmacro() function (cotire_init_compile_cmd _cmdVar _language _compilerExe _compilerArg1) if (NOT _compilerExe) - set (_compilerExe "${CMAKE_${_language}_COMPILER") + set (_compilerExe "${CMAKE_${_language}_COMPILER}") endif() if (NOT _compilerArg1) set (_compilerArg1 ${CMAKE_${_language}_COMPILER_ARG1}) @@ -598,9 +668,9 @@ function (cotire_init_compile_cmd _cmdVar _language _compilerExe _compilerArg1) set (${_cmdVar} "${_compilerExe}" ${_compilerArg1} PARENT_SCOPE) endfunction() -macro (cotire_add_definitions_to_cmd _cmdVar) +macro (cotire_add_definitions_to_cmd _cmdVar _language) foreach (_definition ${ARGN}) - if (MSVC) + if (WIN32 AND CMAKE_${_language}_COMPILER_ID MATCHES "MSVC|Intel") list (APPEND ${_cmdVar} "/D${_definition}") else() list (APPEND ${_cmdVar} "-D${_definition}") @@ -608,9 +678,9 @@ macro (cotire_add_definitions_to_cmd _cmdVar) endforeach() endmacro() -macro (cotire_add_includes_to_cmd _cmdVar) +macro (cotire_add_includes_to_cmd _cmdVar _language) foreach (_include ${ARGN}) - if (MSVC) + if (WIN32 AND CMAKE_${_language}_COMPILER_ID MATCHES "MSVC|Intel") file (TO_NATIVE_PATH "${_include}" _include) list (APPEND ${_cmdVar} "/I${_include}") else() @@ -619,6 +689,24 @@ macro (cotire_add_includes_to_cmd _cmdVar) endforeach() endmacro() +macro (cotire_add_frameworks_to_cmd _cmdVar _language) + if (APPLE) + set (_frameWorkDirs "") + foreach (_include ${ARGN}) + if (IS_ABSOLUTE "${_include}" AND _include MATCHES "\\.framework$") + get_filename_component(_frameWorkDir "${_include}" PATH) + list (APPEND _frameWorkDirs "${_frameWorkDir}") + endif() + endforeach() + if (_frameWorkDirs) + list (REMOVE_DUPLICATES _frameWorkDirs) + foreach (_frameWorkDir ${_frameWorkDirs}) + list (APPEND ${_cmdVar} "-F${_frameWorkDir}") + endforeach() + endif() + endif() +endmacro() + macro (cotire_add_compile_flags_to_cmd _cmdVar) foreach (_flag ${ARGN}) list (APPEND ${_cmdVar} "${_flag}") @@ -729,7 +817,7 @@ macro (cotire_parse_line _line _headerFileVar _headerDepthVar) # English: "Note: including file: C:\directory\file" # German: "Hinweis: Einlesen der Datei: C:\directory\file" # We use a very general regular expression, relying on the presence of the : characters - if ("${_line}" MATCHES ":( +)([^:]+:[^:]+)$") + if (_line MATCHES ":( +)([^:]+:[^:]+)$") # Visual Studio compiler output string (LENGTH "${CMAKE_MATCH_1}" ${_headerDepthVar}) get_filename_component(${_headerFileVar} "${CMAKE_MATCH_2}" ABSOLUTE) @@ -738,7 +826,7 @@ macro (cotire_parse_line _line _headerFileVar _headerDepthVar) set (${_headerDepthVar} 0) endif() else() - if ("${_line}" MATCHES "^(\\.+) (.*)$") + if (_line MATCHES "^(\\.+) (.*)$") # GCC like output string (LENGTH "${CMAKE_MATCH_1}" ${_headerDepthVar}) if (IS_ABSOLUTE "${CMAKE_MATCH_2}") @@ -758,13 +846,17 @@ function (cotire_parse_includes _language _scanOutput _ignoredIncudeDirs _honore # prevent CMake macro invocation errors due to backslash characters in Windows paths string (REPLACE "\\" "/" _scanOutput "${_scanOutput}") endif() + # canonize slashes + string (REPLACE "//" "/" _scanOutput "${_scanOutput}") + # prevent semicolon from being interpreted as a line separator string (REPLACE ";" "\\;" _scanOutput "${_scanOutput}") + # then separate lines string (REGEX REPLACE "\n" ";" _scanOutput "${_scanOutput}") list (LENGTH _scanOutput _len) # remove duplicate lines to speed up parsing list (REMOVE_DUPLICATES _scanOutput) list (LENGTH _scanOutput _uniqueLen) - if (COTIRE_VERBOSE) + if (COTIRE_VERBOSE OR COTIRE_DEBUG) message (STATUS "Scanning ${_uniqueLen} unique lines of ${_len} for includes") if (_ignoredExtensions) message (STATUS "Ignored extensions: ${_ignoredExtensions}") @@ -865,9 +957,10 @@ function (cotire_scan_includes _includesVar) endif() set (_cmd "${_option_COMPILER_EXECUTABLE}" ${_option_COMPILER_ARG1}) cotire_init_compile_cmd(_cmd "${_option_LANGUAGE}" "${_option_COMPILER_EXECUTABLE}" "${_option_COMPILER_ARG1}") - cotire_add_definitions_to_cmd(_cmd ${_option_COMPILE_DEFINITIONS}) + cotire_add_definitions_to_cmd(_cmd "${_option_LANGUAGE}" ${_option_COMPILE_DEFINITIONS}) cotire_add_compile_flags_to_cmd(_cmd ${_option_COMPILE_FLAGS}) - cotire_add_includes_to_cmd(_cmd ${_option_INCLUDE_DIRECTORIES}) + cotire_add_includes_to_cmd(_cmd "${_option_LANGUAGE}" ${_option_INCLUDE_DIRECTORIES}) + cotire_add_frameworks_to_cmd(_cmd "${_option_LANGUAGE}" ${_option_INCLUDE_DIRECTORIES}) cotire_add_makedep_flags("${_option_LANGUAGE}" "${_option_COMPILER_ID}" "${_option_COMPILER_VERSION}" _cmd) # only consider existing source files for scanning set (_existingSourceFiles "") @@ -884,14 +977,18 @@ function (cotire_scan_includes _includesVar) if (COTIRE_VERBOSE) message (STATUS "execute_process: ${_cmd}") endif() - if ("${_option_COMPILER_ID}" STREQUAL "MSVC") + if (_option_COMPILER_ID MATCHES "MSVC") if (COTIRE_DEBUG) message (STATUS "clearing VS_UNICODE_OUTPUT") endif() # cl.exe messes with the output streams unless the environment variable VS_UNICODE_OUTPUT is cleared unset (ENV{VS_UNICODE_OUTPUT}) endif() - execute_process(COMMAND ${_cmd} WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" OUTPUT_QUIET ERROR_VARIABLE _output) + execute_process(COMMAND ${_cmd} WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" + RESULT_VARIABLE _result OUTPUT_QUIET ERROR_VARIABLE _output) + if (_result) + message (STATUS "Result ${_result} scanning includes of ${_existingSourceFiles}.") + endif() cotire_parse_includes( "${_option_LANGUAGE}" "${_output}" "${_option_IGNORE_PATH}" "${_option_INCLUDE_PATH}" @@ -949,7 +1046,7 @@ function (cotire_generate_unity_source _unityFile) set(_oneValueArgs LANGUAGE) set(_multiValueArgs DEPENDS SOURCES_COMPILE_DEFINITIONS - PRE_UNDEFS SOURCES_PRE_UNDEFS POST_UNDEFS SOURCES_POST_UNDEFS) + PRE_UNDEFS SOURCES_PRE_UNDEFS POST_UNDEFS SOURCES_POST_UNDEFS PROLOGUE EPILOGUE) cmake_parse_arguments(_option "${_options}" "${_oneValueArgs}" "${_multiValueArgs}" ${ARGN}) if (_option_DEPENDS) cotire_check_file_up_to_date(_unityFileIsUpToDate "${_unityFile}" ${_option_DEPENDS}) @@ -971,6 +1068,9 @@ function (cotire_generate_unity_source _unityFile) set (_option_SOURCES_POST_UNDEFS "") endif() set (_contents "") + if (_option_PROLOGUE) + list (APPEND _contents ${_option_PROLOGUE}) + endif() if (_option_LANGUAGE AND _sourceFiles) if ("${_option_LANGUAGE}" STREQUAL "CXX") list (APPEND _contents "#ifdef __cplusplus") @@ -1002,7 +1102,7 @@ function (cotire_generate_unity_source _unityFile) list (APPEND _compileUndefinitions ${_option_POST_UNDEFS}) endif() foreach (_definition ${_compileDefinitions}) - if ("${_definition}" MATCHES "^([a-zA-Z0-9_]+)=(.+)$") + if (_definition MATCHES "^([a-zA-Z0-9_]+)=(.+)$") list (APPEND _contents "#define ${CMAKE_MATCH_1} ${CMAKE_MATCH_2}") list (INSERT _compileUndefinitions 0 "${CMAKE_MATCH_1}") else() @@ -1023,6 +1123,9 @@ function (cotire_generate_unity_source _unityFile) if (_option_LANGUAGE AND _sourceFiles) list (APPEND _contents "#endif") endif() + if (_option_EPILOGUE) + list (APPEND _contents ${_option_EPILOGUE}) + endif() list (APPEND _contents "") string (REPLACE ";" "\n" _contents "${_contents}") if (COTIRE_VERBOSE) @@ -1043,6 +1146,19 @@ function (cotire_generate_prefix_header _prefixFile) return() endif() endif() + set (_prologue "") + set (_epilogue "") + if (_option_COMPILER_ID MATCHES "Clang") + set (_prologue "#pragma clang system_header") + elseif (_option_COMPILER_ID MATCHES "GNU") + set (_prologue "#pragma GCC system_header") + elseif (_option_COMPILER_ID MATCHES "MSVC") + set (_prologue "#pragma warning(push, 0)") + set (_epilogue "#pragma warning(pop)") + elseif (_option_COMPILER_ID MATCHES "Intel") + # Intel compiler requires hdrstop pragma to stop generating PCH file + set (_epilogue "#pragma hdrstop") + endif() set (_sourceFiles ${_option_UNPARSED_ARGUMENTS}) cotire_scan_includes(_selectedHeaders ${_sourceFiles} LANGUAGE "${_option_LANGUAGE}" @@ -1056,7 +1172,8 @@ function (cotire_generate_prefix_header _prefixFile) INCLUDE_PATH ${_option_INCLUDE_PATH} IGNORE_EXTENSIONS ${_option_IGNORE_EXTENSIONS} UNPARSED_LINES _unparsedLines) - cotire_generate_unity_source("${_prefixFile}" LANGUAGE "${_option_LANGUAGE}" ${_selectedHeaders}) + cotire_generate_unity_source("${_prefixFile}" + PROLOGUE ${_prologue} EPILOGUE ${_epilogue} LANGUAGE "${_option_LANGUAGE}" ${_selectedHeaders}) set (_unparsedLinesFile "${_prefixFile}.log") if (_unparsedLines) if (COTIRE_VERBOSE OR NOT _selectedHeaders) @@ -1065,15 +1182,13 @@ function (cotire_generate_prefix_header _prefixFile) message (STATUS "${_skippedLineCount} line(s) skipped, see ${_unparsedLinesFileRelPath}") endif() string (REPLACE ";" "\n" _unparsedLines "${_unparsedLines}") - file (WRITE "${_unparsedLinesFile}" "${_unparsedLines}\n") - else() - file (REMOVE "${_unparsedLinesFile}") endif() + file (WRITE "${_unparsedLinesFile}" "${_unparsedLines}") endfunction() function (cotire_add_makedep_flags _language _compilerID _compilerVersion _flagsVar) set (_flags ${${_flagsVar}}) - if ("${_compilerID}" STREQUAL "MSVC") + if (_compilerID MATCHES "MSVC") # cl.exe options used # /nologo suppresses display of sign-on banner # /TC treat all files named on the command line as C source files @@ -1089,7 +1204,7 @@ function (cotire_add_makedep_flags _language _compilerID _compilerVersion _flags # return as a flag string set (_flags "${_sourceFileType${_language}} /EP /showIncludes") endif() - elseif ("${_compilerID}" STREQUAL "GNU") + elseif (_compilerID MATCHES "GNU") # GCC options used # -H print the name of each header file used # -E invoke preprocessor @@ -1107,7 +1222,7 @@ function (cotire_add_makedep_flags _language _compilerID _compilerVersion _flags set (_flags "${_flags} -fdirectives-only") endif() endif() - elseif ("${_compilerID}" STREQUAL "Clang") + elseif (_compilerID MATCHES "Clang") # Clang options used # -H print the name of each header file used # -E invoke preprocessor @@ -1118,6 +1233,42 @@ function (cotire_add_makedep_flags _language _compilerID _compilerVersion _flags # return as a flag string set (_flags "-H -E") endif() + elseif (_compilerID MATCHES "Intel") + if (WIN32) + # Windows Intel options used + # /nologo do not display compiler version information + # /QH display the include file order + # /EP preprocess to stdout, omitting #line directives + # /TC process all source or unrecognized file types as C source files + # /TP process all source or unrecognized file types as C++ source files + set (_sourceFileTypeC "/TC") + set (_sourceFileTypeCXX "/TP") + if (_flags) + # append to list + list (APPEND _flags /nologo "${_sourceFileType${_language}}" /EP /QH) + else() + # return as a flag string + set (_flags "${_sourceFileType${_language}} /EP /QH") + endif() + else() + # Linux / Mac OS X Intel options used + # -H print the name of each header file used + # -EP preprocess to stdout, omitting #line directives + # -Kc++ process all source or unrecognized file types as C++ source files + if (_flags) + # append to list + if ("${_language}" STREQUAL "CXX") + list (APPEND _flags -Kc++) + endif() + list (APPEND _flags -H -EP) + else() + # return as a flag string + if ("${_language}" STREQUAL "CXX") + set (_flags "-Kc++ ") + endif() + set (_flags "${_flags}-H -EP") + endif() + endif() else() message (FATAL_ERROR "Unsupported ${_language} compiler ${_compilerID} version ${_compilerVersion}.") endif() @@ -1126,7 +1277,7 @@ endfunction() function (cotire_add_pch_compilation_flags _language _compilerID _compilerVersion _prefixFile _pchFile _hostFile _flagsVar) set (_flags ${${_flagsVar}}) - if ("${_compilerID}" STREQUAL "MSVC") + if (_compilerID MATCHES "MSVC") file (TO_NATIVE_PATH "${_prefixFile}" _prefixFileNative) file (TO_NATIVE_PATH "${_pchFile}" _pchFileNative) file (TO_NATIVE_PATH "${_hostFile}" _hostFileNative) @@ -1147,8 +1298,9 @@ function (cotire_add_pch_compilation_flags _language _compilerID _compilerVersio # return as a flag string set (_flags "/Yc\"${_prefixFileNative}\" /Fp\"${_pchFileNative}\" /FI\"${_prefixFileNative}\"") endif() - elseif ("${_compilerID}" MATCHES "GNU|Clang") + elseif (_compilerID MATCHES "GNU|Clang") # GCC / Clang options used + # -w disable all warnings # -x specify the source language # -c compile but do not link # -o place output in file @@ -1156,10 +1308,68 @@ function (cotire_add_pch_compilation_flags _language _compilerID _compilerVersio set (_xLanguage_CXX "c++-header") if (_flags) # append to list - list (APPEND _flags "-x" "${_xLanguage_${_language}}" "-c" "${_prefixFile}" -o "${_pchFile}") + list (APPEND _flags "-w" "-x" "${_xLanguage_${_language}}" "-c" "${_prefixFile}" -o "${_pchFile}") else() # return as a flag string - set (_flags "-x ${_xLanguage_${_language}} -c \"${_prefixFile}\" -o \"${_pchFile}\"") + set (_flags "-w -x ${_xLanguage_${_language}} -c \"${_prefixFile}\" -o \"${_pchFile}\"") + endif() + elseif (_compilerID MATCHES "Intel") + if (WIN32) + file (TO_NATIVE_PATH "${_prefixFile}" _prefixFileNative) + file (TO_NATIVE_PATH "${_pchFile}" _pchFileNative) + file (TO_NATIVE_PATH "${_hostFile}" _hostFileNative) + # Windows Intel options used + # /nologo do not display compiler version information + # /Yc create a precompiled header (PCH) file + # /Fp specify a path or file name for precompiled header files + # /FI tells the preprocessor to include a specified file name as the header file + # /TC process all source or unrecognized file types as C source files + # /TP process all source or unrecognized file types as C++ source files + # /Zs syntax check only + # /Wpch-messages enable diagnostics related to pre-compiled headers (requires Intel XE 2013 Update 2) + set (_sourceFileTypeC "/TC") + set (_sourceFileTypeCXX "/TP") + if (_flags) + # append to list + list (APPEND _flags /nologo "${_sourceFileType${_language}}" + "/Yc" "/Fp${_pchFileNative}" "/FI${_prefixFileNative}" /Zs "${_hostFileNative}") + if (NOT "${_compilerVersion}" VERSION_LESS "13.1.0") + list (APPEND _flags "/Wpch-messages") + endif() + else() + # return as a flag string + set (_flags "/Yc /Fp\"${_pchFileNative}\" /FI\"${_prefixFileNative}\"") + if (NOT "${_compilerVersion}" VERSION_LESS "13.1.0") + set (_flags "${_flags} /Wpch-messages") + endif() + endif() + else() + # Linux / Mac OS X Intel options used + # -pch-dir location for precompiled header files + # -pch-create name of the precompiled header (PCH) to create + # -Kc++ process all source or unrecognized file types as C++ source files + # -fsyntax-only check only for correct syntax + # -Wpch-messages enable diagnostics related to pre-compiled headers (requires Intel XE 2013 Update 2) + get_filename_component(_pchDir "${_pchFile}" PATH) + get_filename_component(_pchName "${_pchFile}" NAME) + set (_xLanguage_C "c-header") + set (_xLanguage_CXX "c++-header") + if (_flags) + # append to list + if ("${_language}" STREQUAL "CXX") + list (APPEND _flags -Kc++) + endif() + list (APPEND _flags "-include" "${_prefixFile}" "-pch-dir" "${_pchDir}" "-pch-create" "${_pchName}" "-fsyntax-only" "${_hostFile}") + if (NOT "${_compilerVersion}" VERSION_LESS "13.1.0") + list (APPEND _flags "-Wpch-messages") + endif() + else() + # return as a flag string + set (_flags "-include \"${_prefixFile}\" -pch-dir \"${_pchDir}\" -pch-create \"${_pchName}\"") + if (NOT "${_compilerVersion}" VERSION_LESS "13.1.0") + set (_flags "${_flags} -Wpch-messages") + endif() + endif() endif() else() message (FATAL_ERROR "Unsupported ${_language} compiler ${_compilerID} version ${_compilerVersion}.") @@ -1167,43 +1377,133 @@ function (cotire_add_pch_compilation_flags _language _compilerID _compilerVersio set (${_flagsVar} ${_flags} PARENT_SCOPE) endfunction() -function (cotire_add_pch_inclusion_flags _language _compilerID _compilerVersion _prefixFile _pchFile _flagsVar) +function (cotire_add_prefix_pch_inclusion_flags _language _compilerID _compilerVersion _prefixFile _pchFile _flagsVar) set (_flags ${${_flagsVar}}) - if ("${_compilerID}" STREQUAL "MSVC") + if (_compilerID MATCHES "MSVC") file (TO_NATIVE_PATH "${_prefixFile}" _prefixFileNative) - file (TO_NATIVE_PATH "${_pchFile}" _pchFileNative) # cl.exe options used # /Yu uses a precompiled header file during build # /Fp specifies precompiled header binary file name # /FI forces inclusion of file - if (_flags) - # append to list - list (APPEND _flags "/Yu${_prefixFileNative}" "/Fp${_pchFileNative}" "/FI${_prefixFileNative}") + if (_pchFile) + file (TO_NATIVE_PATH "${_pchFile}" _pchFileNative) + if (_flags) + # append to list + list (APPEND _flags "/Yu${_prefixFileNative}" "/Fp${_pchFileNative}" "/FI${_prefixFileNative}") + else() + # return as a flag string + set (_flags "/Yu\"${_prefixFileNative}\" /Fp\"${_pchFileNative}\" /FI\"${_prefixFileNative}\"") + endif() else() - # return as a flag string - set (_flags "/Yu\"${_prefixFileNative}\" /Fp\"${_pchFileNative}\" /FI\"${_prefixFileNative}\"") + # no precompiled header, force inclusion of prefix header + if (_flags) + # append to list + list (APPEND _flags "/FI${_prefixFileNative}") + else() + # return as a flag string + set (_flags "/FI\"${_prefixFileNative}\"") + endif() endif() - elseif ("${_compilerID}" STREQUAL "GNU") + elseif (_compilerID MATCHES "GNU") # GCC options used # -include process include file as the first line of the primary source file # -Winvalid-pch warns if precompiled header is found but cannot be used if (_flags) # append to list - list (APPEND _flags "-include" "${_prefixFile}" "-Winvalid-pch") + list (APPEND _flags "-Winvalid-pch" "-include" "${_prefixFile}") else() # return as a flag string - set (_flags "-include \"${_prefixFile}\" -Winvalid-pch") + set (_flags "-Winvalid-pch -include \"${_prefixFile}\"") endif() - elseif ("${_compilerID}" STREQUAL "Clang") + elseif (_compilerID MATCHES "Clang") # Clang options used # -include process include file as the first line of the primary source file + # -include-pch include precompiled header file # -Qunused-arguments don't emit warning for unused driver arguments - if (_flags) - # append to list - list (APPEND _flags "-include" "${_prefixFile}" "-Qunused-arguments") + if (_pchFile AND NOT CMAKE_${_language}_COMPILER MATCHES "ccache") + if (_flags) + # append to list + list (APPEND _flags "-Qunused-arguments" "-include-pch" "${_pchFile}") + else() + # return as a flag string + set (_flags "-Qunused-arguments -include-pch \"${_pchFile}\"") + endif() else() - # return as a flag string - set (_flags "-include \"${_prefixFile}\" -Qunused-arguments") + # no precompiled header, force inclusion of prefix header + # ccache requires the -include flag to be used in order to process precompiled header correctly + if (_flags) + # append to list + list (APPEND _flags "-Qunused-arguments" "-include" "${_prefixFile}") + else() + # return as a flag string + set (_flags "-Qunused-arguments -include \"${_prefixFile}\"") + endif() + endif() + elseif (_compilerID MATCHES "Intel") + if (WIN32) + file (TO_NATIVE_PATH "${_prefixFile}" _prefixFileNative) + # Windows Intel options used + # /Yu use a precompiled header (PCH) file + # /Fp specify a path or file name for precompiled header files + # /FI tells the preprocessor to include a specified file name as the header file + # /Wpch-messages enable diagnostics related to pre-compiled headers (requires Intel XE 2013 Update 2) + if (_pchFile) + file (TO_NATIVE_PATH "${_pchFile}" _pchFileNative) + if (_flags) + # append to list + list (APPEND _flags "/Yu" "/Fp${_pchFileNative}" "/FI${_prefixFileNative}") + if (NOT "${_compilerVersion}" VERSION_LESS "13.1.0") + list (APPEND _flags "/Wpch-messages") + endif() + else() + # return as a flag string + set (_flags "/Yu /Fp\"${_pchFileNative}\" /FI\"${_prefixFileNative}\"") + if (NOT "${_compilerVersion}" VERSION_LESS "13.1.0") + set (_flags "${_flags} /Wpch-messages") + endif() + endif() + else() + # no precompiled header, force inclusion of prefix header + if (_flags) + # append to list + list (APPEND _flags "/FI${_prefixFileNative}") + else() + # return as a flag string + set (_flags "/FI\"${_prefixFileNative}\"") + endif() + endif() + else() + # Linux / Mac OS X Intel options used + # -pch-dir location for precompiled header files + # -pch-use name of the precompiled header (PCH) to use + # -include process include file as the first line of the primary source file + # -Wpch-messages enable diagnostics related to pre-compiled headers (requires Intel XE 2013 Update 2) + if (_pchFile) + get_filename_component(_pchDir "${_pchFile}" PATH) + get_filename_component(_pchName "${_pchFile}" NAME) + if (_flags) + # append to list + list (APPEND _flags "-include" "${_prefixFile}" "-pch-dir" "${_pchDir}" "-pch-use" "${_pchName}") + if (NOT "${_compilerVersion}" VERSION_LESS "13.1.0") + list (APPEND _flags "-Wpch-messages") + endif() + else() + # return as a flag string + set (_flags "-include \"${_prefixFile}\" -pch-dir \"${_pchDir}\" -pch-use \"${_pchName}\"") + if (NOT "${_compilerVersion}" VERSION_LESS "13.1.0") + set (_flags "${_flags} -Wpch-messages") + endif() + endif() + else() + # no precompiled header, force inclusion of prefix header + if (_flags) + # append to list + list (APPEND _flags "-include" "${_prefixFile}") + else() + # return as a flag string + set (_flags "-include \"${_prefixFile}\"") + endif() + endif() endif() else() message (FATAL_ERROR "Unsupported ${_language} compiler ${_compilerID} version ${_compilerVersion}.") @@ -1223,16 +1523,17 @@ function (cotire_precompile_prefix_header _prefixFile _pchFile _hostFile) set (_option_COMPILER_ID "${CMAKE_${_option_LANGUAGE}_ID}") endif() cotire_init_compile_cmd(_cmd "${_option_LANGUAGE}" "${_option_COMPILER_EXECUTABLE}" "${_option_COMPILER_ARG1}") - cotire_add_definitions_to_cmd(_cmd ${_option_COMPILE_DEFINITIONS}) + cotire_add_definitions_to_cmd(_cmd "${_option_LANGUAGE}" ${_option_COMPILE_DEFINITIONS}) cotire_add_compile_flags_to_cmd(_cmd ${_option_COMPILE_FLAGS}) - cotire_add_includes_to_cmd(_cmd ${_option_INCLUDE_DIRECTORIES}) + cotire_add_includes_to_cmd(_cmd "${_option_LANGUAGE}" ${_option_INCLUDE_DIRECTORIES}) + cotire_add_frameworks_to_cmd(_cmd "${_option_LANGUAGE}" ${_option_INCLUDE_DIRECTORIES}) cotire_add_pch_compilation_flags( "${_option_LANGUAGE}" "${_option_COMPILER_ID}" "${_option_COMPILER_VERSION}" "${_prefixFile}" "${_pchFile}" "${_hostFile}" _cmd) if (COTIRE_VERBOSE) message (STATUS "execute_process: ${_cmd}") endif() - if ("${_option_COMPILER_ID}" STREQUAL "MSVC") + if (_option_COMPILER_ID MATCHES "MSVC") if (COTIRE_DEBUG) message (STATUS "clearing VS_UNICODE_OUTPUT") endif() @@ -1245,43 +1546,62 @@ function (cotire_precompile_prefix_header _prefixFile _pchFile _hostFile) endif() endfunction() -function (cotire_check_precompiled_header_support _language _target _msgVar) - if (MSVC) +function (cotire_check_precompiled_header_support _language _targetSourceDir _target _msgVar) + set (_unsupportedCompiler + "Precompiled headers not supported for ${_language} compiler ${CMAKE_${_language}_COMPILER_ID}") + if (CMAKE_${_language}_COMPILER_ID MATCHES "MSVC") # supported since Visual Studio C++ 6.0 # and CMake does not support an earlier version set (${_msgVar} "" PARENT_SCOPE) - elseif ("${CMAKE_${_language}_COMPILER_ID}" STREQUAL "GNU") - # GCC PCH support requires GCC >= 3.4 + elseif (CMAKE_${_language}_COMPILER_ID MATCHES "GNU") + # GCC PCH support requires version >= 3.4 cotire_determine_compiler_version("${_language}" COTIRE_${_language}_COMPILER) if ("${COTIRE_${_language}_COMPILER_VERSION}" MATCHES ".+" AND "${COTIRE_${_language}_COMPILER_VERSION}" VERSION_LESS "3.4.0") - set (${_msgVar} - "Precompiled headers not supported for ${_language} compiler ${CMAKE_${_language}_COMPILER_ID} version ${COTIRE_${_language}_COMPILER_VERSION}." - PARENT_SCOPE) + set (${_msgVar} "${_unsupportedCompiler} version ${COTIRE_${_language}_COMPILER_VERSION}." PARENT_SCOPE) else() set (${_msgVar} "" PARENT_SCOPE) endif() - elseif ("${CMAKE_${_language}_COMPILER_ID}" STREQUAL "Clang") - # Clang has PCH support + elseif (CMAKE_${_language}_COMPILER_ID MATCHES "Clang") + # all Clang versions have PCH support set (${_msgVar} "" PARENT_SCOPE) + elseif (CMAKE_${_language}_COMPILER_ID MATCHES "Intel") + # Intel PCH support requires version >= 8.0.0 + cotire_determine_compiler_version("${_language}" COTIRE_${_language}_COMPILER) + if ("${COTIRE_${_language}_COMPILER_VERSION}" MATCHES ".+" AND + "${COTIRE_${_language}_COMPILER_VERSION}" VERSION_LESS "8.0.0") + set (${_msgVar} "${_unsupportedCompiler} version ${COTIRE_${_language}_COMPILER_VERSION}." PARENT_SCOPE) + else() + set (${_msgVar} "" PARENT_SCOPE) + endif() else() - set (${_msgVar} "Unsupported ${_language} compiler ${CMAKE_${_language}_COMPILER_ID}." PARENT_SCOPE) + set (${_msgVar} "${_unsupportedCompiler}." PARENT_SCOPE) + endif() + if (CMAKE_${_language}_COMPILER MATCHES "ccache") + if (NOT "$ENV{CCACHE_SLOPPINESS}" MATCHES "time_macros") + set (${_msgVar} + "ccache requires the environment variable CCACHE_SLOPPINESS to be set to time_macros." + PARENT_SCOPE) + endif() endif() if (APPLE) - # PCH compilation not supported by GCC / Clang when multiple build architectures (e.g., i386, x86_64) are selected + # PCH compilation not supported by GCC / Clang for multi-architecture builds (e.g., i386, x86_64) if (CMAKE_CONFIGURATION_TYPES) set (_configs ${CMAKE_CONFIGURATION_TYPES}) - else() + elseif (CMAKE_BUILD_TYPE) set (_configs ${CMAKE_BUILD_TYPE}) + else() + set (_configs "None") endif() foreach (_config ${_configs}) - cotire_get_target_compile_flags("${_config}" "${_language}" "${CMAKE_CURRENT_SOURCE_DIR}" "${_target}" _targetFlags) - cotire_filter_compile_flags("arch" _architectures _ignore ${_targetFlags}) + set (_targetFlags "") + cotire_get_target_compile_flags("${_config}" "${_language}" "${_targetSourceDir}" "${_target}" _targetFlags) + cotire_filter_compile_flags("${_language}" "arch" _architectures _ignore ${_targetFlags}) list (LENGTH _architectures _numberOfArchitectures) if (_numberOfArchitectures GREATER 1) string (REPLACE ";" ", " _architectureStr "${_architectures}") set (${_msgVar} - "Precompiled headers not supported on Darwin for multiple architecture builds (${_architectureStr})." + "Precompiled headers not supported on Darwin for multi-architecture builds (${_architectureStr})." PARENT_SCOPE) break() endif() @@ -1293,11 +1613,31 @@ macro (cotire_get_intermediate_dir _cotireDir) get_filename_component(${_cotireDir} "${CMAKE_CURRENT_BINARY_DIR}/${CMAKE_CFG_INTDIR}/${COTIRE_INTDIR}" ABSOLUTE) endmacro() -function (cotire_make_untiy_source_file_paths _language _target _maxIncludes _unityFilesVar) - set (_sourceFiles ${ARGN}) - list (LENGTH _sourceFiles _numberOfSources) +macro (cotire_setup_file_extension_variables) set (_unityFileExt_C ".c") set (_unityFileExt_CXX ".cxx") + set (_prefixFileExt_C ".h") + set (_prefixFileExt_CXX ".hxx") +endmacro() + +function (cotire_make_single_unity_source_file_path _language _target _unityFileVar) + cotire_setup_file_extension_variables() + if (NOT DEFINED _unityFileExt_${_language}) + set (${_unityFileVar} "" PARENT_SCOPE) + return() + endif() + set (_unityFileBaseName "${_target}_${_language}${COTIRE_UNITY_SOURCE_FILENAME_SUFFIX}") + set (_unityFileName "${_unityFileBaseName}${_unityFileExt_${_language}}") + cotire_get_intermediate_dir(_baseDir) + set (_unityFile "${_baseDir}/${_unityFileName}") + set (${_unityFileVar} "${_unityFile}" PARENT_SCOPE) + if (COTIRE_DEBUG) + message(STATUS "${_unityFile}") + endif() +endfunction() + +function (cotire_make_unity_source_file_paths _language _target _maxIncludes _unityFilesVar) + cotire_setup_file_extension_variables() if (NOT DEFINED _unityFileExt_${_language}) set (${_unityFileVar} "" PARENT_SCOPE) return() @@ -1307,11 +1647,13 @@ function (cotire_make_untiy_source_file_paths _language _target _maxIncludes _un set (_startIndex 0) set (_index 0) set (_unityFiles "") + set (_sourceFiles ${ARGN}) foreach (_sourceFile ${_sourceFiles}) get_source_file_property(_startNew "${_sourceFile}" COTIRE_START_NEW_UNITY_SOURCE) math (EXPR _unityFileCount "${_index} - ${_startIndex}") if (_startNew OR (_maxIncludes GREATER 0 AND NOT _unityFileCount LESS _maxIncludes)) if (_index GREATER 0) + # start new unity file segment math (EXPR _endIndex "${_index} - 1") set (_unityFileName "${_unityFileBaseName}_${_startIndex}_${_endIndex}${_unityFileExt_${_language}}") list (APPEND _unityFiles "${_baseDir}/${_unityFileName}") @@ -1320,10 +1662,12 @@ function (cotire_make_untiy_source_file_paths _language _target _maxIncludes _un endif() math (EXPR _index "${_index} + 1") endforeach() + list (LENGTH _sourceFiles _numberOfSources) if (_startIndex EQUAL 0) - set (_unityFileName "${_unityFileBaseName}${_unityFileExt_${_language}}") - list (APPEND _unityFiles "${_baseDir}/${_unityFileName}") + # there is only a single unity file + cotire_make_single_unity_source_file_path(${_language} ${_target} _unityFiles) elseif (_startIndex LESS _numberOfSources) + # end with final unity file segment math (EXPR _endIndex "${_index} - 1") set (_unityFileName "${_unityFileBaseName}_${_startIndex}_${_endIndex}${_unityFileExt_${_language}}") list (APPEND _unityFiles "${_baseDir}/${_unityFileName}") @@ -1334,9 +1678,21 @@ function (cotire_make_untiy_source_file_paths _language _target _maxIncludes _un endif() endfunction() +function (cotire_unity_to_prefix_file_path _language _target _unityFile _prefixFileVar) + cotire_setup_file_extension_variables() + if (NOT DEFINED _unityFileExt_${_language}) + set (${_prefixFileVar} "" PARENT_SCOPE) + return() + endif() + set (_unityFileBaseName "${_target}_${_language}${COTIRE_UNITY_SOURCE_FILENAME_SUFFIX}") + set (_prefixFileBaseName "${_target}_${_language}${COTIRE_PREFIX_HEADER_FILENAME_SUFFIX}") + string (REPLACE "${_unityFileBaseName}" "${_prefixFileBaseName}" _prefixFile "${_unityFile}") + string (REGEX REPLACE "${_unityFileExt_${_language}}$" "${_prefixFileExt_${_language}}" _prefixFile "${_prefixFile}") + set (${_prefixFileVar} "${_prefixFile}" PARENT_SCOPE) +endfunction() + function (cotire_make_prefix_file_name _language _target _prefixFileBaseNameVar _prefixFileNameVar) - set (_prefixFileExt_C ".h") - set (_prefixFileExt_CXX ".hxx") + cotire_setup_file_extension_variables() if (NOT _language) set (_prefixFileBaseName "${_target}${COTIRE_PREFIX_HEADER_FILENAME_SUFFIX}") set (_prefixFileName "${_prefixFileBaseName}${_prefixFileExt_C}") @@ -1358,30 +1714,36 @@ function (cotire_make_prefix_file_path _language _target _prefixFileVar) if (NOT _language) set (_language "C") endif() - if (MSVC OR "${CMAKE_${_language}_COMPILER_ID}" MATCHES "GNU|Clang") + if (MSVC OR CMAKE_${_language}_COMPILER_ID MATCHES "GNU|Clang|Intel") cotire_get_intermediate_dir(_baseDir) set (${_prefixFileVar} "${_baseDir}/${_prefixFileName}" PARENT_SCOPE) endif() endif() endfunction() -function (cotire_make_pch_file_path _language _target _pchFileVar) +function (cotire_make_pch_file_path _language _targetSourceDir _target _pchFileVar) cotire_make_prefix_file_name("${_language}" "${_target}" _prefixFileBaseName _prefixFileName) set (${_pchFileVar} "" PARENT_SCOPE) if (_prefixFileBaseName AND _prefixFileName) - cotire_check_precompiled_header_support("${_language}" "${_target}" _msg) + cotire_check_precompiled_header_support("${_language}" "${_targetSourceDir}" "${_target}" _msg) if (NOT _msg) if (XCODE) # For Xcode, we completely hand off the compilation of the prefix header to the IDE return() endif() cotire_get_intermediate_dir(_baseDir) - if (MSVC) + if (CMAKE_${_language}_COMPILER_ID MATCHES "MSVC") # MSVC uses the extension .pch added to the prefix header base name set (${_pchFileVar} "${_baseDir}/${_prefixFileBaseName}.pch" PARENT_SCOPE) - elseif ("${CMAKE_${_language}_COMPILER_ID}" MATCHES "GNU|Clang") - # GCC / Clang look for a precompiled header corresponding to the prefix header with the extension .gch appended + elseif (CMAKE_${_language}_COMPILER_ID MATCHES "Clang") + # Clang looks for a precompiled header corresponding to the prefix header with the extension .pch appended + set (${_pchFileVar} "${_baseDir}/${_prefixFileName}.pch" PARENT_SCOPE) + elseif (CMAKE_${_language}_COMPILER_ID MATCHES "GNU") + # GCC looks for a precompiled header corresponding to the prefix header with the extension .gch appended set (${_pchFileVar} "${_baseDir}/${_prefixFileName}.gch" PARENT_SCOPE) + elseif (CMAKE_${_language}_COMPILER_ID MATCHES "Intel") + # Intel uses the extension .pchi added to the prefix header base name + set (${_pchFileVar} "${_baseDir}/${_prefixFileBaseName}.pchi" PARENT_SCOPE) endif() endif() endif() @@ -1411,10 +1773,9 @@ function (cotire_select_unity_source_files _unityFile _sourcesVar) endfunction() function (cotire_get_unity_source_dependencies _language _target _dependencySourcesVar) - get_target_property(_targetSourceFiles ${_target} SOURCES) set (_dependencySources "") # depend on target's generated source files - cotire_get_objects_with_property_on(_generatedSources GENERATED SOURCE ${_targetSourceFiles}) + cotire_get_objects_with_property_on(_generatedSources GENERATED SOURCE ${ARGN}) if (_generatedSources) # but omit all generated source files that have the COTIRE_EXCLUDED property set to true cotire_get_objects_with_property_on(_excludedGeneratedSources COTIRE_EXCLUDED SOURCE ${_generatedSources}) @@ -1437,22 +1798,29 @@ function (cotire_get_unity_source_dependencies _language _target _dependencySour endfunction() function (cotire_get_prefix_header_dependencies _language _target _dependencySourcesVar) - get_target_property(_targetSourceFiles ${_target} SOURCES) # depend on target source files marked with custom COTIRE_DEPENDENCY property set (_dependencySources "") - cotire_get_objects_with_property_on(_dependencySources COTIRE_DEPENDENCY SOURCE ${_targetSourceFiles}) + cotire_get_objects_with_property_on(_dependencySources COTIRE_DEPENDENCY SOURCE ${ARGN}) + if (CMAKE_${_language}_COMPILER_ID MATCHES "Clang") + # Clang raises a fatal error if a file is not found during preprocessing + # thus we depend on target's generated source files for prefix header generation + cotire_get_objects_with_property_on(_generatedSources GENERATED SOURCE ${ARGN}) + if (_generatedSources) + list (APPEND _dependencySources ${_generatedSources}) + endif() + endif() if (COTIRE_DEBUG AND _dependencySources) message (STATUS "${_language} ${_target} prefix header DEPENDS ${_dependencySources}") endif() set (${_dependencySourcesVar} ${_dependencySources} PARENT_SCOPE) endfunction() -function (cotire_generate_target_script _language _configurations _target _targetScriptVar) +function (cotire_generate_target_script _language _configurations _targetSourceDir _targetBinaryDir _target _targetScriptVar) set (COTIRE_TARGET_SOURCES ${ARGN}) get_filename_component(_moduleName "${COTIRE_CMAKE_MODULE_FILE}" NAME) set (_targetCotireScript "${CMAKE_CURRENT_BINARY_DIR}/${_target}_${_language}_${_moduleName}") - cotire_get_prefix_header_dependencies(${_language} ${_target} COTIRE_TARGET_PREFIX_DEPENDS) - cotire_get_unity_source_dependencies(${_language} ${_target} COTIRE_TARGET_UNITY_DEPENDS) + cotire_get_prefix_header_dependencies(${_language} ${_target} COTIRE_TARGET_PREFIX_DEPENDS ${COTIRE_TARGET_SOURCES}) + cotire_get_unity_source_dependencies(${_language} ${_target} COTIRE_TARGET_UNITY_DEPENDS ${COTIRE_TARGET_SOURCES}) # set up variables to be configured set (COTIRE_TARGET_LANGUAGE "${_language}") cotire_determine_compiler_version("${COTIRE_TARGET_LANGUAGE}" COTIRE_${_language}_COMPILER) @@ -1469,11 +1837,11 @@ function (cotire_generate_target_script _language _configurations _target _targe foreach (_config ${_configurations}) string (TOUPPER "${_config}" _upperConfig) cotire_get_target_include_directories( - "${_config}" "${_language}" "${CMAKE_CURRENT_SOURCE_DIR}" "${_target}" COTIRE_TARGET_INCLUDE_DIRECTORIES_${_upperConfig}) + "${_config}" "${_language}" "${_targetSourceDir}" "${_targetBinaryDir}" "${_target}" COTIRE_TARGET_INCLUDE_DIRECTORIES_${_upperConfig}) cotire_get_target_compile_definitions( - "${_config}" "${_language}" "${CMAKE_CURRENT_SOURCE_DIR}" "${_target}" COTIRE_TARGET_COMPILE_DEFINITIONS_${_upperConfig}) + "${_config}" "${_language}" "${_targetSourceDir}" "${_target}" COTIRE_TARGET_COMPILE_DEFINITIONS_${_upperConfig}) cotire_get_target_compiler_flags( - "${_config}" "${_language}" "${CMAKE_CURRENT_SOURCE_DIR}" "${_target}" COTIRE_TARGET_COMPILE_FLAGS_${_upperConfig}) + "${_config}" "${_language}" "${_targetSourceDir}" "${_target}" COTIRE_TARGET_COMPILE_FLAGS_${_upperConfig}) cotire_get_source_files_compile_definitions( "${_config}" "${_language}" COTIRE_TARGET_SOURCES_COMPILE_DEFINITIONS_${_upperConfig} ${COTIRE_TARGET_SOURCES}) endforeach() @@ -1495,11 +1863,11 @@ function (cotire_generate_target_script _language _configurations _target _targe set (${_targetScriptVar} "${_targetCotireScript}" PARENT_SCOPE) endfunction() -function (cotire_setup_pch_file_compilation _language _targetScript _prefixFile _pchFile) +function (cotire_setup_pch_file_compilation _language _target _targetSourceDir _targetScript _prefixFile _pchFile) set (_sourceFiles ${ARGN}) - if (MSVC) - # for Visual Studio, we attach the precompiled header compilation to the first source file - # the remaining files include the precompiled header, see cotire_setup_prefix_file_inclusion + if (CMAKE_${_language}_COMPILER_ID MATCHES "MSVC|Intel") + # for Visual Studio and Intel, we attach the precompiled header compilation to the first source file + # the remaining files include the precompiled header, see cotire_setup_pch_file_inclusion if (_sourceFiles) file (TO_NATIVE_PATH "${_prefixFile}" _prefixFileNative) file (TO_NATIVE_PATH "${_pchFile}" _pchFileNative) @@ -1507,12 +1875,14 @@ function (cotire_setup_pch_file_compilation _language _targetScript _prefixFile set (_flags "") cotire_determine_compiler_version("${_language}" COTIRE_${_language}_COMPILER) cotire_add_pch_compilation_flags( - "${_language}" "MSVC" "${COTIRE_${_language}_COMPILER_VERSION}" + "${_language}" "${CMAKE_${_language}_COMPILER_ID}" "${COTIRE_${_language}_COMPILER_VERSION}" "${_prefixFile}" "${_pchFile}" "${_hostFile}" _flags) set_property (SOURCE ${_hostFile} APPEND_STRING PROPERTY COMPILE_FLAGS " ${_flags} ") set_property (SOURCE ${_hostFile} APPEND PROPERTY OBJECT_OUTPUTS "${_pchFile}") # make first source file depend on prefix header set_property (SOURCE ${_hostFile} APPEND PROPERTY OBJECT_DEPENDS "${_prefixFile}") + # mark first source file as cotired to prevent it from being used in another cotired target + set_property (SOURCE ${_hostFile} PROPERTY COTIRE_TARGET "${_target}") endif() elseif ("${CMAKE_GENERATOR}" MATCHES "Makefiles|Ninja") # for makefile based generator, we add a custom command to precompile the prefix header @@ -1529,16 +1899,16 @@ function (cotire_setup_pch_file_compilation _language _targetScript _prefixFile COMMAND ${_cmds} DEPENDS "${_prefixFile}" IMPLICIT_DEPENDS ${_language} "${_prefixFile}" - WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" + WORKING_DIRECTORY "${_targetSourceDir}" COMMENT "Building ${_language} precompiled header ${_pchFileRelPath}" VERBATIM) endif() endif() endfunction() -function (cotire_setup_prefix_file_inclusion _language _target _wholeTarget _prefixFile _pchFile) +function (cotire_setup_pch_file_inclusion _language _target _wholeTarget _prefixFile _pchFile) set (_sourceFiles ${ARGN}) - if (MSVC) - # for Visual Studio, we include the precompiled header in all but the first source file + if (CMAKE_${_language}_COMPILER_ID MATCHES "MSVC|Intel") + # for Visual Studio and Intel, we include the precompiled header in all but the first source file # the first source file does the precompiled header compilation, see cotire_setup_pch_file_compilation list (LENGTH _sourceFiles _numberOfSourceFiles) if (_numberOfSourceFiles GREATER 1) @@ -1547,8 +1917,8 @@ function (cotire_setup_prefix_file_inclusion _language _target _wholeTarget _pre list (REMOVE_AT _sourceFiles 0) set (_flags "") cotire_determine_compiler_version("${_language}" COTIRE_${_language}_COMPILER) - cotire_add_pch_inclusion_flags( - "${_language}" "MSVC" "${COTIRE_${_language}_COMPILER_VERSION}" + cotire_add_prefix_pch_inclusion_flags( + "${_language}" "${CMAKE_${_language}_COMPILER_ID}" "${COTIRE_${_language}_COMPILER_VERSION}" "${_prefixFile}" "${_pchFile}" _flags) set_property (SOURCE ${_sourceFiles} APPEND_STRING PROPERTY COMPILE_FLAGS " ${_flags} ") # make source files depend on precompiled header @@ -1560,7 +1930,7 @@ function (cotire_setup_prefix_file_inclusion _language _target _wholeTarget _pre # of the source files, if this is a multi-language target or has excluded files set (_flags "") cotire_determine_compiler_version("${_language}" COTIRE_${_language}_COMPILER) - cotire_add_pch_inclusion_flags( + cotire_add_prefix_pch_inclusion_flags( "${_language}" "${CMAKE_${_language}_COMPILER_ID}" "${COTIRE_${_language}_COMPILER_VERSION}" "${_prefixFile}" "${_pchFile}" _flags) set_property (SOURCE ${_sourceFiles} APPEND_STRING PROPERTY COMPILE_FLAGS " ${_flags} ") @@ -1572,6 +1942,21 @@ function (cotire_setup_prefix_file_inclusion _language _target _wholeTarget _pre endif() endfunction() +function (cotire_setup_prefix_file_inclusion _language _target _prefixFile) + set (_sourceFiles ${ARGN}) + # force the inclusion of the prefix header for the given source files + set (_flags "") + cotire_determine_compiler_version("${_language}" COTIRE_${_language}_COMPILER) + cotire_add_prefix_pch_inclusion_flags( + "${_language}" "${CMAKE_${_language}_COMPILER_ID}" "${COTIRE_${_language}_COMPILER_VERSION}" + "${_prefixFile}" "" _flags) + set_property (SOURCE ${_sourceFiles} APPEND_STRING PROPERTY COMPILE_FLAGS " ${_flags} ") + # mark sources as cotired to prevent them from being used in another cotired target + set_source_files_properties(${_sourceFiles} PROPERTIES COTIRE_TARGET "${_target}") + # make source files depend on prefix header + set_property (SOURCE ${_sourceFiles} APPEND PROPERTY OBJECT_DEPENDS "${_prefixFile}") +endfunction() + function (cotire_get_first_set_property_value _propertyValueVar _type _object) set (_properties ${ARGN}) foreach (_property ${_properties}) @@ -1584,11 +1969,53 @@ function (cotire_get_first_set_property_value _propertyValueVar _type _object) set (${_propertyValueVar} "" PARENT_SCOPE) endfunction() -function (cotire_setup_target_pch_usage _languages _target _wholeTarget) - if (MSVC) - # for Visual Studio, precompiled header inclusion is always done on the source file level - # see cotire_setup_prefix_file_inclusion - elseif (XCODE) +function (cotire_setup_combine_command _language _sourceDir _targetScript _joinedFile _cmdsVar) + set (_files ${ARGN}) + set (_filesPaths "") + foreach (_file ${_files}) + if (IS_ABSOLUTE "${_file}") + set (_filePath "${_file}") + else() + get_filename_component(_filePath "${_sourceDir}/${_file}" ABSOLUTE) + endif() + file (RELATIVE_PATH _fileRelPath "${_sourceDir}" "${_filePath}") + if (NOT IS_ABSOLUTE "${_fileRelPath}" AND NOT "${_fileRelPath}" MATCHES "^\\.\\.") + list (APPEND _filesPaths "${_fileRelPath}") + else() + list (APPEND _filesPaths "${_filePath}") + endif() + endforeach() + cotire_set_cmd_to_prologue(_prefixCmd) + list (APPEND _prefixCmd -P "${COTIRE_CMAKE_MODULE_FILE}" "combine") + if (_targetScript) + list (APPEND _prefixCmd "${_targetScript}") + endif() + list (APPEND _prefixCmd "${_joinedFile}" ${_filesPaths}) + if (COTIRE_DEBUG) + message (STATUS "add_custom_command: OUTPUT ${_joinedFile} COMMAND ${_prefixCmd} DEPENDS ${_files}") + endif() + set_property (SOURCE "${_joinedFile}" PROPERTY GENERATED TRUE) + file (RELATIVE_PATH _joinedFileRelPath "${CMAKE_BINARY_DIR}" "${_joinedFile}") + get_filename_component(_joinedFileName "${_joinedFileRelPath}" NAME_WE) + if (_language AND _joinedFileName MATCHES "${COTIRE_UNITY_SOURCE_FILENAME_SUFFIX}$") + set (_comment "Generating ${_language} unity source ${_joinedFileRelPath}") + elseif (_language AND _joinedFileName MATCHES "${COTIRE_UNITY_SOURCE_FILENAME_SUFFIX}$") + set (_comment "Generating ${_language} prefix header ${_joinedFileRelPath}") + else() + set (_comment "Generating ${_joinedFileRelPath}") + endif() + add_custom_command( + OUTPUT "${_joinedFile}" + COMMAND ${_prefixCmd} + DEPENDS ${_files} + COMMENT "${_comment}" + WORKING_DIRECTORY "${_sourceDir}" VERBATIM) + list (APPEND ${_cmdsVar} COMMAND ${_prefixCmd}) + set (${_cmdsVar} ${${_cmdsVar}} PARENT_SCOPE) +endfunction() + +function (cotire_setup_target_pch_usage _languages _targetSourceDir _target _wholeTarget) + if (XCODE) # for Xcode, we attach a pre-build action to generate the unity sources and prefix headers # if necessary, we also generate a single prefix header which includes all language specific prefix headers set (_prefixFiles "") @@ -1602,7 +2029,7 @@ function (cotire_setup_target_pch_usage _languages _target _wholeTarget) list (LENGTH _prefixFiles _numberOfPrefixFiles) if (_numberOfPrefixFiles GREATER 1) cotire_make_prefix_file_path("" ${_target} _prefixHeader) - cotire_setup_combine_command(${_target} "${_prefixHeader}" "${_prefixFiles}" _cmds) + cotire_setup_combine_command("" "${_targetSourceDir}" "" "${_prefixHeader}" _cmds ${_prefixFiles}) else() set (_prefixHeader "${_prefixFiles}") endif() @@ -1611,61 +2038,74 @@ function (cotire_setup_target_pch_usage _languages _target _wholeTarget) endif() add_custom_command(TARGET "${_target}" PRE_BUILD ${_cmds} - WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" + WORKING_DIRECTORY "${_targetSourceDir}" COMMENT "Updating target ${_target} prefix headers" VERBATIM) # make Xcode precompile the generated prefix header with ProcessPCH and ProcessPCH++ set_target_properties(${_target} PROPERTIES XCODE_ATTRIBUTE_GCC_PRECOMPILE_PREFIX_HEADER "YES") set_target_properties(${_target} PROPERTIES XCODE_ATTRIBUTE_GCC_PREFIX_HEADER "${_prefixHeader}") elseif ("${CMAKE_GENERATOR}" MATCHES "Makefiles|Ninja") + # for makefile based generator, we force inclusion of the prefix header for all target source files + # if this is a single-language target without any excluded files if (_wholeTarget) - # for makefile based generator, we force inclusion of the prefix header for all target source files - # if this is a single-language target without any excluded files set (_language "${_languages}") - get_property(_prefixFile TARGET ${_target} PROPERTY COTIRE_${_language}_PREFIX_HEADER) - get_property(_pchFile TARGET ${_target} PROPERTY COTIRE_${_language}_PRECOMPILED_HEADER) - set (_flags "") - cotire_determine_compiler_version("${_language}" COTIRE_${_language}_COMPILER) - cotire_add_pch_inclusion_flags( - "${_language}" "${CMAKE_${_language}_COMPILER_ID}" "${COTIRE_${_language}_COMPILER_VERSION}" - "${_prefixFile}" "${_pchFile}" _flags) - set_property (TARGET ${_target} APPEND_STRING PROPERTY COMPILE_FLAGS " ${_flags} ") + # for Visual Studio and Intel, precompiled header inclusion is always done on the source file level + # see cotire_setup_pch_file_inclusion + if (NOT CMAKE_${_language}_COMPILER_ID MATCHES "MSVC|Intel") + get_property(_prefixFile TARGET ${_target} PROPERTY COTIRE_${_language}_PREFIX_HEADER) + get_property(_pchFile TARGET ${_target} PROPERTY COTIRE_${_language}_PRECOMPILED_HEADER) + set (_flags "") + cotire_determine_compiler_version("${_language}" COTIRE_${_language}_COMPILER) + cotire_add_prefix_pch_inclusion_flags( + "${_language}" "${CMAKE_${_language}_COMPILER_ID}" "${COTIRE_${_language}_COMPILER_VERSION}" + "${_prefixFile}" "${_pchFile}" _flags) + set_property(TARGET ${_target} APPEND_STRING PROPERTY COMPILE_FLAGS " ${_flags} ") + endif() endif() endif() endfunction() -function (cotire_setup_unity_generation_commands _language _target _targetScript _unityFiles _cmdsVar) +function (cotire_setup_unity_generation_commands _language _targetSourceDir _target _targetScript _unityFiles _cmdsVar) set (_dependencySources "") cotire_get_unity_source_dependencies(${_language} ${_target} _dependencySources ${ARGN}) foreach (_unityFile ${_unityFiles}) file (RELATIVE_PATH _unityFileRelPath "${CMAKE_BINARY_DIR}" "${_unityFile}") set_property (SOURCE "${_unityFile}" PROPERTY GENERATED TRUE) + # set up compiled unity source dependencies + # this ensures that missing source files are generated before the unity file is compiled + if (COTIRE_DEBUG AND _dependencySources) + message (STATUS "${_unityFile} OBJECT_DEPENDS ${_dependencySources}") + endif() + if (_dependencySources) + set_property (SOURCE "${_unityFile}" PROPERTY OBJECT_DEPENDS ${_dependencySources}) + endif() + if (WIN32 AND CMAKE_${_language}_COMPILER_ID MATCHES "MSVC|Intel") + # unity file compilation results in potentially huge object file, thus use /bigobj by default unter MSVC and Windows Intel + set_property (SOURCE "${_unityFile}" APPEND_STRING PROPERTY COMPILE_FLAGS "/bigobj") + endif() cotire_set_cmd_to_prologue(_unityCmd) list (APPEND _unityCmd -P "${COTIRE_CMAKE_MODULE_FILE}" "unity" "${_targetScript}" "${_unityFile}") if (COTIRE_DEBUG) - message (STATUS "add_custom_command: OUTPUT ${_unityFile} COMMAND ${_unityCmd} DEPENDS ${_targetScript} ${_dependencySources}") + message (STATUS "add_custom_command: OUTPUT ${_unityFile} COMMAND ${_unityCmd} DEPENDS ${_targetScript}") endif() add_custom_command( OUTPUT "${_unityFile}" COMMAND ${_unityCmd} - DEPENDS "${_targetScript}" ${_dependencySources} + DEPENDS "${_targetScript}" COMMENT "Generating ${_language} unity source ${_unityFileRelPath}" - WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" VERBATIM) + WORKING_DIRECTORY "${_targetSourceDir}" VERBATIM) list (APPEND ${_cmdsVar} COMMAND ${_unityCmd}) endforeach() - set (${_cmdsVar} ${${_cmdsVar}} PARENT_SCOPE) -endfunction() - -function (cotire_setup_prefix_generation_command _language _target _targetScript _prefixFile _unityFiles _cmdsVar) - set (_sourceFiles ${ARGN}) list (LENGTH _unityFiles _numberOfUnityFiles) if (_numberOfUnityFiles GREATER 1) # create a joint unity file from all unity file segments - cotire_make_untiy_source_file_paths(${_language} ${_target} 0 _unityFile ${_unityFiles}) - cotire_setup_combine_command(${_target} "${_unityFile}" "${_unityFiles}" ${_cmdsVar}) - else() - set (_unityFile "${_unityFiles}") + cotire_make_single_unity_source_file_path(${_language} ${_target} _unityFile) + cotire_setup_combine_command(${_language} "${_targetSourceDir}" "${_targetScript}" "${_unityFile}" ${_cmdsVar} ${_unityFiles}) endif() - file (RELATIVE_PATH _prefixFileRelPath "${CMAKE_BINARY_DIR}" "${_prefixFile}") + set (${_cmdsVar} ${${_cmdsVar}} PARENT_SCOPE) +endfunction() + +function (cotire_setup_single_prefix_generation_command _language _target _targetSourceDir _targetScript _prefixFile _unityFile _cmdsVar) + set (_sourceFiles ${ARGN}) set (_dependencySources "") cotire_get_prefix_header_dependencies(${_language} ${_target} _dependencySources ${_sourceFiles}) cotire_set_cmd_to_prologue(_prefixCmd) @@ -1674,8 +2114,9 @@ function (cotire_setup_prefix_generation_command _language _target _targetScript if (COTIRE_DEBUG) message (STATUS "add_custom_command: OUTPUT ${_prefixFile} COMMAND ${_prefixCmd} DEPENDS ${_targetScript} ${_unityFile} ${_dependencySources}") endif() + file (RELATIVE_PATH _prefixFileRelPath "${CMAKE_BINARY_DIR}" "${_prefixFile}") add_custom_command( - OUTPUT "${_prefixFile}" + OUTPUT "${_prefixFile}" "${_prefixFile}.log" COMMAND ${_prefixCmd} DEPENDS "${_targetScript}" "${_unityFile}" ${_dependencySources} COMMENT "Generating ${_language} prefix header ${_prefixFileRelPath}" @@ -1684,26 +2125,19 @@ function (cotire_setup_prefix_generation_command _language _target _targetScript set (${_cmdsVar} ${${_cmdsVar}} PARENT_SCOPE) endfunction() -function (cotire_setup_combine_command _target _joinedFile _files _cmdsVar) - file (RELATIVE_PATH _joinedFileRelPath "${CMAKE_BINARY_DIR}" "${_joinedFile}") - set (_filesRelPaths "") - foreach (_file ${_files}) - file (RELATIVE_PATH _fileRelPath "${CMAKE_BINARY_DIR}" "${_file}") - list (APPEND _filesRelPaths "${_fileRelPath}") - endforeach() - cotire_set_cmd_to_prologue(_prefixCmd) - list (APPEND _prefixCmd -P "${COTIRE_CMAKE_MODULE_FILE}" "combine" "${_joinedFile}" ${_filesRelPaths}) - if (COTIRE_DEBUG) - message (STATUS "add_custom_command: OUTPUT ${_joinedFile} COMMAND ${_prefixCmd} DEPENDS ${_files}") +function (cotire_setup_multi_prefix_generation_command _language _target _targetSourceDir _targetScript _prefixFile _unityFiles _cmdsVar) + set (_sourceFiles ${ARGN}) + list (LENGTH _unityFiles _numberOfUnityFiles) + if (_numberOfUnityFiles GREATER 1) + cotire_make_single_unity_source_file_path(${_language} ${_target} _unityFile) + cotire_setup_single_prefix_generation_command( + ${_language} ${_target} "${_targetSourceDir}" "${_targetScript}" + "${_prefixFile}" "${_unityFile}" ${_cmdsVar} ${_sourceFiles}) + else() + cotire_setup_single_prefix_generation_command( + ${_language} ${_target} "${_targetSourceDir}" "${_targetScript}" + "${_prefixFile}" "${_unityFiles}" ${_cmdsVar} ${_sourceFiles}) endif() - set_property (SOURCE "${_joinedFile}" PROPERTY GENERATED TRUE) - add_custom_command( - OUTPUT "${_joinedFile}" - COMMAND ${_prefixCmd} - DEPENDS ${_files} - COMMENT "Generating ${_joinedFileRelPath}" - WORKING_DIRECTORY "${CMAKE_BINARY_DIR}" VERBATIM) - list (APPEND ${_cmdsVar} COMMAND ${_prefixCmd}) set (${_cmdsVar} ${${_cmdsVar}} PARENT_SCOPE) endfunction() @@ -1740,6 +2174,10 @@ function (cotire_init_cotire_target_properties _target) if (NOT _isSet) set_property(TARGET ${_target} PROPERTY COTIRE_UNITY_SOURCE_POST_UNDEFS "") endif() + get_property(_isSet TARGET ${_target} PROPERTY COTIRE_UNITY_LINK_LIBRARIES_INIT SET) + if (NOT _isSet) + set_property(TARGET ${_target} PROPERTY COTIRE_UNITY_LINK_LIBRARIES_INIT "") + endif() get_property(_isSet TARGET ${_target} PROPERTY COTIRE_UNITY_SOURCE_MAXIMUM_NUMBER_OF_INCLUDES SET) if (NOT _isSet) if (COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES) @@ -1754,7 +2192,14 @@ function (cotire_make_target_message _target _languages _disableMsg _targetMsgVa get_target_property(_targetUsePCH ${_target} COTIRE_ENABLE_PRECOMPILED_HEADER) get_target_property(_targetAddSCU ${_target} COTIRE_ADD_UNITY_BUILD) string (REPLACE ";" " " _languagesStr "${_languages}") - string (REPLACE ";" ", " _excludedStr "${ARGN}") + math (EXPR _numberOfExcludedFiles "${ARGC} - 4") + if (_numberOfExcludedFiles EQUAL 0) + set (_excludedStr "") + elseif (COTIRE_VERBOSE OR _numberOfExcludedFiles LESS 4) + string (REPLACE ";" ", " _excludedStr "excluding ${ARGN}") + else() + set (_excludedStr "excluding ${_numberOfExcludedFiles} files") + endif() set (_targetMsg "") if (NOT _languages) set (_targetMsg "Target ${_target} cannot be cotired.") @@ -1767,8 +2212,8 @@ function (cotire_make_target_message _target _languages _disableMsg _targetMsgVa set (_targetMsg "${_targetMsg} ${_disableMsg}") endif() elseif (NOT _targetUsePCH) - if (_allExcludedSourceFiles) - set (_targetMsg "${_languagesStr} target ${_target} cotired excluding files ${_excludedStr} without precompiled header.") + if (_excludedStr) + set (_targetMsg "${_languagesStr} target ${_target} cotired without precompiled header ${_excludedStr}.") else() set (_targetMsg "${_languagesStr} target ${_target} cotired without precompiled header.") endif() @@ -1776,14 +2221,14 @@ function (cotire_make_target_message _target _languages _disableMsg _targetMsgVa set (_targetMsg "${_targetMsg} ${_disableMsg}") endif() elseif (NOT _targetAddSCU) - if (_allExcludedSourceFiles) - set (_targetMsg "${_languagesStr} target ${_target} cotired excluding files ${_excludedStr} without unity build.") + if (_excludedStr) + set (_targetMsg "${_languagesStr} target ${_target} cotired without unity build ${_excludedStr}.") else() set (_targetMsg "${_languagesStr} target ${_target} cotired without unity build.") endif() else() - if (_allExcludedSourceFiles) - set (_targetMsg "${_languagesStr} target ${_target} cotired excluding files ${_excludedStr}.") + if (_excludedStr) + set (_targetMsg "${_languagesStr} target ${_target} cotired ${_excludedStr}.") else() set (_targetMsg "${_languagesStr} target ${_target} cotired.") endif() @@ -1791,7 +2236,7 @@ function (cotire_make_target_message _target _languages _disableMsg _targetMsgVa set (${_targetMsgVar} "${_targetMsg}" PARENT_SCOPE) endfunction() -function (cotire_choose_target_languages _target _targetLanguagesVar) +function (cotire_choose_target_languages _targetSourceDir _target _targetLanguagesVar) set (_languages ${ARGN}) set (_allSourceFiles "") set (_allExcludedSourceFiles "") @@ -1806,12 +2251,12 @@ function (cotire_choose_target_languages _target _targetLanguagesVar) get_target_property(_prefixHeader ${_target} COTIRE_${_language}_PREFIX_HEADER) get_target_property(_unityBuildFile ${_target} COTIRE_${_language}_UNITY_SOURCE) if (_prefixHeader OR _unityBuildFile) - message (WARNING "Target ${_target} has already been cotired.") + message (STATUS "Target ${_target} has already been cotired.") set (${_targetLanguagesVar} "" PARENT_SCOPE) return() endif() - if (_targetUsePCH AND "${_language}" STREQUAL "C" OR "${_language}" STREQUAL "CXX") - cotire_check_precompiled_header_support("${_language}" "${_target}" _disableMsg) + if (_targetUsePCH AND "${_language}" MATCHES "^C|CXX$") + cotire_check_precompiled_header_support("${_language}" "${_targetSourceDir}" "${_target}" _disableMsg) if (_disableMsg) set (_targetUsePCH FALSE) endif() @@ -1881,46 +2326,82 @@ function (cotire_choose_target_languages _target _targetLanguagesVar) set (${_targetLanguagesVar} ${_targetLanguages} PARENT_SCOPE) endfunction() -function (cotire_process_target_language _language _configurations _target _wholeTargetVar _cmdsVar) +function (cotire_compute_unity_max_number_of_includes _target _maxIncludesVar) + set (_sourceFiles ${ARGN}) + get_target_property(_maxIncludes ${_target} COTIRE_UNITY_SOURCE_MAXIMUM_NUMBER_OF_INCLUDES) + if (_maxIncludes MATCHES "(-j|--parallel|--jobs) ?([0-9]*)") + set (_numberOfThreads "${CMAKE_MATCH_2}") + if (NOT _numberOfThreads) + # use all available cores + ProcessorCount(_numberOfThreads) + endif() + list (LENGTH _sourceFiles _numberOfSources) + math (EXPR _maxIncludes "(${_numberOfSources} + ${_numberOfThreads} - 1) / ${_numberOfThreads}") + # a unity source segment must not contain less than COTIRE_MINIMUM_NUMBER_OF_TARGET_SOURCES files + if (_maxIncludes LESS ${COTIRE_MINIMUM_NUMBER_OF_TARGET_SOURCES}) + set (_maxIncludes ${COTIRE_MINIMUM_NUMBER_OF_TARGET_SOURCES}) + endif() + elseif (NOT _maxIncludes MATCHES "[0-9]+") + set (_maxIncludes 0) + endif() + if (COTIRE_DEBUG) + message (STATUS "${_target} unity source max includes = ${_maxIncludes}") + endif() + set (${_maxIncludesVar} ${_maxIncludes} PARENT_SCOPE) +endfunction() + +function (cotire_process_target_language _language _configurations _targetSourceDir _targetBinaryDir _target _wholeTargetVar _cmdsVar) set (${_cmdsVar} "" PARENT_SCOPE) get_target_property(_targetSourceFiles ${_target} SOURCES) set (_sourceFiles "") set (_excludedSources "") set (_cotiredSources "") cotire_filter_language_source_files(${_language} _sourceFiles _excludedSources _cotiredSources ${_targetSourceFiles}) - if (NOT _sourceFiles) - return() - endif() - get_target_property(_maxIncludes ${_target} COTIRE_UNITY_SOURCE_MAXIMUM_NUMBER_OF_INCLUDES) - if (NOT _maxIncludes) - set (_maxIncludes 0) - endif() - cotire_make_untiy_source_file_paths(${_language} ${_target} ${_maxIncludes} _unityFiles ${_sourceFiles} ${_cotiredSources}) - if (NOT _unityFiles) + if (NOT _sourceFiles AND NOT _cotiredSources) return() endif() set (_wholeTarget ${${_wholeTargetVar}}) - cotire_generate_target_script( - ${_language} "${_configurations}" ${_target} _targetScript ${_sourceFiles}) set (_cmds "") + # check for user provided unity source file list + get_property(_unitySourceFiles TARGET ${_target} PROPERTY COTIRE_${_language}_UNITY_SOURCE_INIT) + if (NOT _unitySourceFiles) + set (_unitySourceFiles ${_sourceFiles} ${_cotiredSources}) + endif() + cotire_generate_target_script( + ${_language} "${_configurations}" "${_targetSourceDir}" "${_targetBinaryDir}" ${_target} _targetScript ${_unitySourceFiles}) + cotire_compute_unity_max_number_of_includes(${_target} _maxIncludes ${_unitySourceFiles}) + cotire_make_unity_source_file_paths(${_language} ${_target} ${_maxIncludes} _unityFiles ${_unitySourceFiles}) + if (NOT _unityFiles) + return() + endif() cotire_setup_unity_generation_commands( - ${_language} ${_target} "${_targetScript}" "${_unityFiles}" _cmds ${_sourceFiles} ${_cotiredSources}) + ${_language} "${_targetSourceDir}" ${_target} "${_targetScript}" "${_unityFiles}" _cmds ${_unitySourceFiles}) cotire_make_prefix_file_path(${_language} ${_target} _prefixFile) if (_prefixFile) - cotire_setup_prefix_generation_command( - ${_language} ${_target} "${_targetScript}" "${_prefixFile}" "${_unityFiles}" _cmds ${_sourceFiles} ${_cotiredSources}) + # check for user provided prefix header files + get_property(_prefixHeaderFiles TARGET ${_target} PROPERTY COTIRE_${_language}_PREFIX_HEADER_INIT) + if (_prefixHeaderFiles) + cotire_setup_combine_command(${_language} "${_targetSourceDir}" "${_targetScript}" "${_prefixFile}" _cmds ${_prefixHeaderFiles}) + else() + cotire_setup_multi_prefix_generation_command( + ${_language} ${_target} "${_targetSourceDir}" "${_targetScript}" "${_prefixFile}" "${_unityFiles}" _cmds ${_unitySourceFiles}) + endif() get_target_property(_targetUsePCH ${_target} COTIRE_ENABLE_PRECOMPILED_HEADER) if (_targetUsePCH) - cotire_make_pch_file_path(${_language} ${_target} _pchFile) + cotire_make_pch_file_path(${_language} "${_targetSourceDir}" ${_target} _pchFile) if (_pchFile) cotire_setup_pch_file_compilation( - ${_language} "${_targetScript}" "${_prefixFile}" "${_pchFile}" ${_sourceFiles}) + ${_language} ${_target} "${_targetSourceDir}" "${_targetScript}" "${_prefixFile}" "${_pchFile}" ${_sourceFiles}) if (_excludedSources) set (_wholeTarget FALSE) endif() - cotire_setup_prefix_file_inclusion( + cotire_setup_pch_file_inclusion( ${_language} ${_target} ${_wholeTarget} "${_prefixFile}" "${_pchFile}" ${_sourceFiles}) endif() + elseif (_prefixHeaderFiles) + # user provided prefix header must be included + cotire_setup_prefix_file_inclusion( + ${_language} ${_target} "${_prefixFile}" ${_sourceFiles}) endif() endif() # mark target as cotired for language @@ -1953,9 +2434,9 @@ function (cotire_setup_pch_target _languages _configurations _target) set (_dependsFiles "") foreach (_language ${_languages}) set (_props COTIRE_${_language}_PREFIX_HEADER COTIRE_${_language}_UNITY_SOURCE) - if (NOT MSVC) - # Visual Studio only creates precompiled header as a side effect - list(INSERT _props 0 COTIRE_${_language}_PRECOMPILED_HEADER) + if (NOT CMAKE_${_language}_COMPILER_ID MATCHES "MSVC|Intel") + # Visual Studio and Intel only create precompiled header as a side effect + list (INSERT _props 0 COTIRE_${_language}_PRECOMPILED_HEADER) endif() cotire_get_first_set_property_value(_dependsFile TARGET ${_target} ${_props}) if (_dependsFile) @@ -1968,23 +2449,21 @@ function (cotire_setup_pch_target _languages _configurations _target) cotire_init_target("${_pchTargetName}") cotire_add_to_pch_all_target(${_pchTargetName}) endif() + else() + # for other generators, we add the "clean all" target to clean up the precompiled header + cotire_setup_clean_all_target() endif() endfunction() -function (cotire_setup_unity_build_target _languages _configurations _target) - set (_unityTargetName "${_target}${COTIRE_UNITY_BUILD_TARGET_SUFFIX}") +function (cotire_setup_unity_build_target _languages _configurations _targetSourceDir _target) + get_target_property(_unityTargetName ${_target} COTIRE_UNITY_TARGET_NAME) + if (NOT _unityTargetName) + set (_unityTargetName "${_target}${COTIRE_UNITY_BUILD_TARGET_SUFFIX}") + endif() # determine unity target sub type get_target_property(_targetType ${_target} TYPE) if ("${_targetType}" STREQUAL "EXECUTABLE") - get_target_property(_isWin32 ${_target} WIN32_EXECUTABLE) - get_target_property(_isMacOSX_Bundle ${_target} MACOSX_BUNDLE) - if (_isWin32) - set (_unityTargetSubType WIN32) - elseif (_isMacOSX_Bundle) - set (_unityTargetSubType MACOSX_BUNDLE) - else() - set (_unityTargetSubType "") - endif() + set (_unityTargetSubType "") elseif (_targetType MATCHES "(STATIC|SHARED|MODULE|OBJECT)_LIBRARY") set (_unityTargetSubType "${CMAKE_MATCH_1}") else() @@ -1994,7 +2473,6 @@ function (cotire_setup_unity_build_target _languages _configurations _target) # determine unity target sources get_target_property(_targetSourceFiles ${_target} SOURCES) set (_unityTargetSources ${_targetSourceFiles}) - get_target_property(_targetUsePCH ${_target} COTIRE_ENABLE_PRECOMPILED_HEADER) foreach (_language ${_languages}) get_property(_unityFiles TARGET ${_target} PROPERTY COTIRE_${_language}_UNITY_SOURCE) if (_unityFiles) @@ -2006,22 +2484,24 @@ function (cotire_setup_unity_build_target _languages _configurations _target) if (_sourceFiles OR _cotiredSources) list (REMOVE_ITEM _unityTargetSources ${_sourceFiles} ${_cotiredSources}) endif() - # then add unity source file instead - list (APPEND _unityTargetSources ${_unityFiles}) - # make unity files use precompiled header if there are multiple unity files - list (LENGTH _unityFiles _numberOfUnityFiles) - if (_targetUsePCH AND _numberOfUnityFiles GREATER ${COTIRE_MINIMUM_NUMBER_OF_TARGET_SOURCES}) - get_property(_prefixFile TARGET ${_target} PROPERTY COTIRE_${_language}_PREFIX_HEADER) - get_property(_pchFile TARGET ${_target} PROPERTY COTIRE_${_language}_PRECOMPILED_HEADER) - if (_prefixFile AND _pchFile) - cotire_setup_pch_file_compilation( - ${_language} "" "${_prefixFile}" "${_pchFile}" ${_unityFiles}) - cotire_setup_prefix_file_inclusion( - ${_language} ${_target} FALSE "${_prefixFile}" "${_pchFile}" ${_unityFiles}) - # add the prefix header to unity target sources - list (APPEND _unityTargetSources "${_prefixFile}") + # if cotire is applied to a target which has not been added in the current source dir, + # non-existing files cannot be referenced from the unity build target (this is a CMake restriction) + if (NOT "${_targetSourceDir}" STREQUAL "${CMAKE_CURRENT_SOURCE_DIR}") + set (_nonExistingFiles "") + foreach (_file ${_unityTargetSources}) + if (NOT EXISTS "${_file}") + list (APPEND _nonExistingFiles "${_file}") + endif() + endforeach() + if (_nonExistingFiles) + if (COTIRE_VERBOSE) + message (STATUS "removing non-existing ${_nonExistingFiles} from ${_unityTargetName}") + endif() + list (REMOVE_ITEM _unityTargetSources ${_nonExistingFiles}) endif() endif() + # add unity source files instead + list (APPEND _unityTargetSources ${_unityFiles}) endif() endforeach() if (COTIRE_DEBUG) @@ -2043,13 +2523,13 @@ function (cotire_setup_unity_build_target _languages _configurations _target) if (IS_ABSOLUTE "${COTIRE_UNITY_OUTPUT_DIRECTORY}") set (_outputDir "${COTIRE_UNITY_OUTPUT_DIRECTORY}") else() - cotrie_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} ${_outputDirProperties}) - cotrie_resolve_config_properites("${_configurations}" _properties ${_outputDirProperties}) + cotire_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} ${_outputDirProperties}) + cotire_resolve_config_properites("${_configurations}" _properties ${_outputDirProperties}) foreach (_property ${_properties}) get_property(_outputDir TARGET ${_target} PROPERTY ${_property}) if (_outputDir) get_filename_component(_outputDir "${_outputDir}/${COTIRE_UNITY_OUTPUT_DIRECTORY}" ABSOLUTE) - set_property(TARGET ${_target} PROPERTY ${_property} "${_outputDir}") + set_property(TARGET ${_unityTargetName} PROPERTY ${_property} "${_outputDir}") set (_setDefaultOutputDir FALSE) endif() endforeach() @@ -2064,49 +2544,56 @@ function (cotire_setup_unity_build_target _languages _configurations _target) RUNTIME_OUTPUT_DIRECTORY "${_outputDir}") endif() else() - cotrie_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} ${_outputDirProperties}) + cotire_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} ${_outputDirProperties}) endif() # copy output name - cotrie_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} + cotire_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} ARCHIVE_OUTPUT_NAME ARCHIVE_OUTPUT_NAME_ LIBRARY_OUTPUT_NAME LIBRARY_OUTPUT_NAME_ OUTPUT_NAME OUTPUT_NAME_ RUNTIME_OUTPUT_NAME RUNTIME_OUTPUT_NAME_ PREFIX _POSTFIX SUFFIX) # copy compile stuff - cotrie_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} + cotire_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} COMPILE_DEFINITIONS COMPILE_DEFINITIONS_ - COMPILE_FLAGS Fortran_FORMAT + COMPILE_FLAGS COMPILE_OPTIONS + Fortran_FORMAT Fortran_MODULE_DIRECTORY INCLUDE_DIRECTORIES - INTERPROCEDURAL_OPTIMIZATION INTERPROCEDURAL_OPTIMIZATION_) + INTERPROCEDURAL_OPTIMIZATION INTERPROCEDURAL_OPTIMIZATION_ + POSITION_INDEPENDENT_CODE + C_VISIBILITY_PRESET CXX_VISIBILITY_PRESET VISIBILITY_INLINES_HIDDEN) + # copy interface stuff + cotire_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} + COMPATIBLE_INTERFACE_BOOL COMPATIBLE_INTERFACE_STRING + INTERFACE_COMPILE_DEFINITIONS INTERFACE_COMPILE_OPTIONS INTERFACE_INCLUDE_DIRECTORIES + INTERFACE_LINK_LIBRARIES INTERFACE_POSITION_INDEPENDENT_CODE INTERFACE_SYSTEM_INCLUDE_DIRECTORIES) # copy link stuff - cotrie_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} + cotire_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} BUILD_WITH_INSTALL_RPATH INSTALL_RPATH INSTALL_RPATH_USE_LINK_PATH SKIP_BUILD_RPATH - LINKER_LANGUAGE LINK_DEPENDS + LINKER_LANGUAGE LINK_DEPENDS LINK_DEPENDS_NO_SHARED LINK_FLAGS LINK_FLAGS_ LINK_INTERFACE_LIBRARIES LINK_INTERFACE_LIBRARIES_ LINK_INTERFACE_MULTIPLICITY LINK_INTERFACE_MULTIPLICITY_ LINK_SEARCH_START_STATIC LINK_SEARCH_END_STATIC STATIC_LIBRARY_FLAGS STATIC_LIBRARY_FLAGS_ - SOVERSION VERSION) + NO_SONAME SOVERSION VERSION) # copy Qt stuff - cotrie_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} + cotire_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} AUTOMOC AUTOMOC_MOC_OPTIONS) # copy cmake stuff - cotrie_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} + cotire_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} IMPLICIT_DEPENDS_INCLUDE_TRANSFORM RULE_LAUNCH_COMPILE RULE_LAUNCH_CUSTOM RULE_LAUNCH_LINK) - # copy platform stuff - if (APPLE) - cotrie_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} - BUNDLE BUNDLE_EXTENSION FRAMEWORK INSTALL_NAME_DIR MACOSX_BUNDLE_INFO_PLIST MACOSX_FRAMEWORK_INFO_PLIST - OSX_ARCHITECTURES OSX_ARCHITECTURES_ PRIVATE_HEADER PUBLIC_HEADER RESOURCE) - elseif (WIN32) - cotrie_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} - GNUtoMS - VS_DOTNET_REFERENCES VS_GLOBAL_KEYWORD VS_GLOBAL_PROJECT_TYPES VS_KEYWORD - VS_SCC_AUXPATH VS_SCC_LOCALPATH VS_SCC_PROJECTNAME VS_SCC_PROVIDER - VS_WINRT_EXTENSIONS VS_WINRT_REFERENCES) - endif() + # copy Apple platform specific stuff + cotire_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} + BUNDLE BUNDLE_EXTENSION FRAMEWORK INSTALL_NAME_DIR MACOSX_BUNDLE MACOSX_BUNDLE_INFO_PLIST MACOSX_FRAMEWORK_INFO_PLIST + MACOSX_RPATH OSX_ARCHITECTURES OSX_ARCHITECTURES_ PRIVATE_HEADER PUBLIC_HEADER RESOURCE) + # copy Windows platform specific stuff + cotire_copy_set_properites("${_configurations}" TARGET ${_target} ${_unityTargetName} + GNUtoMS + PDB_NAME PDB_NAME_ PDB_OUTPUT_DIRECTORY PDB_OUTPUT_DIRECTORY_ + VS_DOTNET_REFERENCES VS_GLOBAL_KEYWORD VS_GLOBAL_PROJECT_TYPES VS_GLOBAL_ROOTNAMESPACE VS_KEYWORD + VS_SCC_AUXPATH VS_SCC_LOCALPATH VS_SCC_PROJECTNAME VS_SCC_PROVIDER + VS_WINRT_EXTENSIONS VS_WINRT_REFERENCES WIN32_EXECUTABLE) # use output name from original target get_target_property(_targetOutputName ${_unityTargetName} OUTPUT_NAME) if (NOT _targetOutputName) @@ -2123,13 +2610,19 @@ function (cotire_setup_unity_build_target _languages _configurations _target) cotire_init_target(${_unityTargetName}) cotire_add_to_unity_all_target(${_unityTargetName}) set_property(TARGET ${_target} PROPERTY COTIRE_UNITY_TARGET_NAME "${_unityTargetName}") -endfunction() +endfunction(cotire_setup_unity_build_target) function (cotire_target _target) set(_options "") - set(_oneValueArgs "") + set(_oneValueArgs SOURCE_DIR BINARY_DIR) set(_multiValueArgs LANGUAGES CONFIGURATIONS) cmake_parse_arguments(_option "${_options}" "${_oneValueArgs}" "${_multiValueArgs}" ${ARGN}) + if (NOT _option_SOURCE_DIR) + set (_option_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}") + endif() + if (NOT _option_BINARY_DIR) + set (_option_BINARY_DIR "${CMAKE_CURRENT_BINARY_DIR}") + endif() if (NOT _option_LANGUAGES) get_property (_option_LANGUAGES GLOBAL PROPERTY ENABLED_LANGUAGES) endif() @@ -2145,9 +2638,17 @@ function (cotire_target _target) # trivial checks get_target_property(_imported ${_target} IMPORTED) if (_imported) - message (WARNING "Imported target ${_target} cannot be cotired") + message (WARNING "Imported target ${_target} cannot be cotired.") return() endif() + # resolve alias + get_target_property(_aliasName ${_target} ALIASED_TARGET) + if (_aliasName) + if (COTIRE_DEBUG) + message (STATUS "${_target} is an alias. Applying cotire to aliased target ${_aliasName} instead.") + endif() + set (_target ${_aliasName}) + endif() # check if target needs to be cotired for build type # when using configuration types, the test is performed at build time cotire_init_cotire_target_properties(${_target}) @@ -2165,7 +2666,7 @@ function (cotire_target _target) endif() endif() # choose languages that apply to the target - cotire_choose_target_languages("${_target}" _targetLanguages ${_option_LANGUAGES}) + cotire_choose_target_languages("${_option_SOURCE_DIR}" "${_target}" _targetLanguages ${_option_LANGUAGES}) if (NOT _targetLanguages) return() endif() @@ -2177,25 +2678,65 @@ function (cotire_target _target) endif() set (_cmds "") foreach (_language ${_targetLanguages}) - cotire_process_target_language("${_language}" "${_option_CONFIGURATIONS}" ${_target} _wholeTarget _cmd) + cotire_process_target_language("${_language}" "${_option_CONFIGURATIONS}" + "${_option_SOURCE_DIR}" "${_option_BINARY_DIR}" ${_target} _wholeTarget _cmd) if (_cmd) list (APPEND _cmds ${_cmd}) endif() endforeach() get_target_property(_targetAddSCU ${_target} COTIRE_ADD_UNITY_BUILD) if (_targetAddSCU) - cotire_setup_unity_build_target("${_targetLanguages}" "${_option_CONFIGURATIONS}" ${_target}) + cotire_setup_unity_build_target("${_targetLanguages}" "${_option_CONFIGURATIONS}" "${_option_SOURCE_DIR}" ${_target}) endif() get_target_property(_targetUsePCH ${_target} COTIRE_ENABLE_PRECOMPILED_HEADER) if (_targetUsePCH) - cotire_setup_target_pch_usage("${_targetLanguages}" ${_target} ${_wholeTarget} ${_cmds}) + cotire_setup_target_pch_usage("${_targetLanguages}" "${_option_SOURCE_DIR}" ${_target} ${_wholeTarget} ${_cmds}) cotire_setup_pch_target("${_targetLanguages}" "${_option_CONFIGURATIONS}" ${_target}) endif() get_target_property(_targetAddCleanTarget ${_target} COTIRE_ADD_CLEAN) if (_targetAddCleanTarget) cotire_setup_clean_target(${_target}) endif() -endfunction() +endfunction(cotire_target) + +function(cotire_target_link_libraries _target) + get_target_property(_unityTargetName ${_target} COTIRE_UNITY_TARGET_NAME) + if (TARGET "${_unityTargetName}") + get_target_property(_linkLibrariesStrategy ${_target} COTIRE_UNITY_LINK_LIBRARIES_INIT) + if (COTIRE_DEBUG) + message (STATUS "unity target ${_unityTargetName} link strategy: ${_linkLibrariesStrategy}") + endif() + if ("${_linkLibrariesStrategy}" MATCHES "^(COPY|COPY_UNITY)$") + if (CMAKE_VERSION VERSION_LESS "2.8.11") + message (WARNING "Unity target link strategy ${_linkLibrariesStrategy} requires CMake 2.8.11 or later. Defaulting to NONE for ${_target}.") + return() + endif() + get_target_property(_linkLibraries ${_target} LINK_LIBRARIES) + if (_linkLibraries) + if (COTIRE_DEBUG) + message (STATUS "target ${_target} link libraries: ${_linkLibraries}") + endif() + set (_unityTargetLibraries "") + foreach (_library ${_linkLibraries}) + if (TARGET "${_library}" AND "${_linkLibrariesStrategy}" MATCHES "COPY_UNITY") + get_target_property(_libraryUnityTargetName ${_library} COTIRE_UNITY_TARGET_NAME) + if (TARGET "${_libraryUnityTargetName}") + list (APPEND _unityTargetLibraries "${_libraryUnityTargetName}") + else() + list (APPEND _unityTargetLibraries "${_library}") + endif() + else() + list (APPEND _unityTargetLibraries "${_library}") + endif() + endforeach() + set_property(TARGET ${_unityTargetName} APPEND PROPERTY LINK_LIBRARIES ${_unityTargetLibraries}) + if (COTIRE_DEBUG) + message (STATUS "set unity target ${_unityTargetName} link libraries: ${_unityTargetLibraries}") + endif() + endif() + endif() + endif() +endfunction(cotire_target_link_libraries) function (cotire_cleanup _binaryDir _cotireIntermediateDirName _targetName) if (_targetName) @@ -2262,15 +2803,27 @@ endfunction() function (cotire) set(_options "") - set(_oneValueArgs "") + set(_oneValueArgs SOURCE_DIR BINARY_DIR) set(_multiValueArgs LANGUAGES CONFIGURATIONS) cmake_parse_arguments(_option "${_options}" "${_oneValueArgs}" "${_multiValueArgs}" ${ARGN}) set (_targets ${_option_UNPARSED_ARGUMENTS}) + if (NOT _option_SOURCE_DIR) + set (_option_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}") + endif() + if (NOT _option_BINARY_DIR) + set (_option_BINARY_DIR "${CMAKE_CURRENT_BINARY_DIR}") + endif() foreach (_target ${_targets}) if (TARGET ${_target}) - cotire_target(${_target} LANGUAGES ${_option_LANGUAGES} CONFIGURATIONS ${_option_CONFIGURATIONS}) + cotire_target(${_target} LANGUAGES ${_option_LANGUAGES} CONFIGURATIONS ${_option_CONFIGURATIONS} + SOURCE_DIR "${_option_SOURCE_DIR}" BINARY_DIR "${_option_BINARY_DIR}") else() - message (WARNING "${_target} is not a target") + message (WARNING "${_target} is not a target.") + endif() + endforeach() + foreach (_target ${_targets}) + if (TARGET ${_target}) + cotire_target_link_libraries(${_target}) endif() endforeach() endfunction() @@ -2289,15 +2842,16 @@ if (CMAKE_SCRIPT_MODE_FILE) endif() endforeach() - if (COTIRE_DEBUG) - message (STATUS "${COTIRE_ARGV0} ${COTIRE_ARGV1} ${COTIRE_ARGV2} ${COTIRE_ARGV3} ${COTIRE_ARGV4} ${COTIRE_ARGV5}") - endif() - # include target script if available if ("${COTIRE_ARGV2}" MATCHES "\\.cmake$") + # the included target scripts sets up additional variables relating to the target (e.g., COTIRE_TARGET_SOURCES) include("${COTIRE_ARGV2}") endif() + if (COTIRE_DEBUG) + message (STATUS "${COTIRE_ARGV0} ${COTIRE_ARGV1} ${COTIRE_ARGV2} ${COTIRE_ARGV3} ${COTIRE_ARGV4} ${COTIRE_ARGV5}") + endif() + if (WIN32) # for MSVC, compiler IDs may not always be set correctly if (MSVC) @@ -2336,7 +2890,7 @@ if (CMAKE_SCRIPT_MODE_FILE) cotire_generate_unity_source( "${COTIRE_ARGV3}" ${_sources} LANGUAGE "${COTIRE_TARGET_LANGUAGE}" - DEPENDS "${COTIRE_ARGV0}" "${COTIRE_ARGV2}" ${COTIRE_TARGET_UNITY_DEPENDS} + DEPENDS "${COTIRE_ARGV0}" "${COTIRE_ARGV2}" SOURCES_COMPILE_DEFINITIONS ${_sourcesDefinitions} PRE_UNDEFS ${_targetPreUndefs} POST_UNDEFS ${_targetPostUndefs} @@ -2389,13 +2943,22 @@ if (CMAKE_SCRIPT_MODE_FILE) elseif ("${COTIRE_ARGV1}" STREQUAL "combine") + if (COTIRE_TARGET_LANGUAGE) + set (_startIndex 3) + else() + set (_startIndex 2) + endif() set (_files "") - foreach (_index RANGE 2 ${COTIRE_ARGC}) + foreach (_index RANGE ${_startIndex} ${COTIRE_ARGC}) if (COTIRE_ARGV${_index}) list (APPEND _files "${COTIRE_ARGV${_index}}") endif() endforeach() - cotire_generate_unity_source(${_files}) + if (COTIRE_TARGET_LANGUAGE) + cotire_generate_unity_source(${_files} LANGUAGE "${COTIRE_TARGET_LANGUAGE}") + else() + cotire_generate_unity_source(${_files}) + endif() elseif ("${COTIRE_ARGV1}" STREQUAL "cleanup") @@ -2437,10 +3000,23 @@ else() set (COTIRE_ADDITIONAL_PREFIX_HEADER_IGNORE_PATH "" CACHE STRING "Ignore headers from these directories when generating the prefix header.") + set (COTIRE_UNITY_SOURCE_EXCLUDE_EXTENSIONS "m;mm" CACHE STRING + "Ignore sources with the listed file extensions from the generated unity source.") + set (COTIRE_MINIMUM_NUMBER_OF_TARGET_SOURCES "3" CACHE STRING "Minimum number of sources in target required to enable use of precompiled header.") - set (COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES "" CACHE STRING + if (NOT DEFINED COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES_INIT) + if (DEFINED COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES) + set (COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES_INIT ${COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES}) + elseif ("${CMAKE_GENERATOR}" MATCHES "JOM|Ninja|Visual Studio") + # enable parallelization for generators that run multiple jobs by default + set (COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES_INIT "-j") + else() + set (COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES_INIT "0") + endif() + endif() + set (COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES "${COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES_INIT}" CACHE STRING "Maximum number of source files to include in a single unity source file.") if (NOT COTIRE_PREFIX_HEADER_FILENAME_SUFFIX) @@ -2495,7 +3071,7 @@ else() define_property( CACHED_VARIABLE PROPERTY "COTIRE_ADDITIONAL_PREFIX_HEADER_IGNORE_EXTENSIONS" - BRIEF_DOCS "Ignore includes with the listed file extensions from the prefix header when generating the prefix header." + BRIEF_DOCS "Ignore includes with the listed file extensions from the generated prefix header." FULL_DOCS "The variable can be set to a semicolon separated list of file extensions." "If a header file extension matches one in the list, it will be excluded from the generated prefix header." @@ -2503,6 +3079,16 @@ else() "If not defined, defaults to inc;inl;ipp." ) + define_property( + CACHED_VARIABLE PROPERTY "COTIRE_UNITY_SOURCE_EXCLUDE_EXTENSIONS" + BRIEF_DOCS "Exclude sources with the listed file extensions from the generated unity source." + FULL_DOCS + "The variable can be set to a semicolon separated list of file extensions." + "If a source file extension matches one in the list, it will be excluded from the generated unity source file." + "Source files with an extension in CMAKE__IGNORE_EXTENSIONS are always excluded." + "If not defined, defaults to m;mm." + ) + define_property( CACHED_VARIABLE PROPERTY "COTIRE_MINIMUM_NUMBER_OF_TARGET_SOURCES" BRIEF_DOCS "Minimum number of sources in target required to enable use of precompiled header." @@ -2516,11 +3102,13 @@ else() CACHED_VARIABLE PROPERTY "COTIRE_MAXIMUM_NUMBER_OF_UNITY_INCLUDES" BRIEF_DOCS "Maximum number of source files to include in a single unity source file." FULL_DOCS - "This may be set to an integer > 0." + "This may be set to an integer >= 0." + "If 0, cotire will only create a single unity source file." "If a target contains more than that number of source files, cotire will create multiple unity source files for it." - "If not set, cotire will only create a single unity source file." - "Is use to initialize the target property COTIRE_UNITY_SOURCE_MAXIMUM_NUMBER_OF_INCLUDES." - "Defaults to empty." + "Can be set to \"-j\" to optimize the count of unity source files for the number of available processor cores." + "Can be set to \"-j jobs\" to optimize the number of unity source files for the given number of simultaneous jobs." + "Is used to initialize the target property COTIRE_UNITY_SOURCE_MAXIMUM_NUMBER_OF_INCLUDES." + "Defaults to \"-j\" for the generators Visual Studio, JOM or Ninja. Defaults to 0 otherwise." ) # define cotire directory properties @@ -2581,6 +3169,13 @@ else() "See target property COTIRE_UNITY_SOURCE_MAXIMUM_NUMBER_OF_INCLUDES." ) + define_property( + DIRECTORY PROPERTY "COTIRE_UNITY_LINK_LIBRARIES_INIT" + BRIEF_DOCS "Define strategy for setting up the unity target's link libraries." + FULL_DOCS + "See target property COTIRE_UNITY_LINK_LIBRARIES_INIT." + ) + # define cotire target properties define_property( @@ -2670,6 +3265,37 @@ else() "Defaults to empty." ) + define_property( + TARGET PROPERTY "COTIRE__UNITY_SOURCE_INIT" + BRIEF_DOCS "User provided unity source file to be used instead of the automatically generated one." + FULL_DOCS + "If set, cotire will only add the given file(s) to the generated unity source file." + "If not set, cotire will add all the target source files to the generated unity source file." + "The property can be set to a user provided unity source file." + "Defaults to empty." + ) + + define_property( + TARGET PROPERTY "COTIRE__PREFIX_HEADER_INIT" + BRIEF_DOCS "User provided prefix header file to be used instead of the automatically generated one." + FULL_DOCS + "If set, cotire will add the given header file(s) to the generated prefix header file." + "If not set, cotire will generate a prefix header by tracking the header files included by the unity source file." + "The property can be set to a user provided prefix header file (e.g., stdafx.h)." + "Defaults to empty." + ) + + define_property( + TARGET PROPERTY "COTIRE_UNITY_LINK_LIBRARIES_INIT" INHERITED + BRIEF_DOCS "Define strategy for setting up unity target's link libraries." + FULL_DOCS + "If this property is empty, the generated unity target's link libraries have to be set up manually." + "If this property is set to COPY, the unity target's link libraries will be copied from this target." + "If this property is set to COPY_UNITY, the unity target's link libraries will be copied from this target with considering existing unity targets." + "Inherited from directory." + "Defaults to empty." + ) + define_property( TARGET PROPERTY "COTIRE__UNITY_SOURCE" BRIEF_DOCS "Read-only property. The generated unity source file(s)." @@ -2696,9 +3322,11 @@ else() define_property( TARGET PROPERTY "COTIRE_UNITY_TARGET_NAME" - BRIEF_DOCS "Read-only property. The name of the generated unity build target corresponding to this target." + BRIEF_DOCS "The name of the generated unity build target corresponding to this target." FULL_DOCS - "cotire sets this property to the name the generated unity build target for this target." + "This property can be set to the desired name of the unity target that will be created by cotire." + "If not set, the unity target name will be set to this target's name with the suffix _unity appended." + "After this target has been processed by cotire, the property is set to the actual name of the generated unity target." "Defaults to empty string." ) @@ -2759,4 +3387,6 @@ else() "Defaults to empty string." ) + message (STATUS "cotire ${COTIRE_CMAKE_MODULE_VERSION} loaded.") + endif() diff --git a/include/BinaryImage.h b/include/BinaryImage.h index 4ecd86f..06dd6eb 100644 --- a/include/BinaryImage.h +++ b/include/BinaryImage.h @@ -1,5 +1,6 @@ #pragma once #include +#include struct PROG /* Loaded program image parameters */ { int16_t initCS; @@ -8,15 +9,17 @@ struct PROG /* Loaded program image parameters */ uint16_t initSP; bool fCOM; /* Flag set if COM program (else EXE)*/ int cReloc; /* No. of relocation table entries */ - uint32_t * relocTable; /* Ptr. to relocation table */ + std::vector relocTable; /* Ptr. to relocation table */ uint8_t * map; /* Memory bitmap ptr */ int cProcs; /* Number of procedures so far */ int offMain; /* The offset of the main() proc */ uint16_t segMain; /* The segment of the main() proc */ bool bSigs; /* True if signatures loaded */ int cbImage; /* Length of image in bytes */ - const uint8_t *image() const {return Imagez;} uint8_t * Imagez; /* Allocated by loader to hold entire program image */ int addressingMode; +public: + const uint8_t *image() const {return Imagez;} + void displayLoadInfo(); }; diff --git a/include/CallGraph.h b/include/CallGraph.h new file mode 100644 index 0000000..114d92d --- /dev/null +++ b/include/CallGraph.h @@ -0,0 +1,19 @@ +#pragma once +#include "Procedure.h" +/* CALL GRAPH NODE */ +struct CALL_GRAPH +{ + ilFunction proc; /* Pointer to procedure in pProcList */ + std::vector outEdges; /* array of out edges */ +public: + void write(); + CALL_GRAPH() + { + } +public: + void writeNodeCallGraph(int indIdx); + bool insertCallGraph(ilFunction caller, ilFunction callee); + bool insertCallGraph(Function *caller, ilFunction callee); + void insertArc(ilFunction newProc); +}; +//extern CALL_GRAPH * callGraph; /* Pointer to the head of the call graph */ diff --git a/include/DccFrontend.h b/include/DccFrontend.h new file mode 100644 index 0000000..39d6c84 --- /dev/null +++ b/include/DccFrontend.h @@ -0,0 +1,17 @@ +#pragma once +#include +class Project; +class DccFrontend : public QObject +{ + Q_OBJECT + void LoadImage(); + void parse(Project &proj); + std::string m_fname; +public: + explicit DccFrontend(QObject *parent = 0); + bool FrontEnd(); /* frontend.c */ + +signals: + +public slots: +}; diff --git a/include/dcc.h b/include/dcc.h index 20a7474..3fc0f25 100644 --- a/include/dcc.h +++ b/include/dcc.h @@ -9,6 +9,7 @@ #include #include #include +#include #include "Enums.h" #include "types.h" @@ -26,7 +27,7 @@ extern bundle cCode; /* Output C procedure's declaration and code */ /**** Global variables ****/ -extern std::string asm1_name, asm2_name; /* Assembler output filenames */ +extern QString asm1_name, asm2_name; /* Assembler output filenames */ typedef struct { /* Command line option flags */ unsigned verbose : 1; @@ -37,7 +38,7 @@ typedef struct { /* Command line option flags */ unsigned Stats : 1; unsigned Interact : 1; /* Interactive mode */ unsigned Calls : 1; /* Follow register indirect calls */ - std::string filename; /* The input filename */ + QString filename; /* The input filename */ } OPTION; extern OPTION option; /* Command line options */ @@ -71,22 +72,11 @@ extern STATS stats; /* Icode statistics */ /**** Global function prototypes ****/ -class DccFrontend -{ - void LoadImage(Project &proj); - void parse(Project &proj); - std::string m_fname; -public: - DccFrontend(const std::string &fname) : m_fname(fname) - { - } - bool FrontEnd(); /* frontend.c */ -}; void udm(void); /* udm.c */ void freeCFG(BB * cfg); /* graph.c */ BB * newBB(BB *, int, int, uint8_t, int, Function *); /* graph.c */ -void BackEnd(const std::string &filename, CALL_GRAPH *); /* backend.c */ +void BackEnd(CALL_GRAPH *); /* backend.c */ extern char *cChar(uint8_t c); /* backend.c */ eErrorId scan(uint32_t ip, ICODE &p); /* scanner.c */ void parse (CALL_GRAPH * *); /* parser.c */ diff --git a/include/dcc_interface.h b/include/dcc_interface.h new file mode 100644 index 0000000..12488e1 --- /dev/null +++ b/include/dcc_interface.h @@ -0,0 +1,25 @@ +#pragma once +#include "Procedure.h" + +#include +#include +#include + +class IXmlTarget; + +struct IDcc { + static IDcc *get(); + virtual void BaseInit()=0; + virtual void Init(QObject *tgt)=0; + virtual lFunction::iterator GetFirstFuncHandle()=0; + virtual lFunction::iterator GetCurFuncHandle()=0; + virtual void analysis_Once()=0; + virtual void load(QString name)=0; // load and preprocess -> find entry point + virtual void prtout_asm(IXmlTarget *,int level=0)=0; + virtual void prtout_cpp(IXmlTarget *,int level=0)=0; + virtual size_t getFuncCount()=0; + virtual const lFunction &validFunctions() const =0; + virtual void SetCurFunc_by_Name(QString )=0; + virtual QDir installDir()=0; + virtual QDir dataDir(QString kind)=0; +}; diff --git a/include/project.h b/include/project.h index 32380d6..61b8296 100644 --- a/include/project.h +++ b/include/project.h @@ -8,22 +8,25 @@ #include #include #include +#include #include "symtab.h" #include "BinaryImage.h" #include "Procedure.h" +class QString; class SourceMachine; struct CALL_GRAPH; class IProject { virtual PROG *binary()=0; - virtual const std::string & project_name() const =0; - virtual const std::string & binary_path() const =0; + virtual const QString & project_name() const =0; + virtual const QString & binary_path() const =0; }; class Project : public IProject { static Project *s_instance; - std::string m_fname; - std::string m_project_name; + QString m_fname; + QString m_project_name; + QString m_output_path; public: typedef llvm::iplist FunctionListType; @@ -41,9 +44,12 @@ typedef FunctionListType lFunction; Project(); // default constructor, public: - void create(const std::string & a); - const std::string &project_name() const {return m_project_name;} - const std::string &binary_path() const {return m_fname;} + void create(const QString &a); + bool load(); + const QString &output_path() const {return m_output_path;} + const QString &project_name() const {return m_project_name;} + const QString &binary_path() const {return m_fname;} + QString output_name(const char *ext); ilFunction funcIter(Function *to_find); ilFunction findByEntry(uint32_t entry); ilFunction createFunction(FunctionType *f,const std::string &name); @@ -60,6 +66,7 @@ public: PROG * binary() {return &prog;} SourceMachine *machine(); + const FunctionListType &functions() const { return pProcList; } protected: void initialize(); void writeGlobSymTable(); diff --git a/prototypes/dcclibs.dat b/prototypes/dcclibs.dat new file mode 100644 index 0000000..485c9b0 Binary files /dev/null and b/prototypes/dcclibs.dat differ diff --git a/sigs/dccb2s.sig b/sigs/dccb2s.sig new file mode 100644 index 0000000..b2f49a6 Binary files /dev/null and b/sigs/dccb2s.sig differ diff --git a/src/BasicBlock.cpp b/src/BasicBlock.cpp index 10f182f..f2f4cea 100644 --- a/src/BasicBlock.cpp +++ b/src/BasicBlock.cpp @@ -28,11 +28,11 @@ BB *BB::Create(const rCODE &r,eBBKind _nodeType, Function *parent) pnewBB->loopHead = pnewBB->caseHead = pnewBB->caseTail = pnewBB->latchNode= pnewBB->loopFollow = NO_NODE; pnewBB->instructions = r; - int addr = pnewBB->begin()->loc_ip; /* Mark the basic block to which the icodes belong to, but only for * real code basic blocks (ie. not interval bbs) */ if(parent) { + int addr = pnewBB->begin()->loc_ip; //setInBB should automatically handle if our range is empty parent->Icode.SetInBB(pnewBB->instructions, pnewBB); @@ -40,10 +40,10 @@ BB *BB::Create(const rCODE &r,eBBKind _nodeType, Function *parent) parent->m_ip_to_bb[addr] = pnewBB; parent->m_actual_cfg.push_back(pnewBB); pnewBB->Parent = parent; - } if ( r.begin() != parent->Icode.end() ) /* Only for code BB's */ stats.numBBbef++; + } return pnewBB; } @@ -90,7 +90,7 @@ void BB::displayDfs() dfsFirstNum, dfsLastNum, immedDom == MAX ? -1 : immedDom); printf("loopType = %s, loopHead = %d, latchNode = %d, follow = %d\n", - s_loopType[loopType], + s_loopType[(int)loopType], loopHead == MAX ? -1 : loopHead, latchNode == MAX ? -1 : latchNode, loopFollow == MAX ? -1 : loopFollow); @@ -136,12 +136,14 @@ void BB::displayDfs() */ ICODE* BB::writeLoopHeader(int &indLevel, Function* pProc, int *numLoc, BB *&latch, bool &repCond) { + if(loopType == eNodeHeaderType::NO_TYPE) + return nullptr; latch = pProc->m_dfsLast[this->latchNode]; std::ostringstream ostr; ICODE* picode; switch (loopType) { - case WHILE_TYPE: + case eNodeHeaderType::WHILE_TYPE: picode = &this->back(); /* Check for error in while condition */ @@ -169,15 +171,16 @@ ICODE* BB::writeLoopHeader(int &indLevel, Function* pProc, int *numLoc, BB *&lat picode->invalidate(); break; - case REPEAT_TYPE: + case eNodeHeaderType::REPEAT_TYPE: ostr << "\n"<back(); picode->invalidate(); break; - case ENDLESS_TYPE: + case eNodeHeaderType::ENDLESS_TYPE: ostr << "\n"<back(); + break; } cCode.appendCode(ostr.str()); stats.numHLIcode += 1; @@ -209,10 +212,7 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode, /* Check for start of loop */ repCond = false; latch = nullptr; - if (loopType) - { picode=writeLoopHeader(indLevel, pProc, numLoc, latch, repCond); - } /* Write the code for this basic block */ if (repCond == false) @@ -227,12 +227,12 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode, return; /* Check type of loop/node and process code */ - if ( loopType ) /* there is a loop */ + if ( loopType!=eNodeHeaderType::NO_TYPE ) /* there is a loop */ { assert(latch); if (this != latch) /* loop is over several bbs */ { - if (loopType == WHILE_TYPE) + if (loopType == eNodeHeaderType::WHILE_TYPE) { succ = edges[THEN].BBptr; if (succ->dfsLastNum == loopFollow) @@ -248,7 +248,7 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode, /* Loop epilogue: generate the loop trailer */ indLevel--; - if (loopType == WHILE_TYPE) + if (loopType == eNodeHeaderType::WHILE_TYPE) { std::ostringstream ostr; /* Check if there is need to repeat other statements involved @@ -260,9 +260,9 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode, ostr <hl()->opcode != HLI_JCOND) diff --git a/src/DccFrontend.cpp b/src/DccFrontend.cpp new file mode 100644 index 0000000..eb478e4 --- /dev/null +++ b/src/DccFrontend.cpp @@ -0,0 +1,410 @@ +#include +#include +#include +#include "dcc.h" +#include "DccFrontend.h" +#include "project.h" +#include "disassem.h" +#include "CallGraph.h" + + +class Loader +{ + bool loadIntoProject(IProject *); +}; + +struct PSP { /* PSP structure */ + uint16_t int20h; /* interrupt 20h */ + uint16_t eof; /* segment, end of allocation block */ + uint8_t res1; /* reserved */ + uint8_t dosDisp[5]; /* far call to DOS function dispatcher */ + uint8_t int22h[4]; /* vector for terminate routine */ + uint8_t int23h[4]; /* vector for ctrl+break routine */ + uint8_t int24h[4]; /* vector for error routine */ + uint8_t res2[22]; /* reserved */ + uint16_t segEnv; /* segment address of environment block */ + uint8_t res3[34]; /* reserved */ + uint8_t int21h[6]; /* opcode for int21h and far return */ + uint8_t res4[6]; /* reserved */ + uint8_t fcb1[16]; /* default file control block 1 */ + uint8_t fcb2[16]; /* default file control block 2 */ + uint8_t res5[4]; /* reserved */ + uint8_t cmdTail[0x80]; /* command tail and disk transfer area */ +}; + +static struct MZHeader { /* EXE file header */ + uint8_t sigLo; /* .EXE signature: 0x4D 0x5A */ + uint8_t sigHi; + uint16_t lastPageSize; /* Size of the last page */ + uint16_t numPages; /* Number of pages in the file */ + uint16_t numReloc; /* Number of relocation items */ + uint16_t numParaHeader; /* # of paragraphs in the header */ + uint16_t minAlloc; /* Minimum number of paragraphs */ + uint16_t maxAlloc; /* Maximum number of paragraphs */ + uint16_t initSS; /* Segment displacement of stack */ + uint16_t initSP; /* Contents of SP at entry */ + uint16_t checkSum; /* Complemented checksum */ + uint16_t initIP; /* Contents of IP at entry */ + uint16_t initCS; /* Segment displacement of code */ + uint16_t relocTabOffset; /* Relocation table offset */ + uint16_t overlayNum; /* Overlay number */ +} header; + +#define EXE_RELOCATION 0x10 /* EXE images rellocated to above PSP */ + +//static void LoadImage(char *filename); +static void displayMemMap(void); +/**************************************************************************** +* displayLoadInfo - Displays low level loader type info. +***************************************************************************/ +void PROG::displayLoadInfo(void) +{ + int i; + + printf("File type is %s\n", (fCOM)?"COM":"EXE"); + if (! fCOM) { + printf("Signature = %02X%02X\n", header.sigLo, header.sigHi); + printf("File size %% 512 = %04X\n", LH(&header.lastPageSize)); + printf("File size / 512 = %04X pages\n", LH(&header.numPages)); + printf("# relocation items = %04X\n", LH(&header.numReloc)); + printf("Offset to load image = %04X paras\n", LH(&header.numParaHeader)); + printf("Minimum allocation = %04X paras\n", LH(&header.minAlloc)); + printf("Maximum allocation = %04X paras\n", LH(&header.maxAlloc)); + } + printf("Load image size = %04" PRIiPTR "\n", cbImage - sizeof(PSP)); + printf("Initial SS:SP = %04X:%04X\n", initSS, initSP); + printf("Initial CS:IP = %04X:%04X\n", initCS, initIP); + + if (option.VeryVerbose && cReloc) + { + printf("\nRelocation Table\n"); + for (i = 0; i < cReloc; i++) + { + printf("%06X -> [%04X]\n", relocTable[i],LH(image() + relocTable[i])); + } + } + printf("\n"); +} + +/***************************************************************************** +* fill - Fills line for displayMemMap() +****************************************************************************/ +static void fill(int ip, char *bf) +{ + PROG &prog(Project::get()->prog); + static uint8_t type[4] = {'.', 'd', 'c', 'x'}; + uint8_t i; + + for (i = 0; i < 16; i++, ip++) + { + *bf++ = ' '; + *bf++ = (ip < prog.cbImage)? type[(prog.map[ip >> 2] >> ((ip & 3) * 2)) & 3]: ' '; + } + *bf = '\0'; +} + + +/***************************************************************************** +* displayMemMap - Displays the memory bitmap +****************************************************************************/ +static void displayMemMap(void) +{ + PROG &prog(Project::get()->prog); + + char c, b1[33], b2[33], b3[33]; + uint8_t i; + int ip = 0; + + printf("\nMemory Map\n"); + while (ip < prog.cbImage) + { + fill(ip, b1); + printf("%06X %s\n", ip, b1); + ip += 16; + for (i = 3, c = b1[1]; i < 32 && c == b1[i]; i += 2) + ; /* Check if all same */ + if (i > 32) + { + fill(ip, b2); /* Skip until next two are not same */ + fill(ip+16, b3); + if (! (strcmp(b1, b2) || strcmp(b1, b3))) + { + printf(" :\n"); + do + { + ip += 16; + fill(ip+16, b1); + } while (! strcmp(b1, b2)); + } + } + } + printf("\n"); +} +DccFrontend::DccFrontend(QObject *parent) : + QObject(parent) +{ +} + +/***************************************************************************** +* FrontEnd - invokes the loader, parser, disassembler (if asm1), icode +* rewritter, and displays any useful information. +****************************************************************************/ +bool DccFrontend::FrontEnd () +{ + + /* Do depth first flow analysis building call graph and procedure list, + * and attaching the I-code to each procedure */ + parse (*Project::get()); + + if (option.asm1) + { + std::cout << "dcc: writing assembler file "<pProcList) + { + f.markImpure(); + if (option.asm1) + { + ds.disassem(&f); + } + } + if (option.Interact) + { + interactDis(&Project::get()->pProcList.front(), 0); /* Interactive disassembler */ + } + + /* Converts jump target addresses to icode offsets */ + for(Function &f : Project::get()->pProcList) + { + f.bindIcodeOff(); + } + /* Print memory bitmap */ + if (option.Map) + displayMemMap(); + return(true); // we no longer own proj ! +} +struct DosLoader { +protected: + void prepareImage(PROG &prog,size_t sz,QFile &fp) { + /* Allocate a block of memory for the program. */ + prog.cbImage = sz + sizeof(PSP); + prog.Imagez = new uint8_t [prog.cbImage]; + prog.Imagez[0] = 0xCD; /* Fill in PSP int 20h location */ + prog.Imagez[1] = 0x20; /* for termination checking */ + /* Read in the image past where a PSP would go */ + if (sz != fp.read((char *)prog.Imagez + sizeof(PSP),sz)) + fatalError(CANNOT_READ, fp.fileName().toLocal8Bit().data()); + } +}; +struct ComLoader : public DosLoader { + bool canLoad(QFile &fp) { + fp.seek(0); + char sig[2]; + if(2==fp.read(sig,2)) { + return not (sig[0] == 0x4D && sig[1] == 0x5A); + } + return false; + } + bool load(PROG &prog,QFile &fp) { + /* COM file + * In this case the load module size is just the file length + */ + auto cb = fp.size(); + + /* COM programs start off with an ORG 100H (to leave room for a PSP) + * This is also the implied start address so if we load the image + * at offset 100H addresses should all line up properly again. + */ + prog.initCS = 0; + prog.initIP = 0x100; + prog.initSS = 0; + prog.initSP = 0xFFFE; + prog.cReloc = 0; + + prepareImage(prog,cb,fp); + + + /* Set up memory map */ + cb = (prog.cbImage + 3) / 4; + prog.map = (uint8_t *)malloc(cb); + memset(prog.map, BM_UNKNOWN, (size_t)cb); + return true; + } +}; +struct ExeLoader : public DosLoader { + bool canLoad(QFile &fp) { + if(fp.size()> 8); + } + return true; + } +}; +/***************************************************************************** +* LoadImage +****************************************************************************/ +bool Project::load() +{ + // addTask(loaderSelection,PreCond(BinaryImage)) + // addTask(applyLoader,PreCond(Loader)) + const char *fname = binary_path().toLocal8Bit().data(); + QFile finfo(binary_path()); + /* Open the input file */ + if(!finfo.open(QFile::ReadOnly)) { + fatalError(CANNOT_OPEN, fname); + } + /* Read in first 2 bytes to check EXE signature */ + if (finfo.size()<=2) + { + fatalError(CANNOT_READ, fname); + } + ComLoader com_loader; + ExeLoader exe_loader; + if(exe_loader.canLoad(finfo)) { + prog.fCOM = false; + return exe_loader.load(prog,finfo); + } + if(com_loader.canLoad(finfo)) { + prog.fCOM = true; + return com_loader.load(prog,finfo); + } + return false; +} +uint32_t SynthLab; +/* Parses the program, builds the call graph, and returns the list of + * procedures found */ +void DccFrontend::parse(Project &proj) +{ + PROG &prog(proj.prog); + STATE state; + + /* Set initial state */ + state.setState(rES, 0); /* PSP segment */ + state.setState(rDS, 0); + state.setState(rCS, prog.initCS); + state.setState(rSS, prog.initSS); + state.setState(rSP, prog.initSP); + state.IP = ((uint32_t)prog.initCS << 4) + prog.initIP; + SynthLab = SYNTHESIZED_MIN; + + /* Check for special settings of initial state, based on idioms of the + startup code */ + state.checkStartup(); + Function *start_proc; + /* Make a struct for the initial procedure */ + if (prog.offMain != -1) + { + start_proc = proj.createFunction(0,"main"); + start_proc->retVal.loc = REG_FRAME; + start_proc->retVal.type = TYPE_WORD_SIGN; + start_proc->retVal.id.regi = rAX; + /* We know where main() is. Start the flow of control from there */ + start_proc->procEntry = prog.offMain; + /* In medium and large models, the segment of main may (will?) not be + the same as the initial CS segment (of the startup code) */ + state.setState(rCS, prog.segMain); + state.IP = prog.offMain; + } + else + { + start_proc = proj.createFunction(0,"start"); + /* Create initial procedure at program start address */ + start_proc->procEntry = (uint32_t)state.IP; + } + + /* The state info is for the first procedure */ + start_proc->state = state; + + /* Set up call graph initial node */ + proj.callGraph = new CALL_GRAPH; + proj.callGraph->proc = start_proc; + + /* This proc needs to be called to set things up for LibCheck(), which + checks a proc to see if it is a know C (etc) library */ + SetupLibCheck(); + //BUG: proj and g_proj are 'live' at this point ! + + /* Recursively build entire procedure list */ + start_proc->FollowCtrl(proj.callGraph, &state); + + /* This proc needs to be called to clean things up from SetupLibCheck() */ + CleanupLibCheck(); +} diff --git a/src/backend.cpp b/src/backend.cpp index 874cb03..7f62b94 100644 --- a/src/backend.cpp +++ b/src/backend.cpp @@ -4,6 +4,8 @@ * Purpose: Back-end module. Generates C code for each procedure. * (C) Cristina Cifuentes ****************************************************************************/ +#include +#include #include #include #include @@ -167,13 +169,13 @@ void Project::writeGlobSymTable() /* Writes the header information and global variables to the output C file * fp. */ -static void writeHeader (std::ostream &_ios, const char *fileName) +static void writeHeader (std::ostream &_ios, const std::string &fileName) { PROG &prog(Project::get()->prog); /* Write header information */ cCode.init(); cCode.appendDecl( "/*\n"); - cCode.appendDecl( " * Input file\t: %s\n", fileName); + cCode.appendDecl( " * Input file\t: %s\n", fileName.c_str()); cCode.appendDecl( " * File type\t: %s\n", (prog.fCOM)?"COM":"EXE"); cCode.appendDecl( " */\n\n#include \"dcc.h\"\n\n"); @@ -341,22 +343,21 @@ static void backBackEnd (CALL_GRAPH * pcallGraph, std::ostream &_ios) /* Invokes the necessary routines to produce code one procedure at a time. */ -void BackEnd (const std::string &fileName, CALL_GRAPH * pcallGraph) +void BackEnd(CALL_GRAPH * pcallGraph) { std::ofstream fs; /* Output C file */ /* Get output file name */ - std::string outNam(fileName); - outNam = outNam.substr(0,outNam.rfind("."))+".b"; /* b for beta */ + QString outNam(Project::get()->output_name("b")); /* b for beta */ /* Open output file */ - fs.open(outNam); + fs.open(outNam.toStdString()); if(!fs.is_open()) - fatalError (CANNOT_OPEN, outNam.c_str()); - printf ("dcc: Writing C beta file %s\n", outNam.c_str()); + fatalError (CANNOT_OPEN, outNam.toStdString().c_str()); + std::cout<<"dcc: Writing C beta file "< -#include -#ifdef __BORLAND__ -#include -#else -#include -#endif -#include #include "dcc.h" #include "project.h" #include "perfhlib.h" +#include "dcc_interface.h" + +#include +#include +#include +#include +#include #define NIL -1 /* Used like NULL, but 0 is valid */ @@ -300,10 +299,11 @@ void SetupLibCheck(void) PROG &prog(Project::get()->prog); uint16_t w, len; int i; - - if ((g_file = fopen(sSigName, "rb")) == nullptr) + IDcc *dcc = IDcc::get(); + QString fpath = dcc->dataDir("sigs").absoluteFilePath(sSigName); + if ((g_file = fopen(qPrintable(fpath), "rb")) == nullptr) { - printf("Warning: cannot open signature file %s\n", sSigName); + printf("Warning: cannot open signature file %s\n", qPrintable(fpath)); return; } @@ -638,7 +638,6 @@ void STATE::checkStartup() char chModel = 'x'; char chVendor = 'x'; char chVersion = 'x'; - char *pPath; char temp[4]; startOff = ((uint32_t)prog.initCS << 4) + prog.initIP; @@ -829,21 +828,6 @@ void STATE::checkStartup() gotVendor: - /* Use the DCC environment variable to set where the .sig files will - be found. Otherwise, assume current directory */ - pPath = getenv("DCC"); - if (pPath) - { - strcpy(sSigName, pPath); /* Use path given */ - if (sSigName[strlen(sSigName)-1] != '/') - { - strcat(sSigName, "/"); /* Append a slash if necessary */ - } - } - else - { - strcpy(sSigName, "./"); /* Current directory */ - } strcat(sSigName, "dcc"); temp[1] = '\0'; temp[0] = chVendor; @@ -866,45 +850,30 @@ gotVendor: */ void readProtoFile(void) { + IDcc *dcc = IDcc::get(); + QString szProFName = dcc->dataDir("prototypes").absoluteFilePath(DCCLIBS); /* Full name of dclibs.lst */ + FILE *fProto; char *pPath; /* Point to the environment string */ - char szProFName[81]; /* Full name of dclibs.lst */ int i; - /* Use the DCC environment variable to set where the dcclibs.lst file will - be found. Otherwise, assume current directory */ - pPath = getenv("DCC"); - if (pPath) + if ((fProto = fopen(qPrintable(szProFName), "rb")) == nullptr) { - strcpy(szProFName, pPath); /* Use path given */ - if (szProFName[strlen(szProFName)-1] != '/') - { - strcat(szProFName, "/"); /* Append a slash if necessary */ - } - } - else - { - strcpy(szProFName, "./"); /* Current directory */ - } - strcat(szProFName, DCCLIBS); - - if ((fProto = fopen(szProFName, "rb")) == nullptr) - { - printf("Warning: cannot open library prototype data file %s\n", szProFName); + printf("Warning: cannot open library prototype data file %s\n", qPrintable(szProFName)); return; } grab(4, fProto); if (strncmp(buf, "dccp", 4) != 0) { - printf("%s is not a dcc prototype file\n", szProFName); + printf("%s is not a dcc prototype file\n", qPrintable(szProFName)); exit(1); } grab(2, fProto); if (strncmp(buf, "FN", 2) != 0) { - printf("FN (Function Name) subsection expected in %s\n", szProFName); + printf("FN (Function Name) subsection expected in %s\n", qPrintable(szProFName)); exit(2); } @@ -931,7 +900,7 @@ void readProtoFile(void) grab(2, fProto); if (strncmp(buf, "PM", 2) != 0) { - printf("PM (Parameter) subsection expected in %s\n", szProFName); + printf("PM (Parameter) subsection expected in %s\n", qPrintable(szProFName)); exit(2); } diff --git a/src/control.cpp b/src/control.cpp index 7c2c62b..fc30051 100644 --- a/src/control.cpp +++ b/src/control.cpp @@ -168,7 +168,7 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int (inList (loopNodes, head->edges[THEN].BBptr->dfsLastNum) && inList (loopNodes, head->edges[ELSE].BBptr->dfsLastNum))) { - head->loopType = REPEAT_TYPE; + head->loopType = eNodeHeaderType::REPEAT_TYPE; if (latchNode->edges[0].BBptr == head) head->loopFollow = latchNode->edges[ELSE].BBptr->dfsLastNum; else @@ -177,7 +177,7 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int } else { - head->loopType = WHILE_TYPE; + head->loopType = eNodeHeaderType::WHILE_TYPE; if (inList (loopNodes, head->edges[THEN].BBptr->dfsLastNum)) head->loopFollow = head->edges[ELSE].BBptr->dfsLastNum; else @@ -186,7 +186,7 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int } else /* head = anything besides 2-way, latch = 2-way */ { - head->loopType = REPEAT_TYPE; + head->loopType = eNodeHeaderType::REPEAT_TYPE; if (latchNode->edges[THEN].BBptr == head) head->loopFollow = latchNode->edges[ELSE].BBptr->dfsLastNum; else @@ -196,12 +196,12 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int else /* latch = 1-way */ if (latchNode->nodeType == LOOP_NODE) { - head->loopType = REPEAT_TYPE; + head->loopType = eNodeHeaderType::REPEAT_TYPE; head->loopFollow = latchNode->edges[0].BBptr->dfsLastNum; } else if (intNodeType == TWO_BRANCH) { - head->loopType = WHILE_TYPE; + head->loopType = eNodeHeaderType::WHILE_TYPE; pbb = latchNode; thenDfs = head->edges[THEN].BBptr->dfsLastNum; elseDfs = head->edges[ELSE].BBptr->dfsLastNum; @@ -222,7 +222,7 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int * loop, so it is safer to consider it an endless loop */ if (pbb->dfsLastNum <= head->dfsLastNum) { - head->loopType = ENDLESS_TYPE; + head->loopType = eNodeHeaderType::ENDLESS_TYPE; findEndlessFollow (pProc, loopNodes, head); break; } @@ -234,7 +234,7 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int } else { - head->loopType = ENDLESS_TYPE; + head->loopType = eNodeHeaderType::ENDLESS_TYPE; findEndlessFollow (pProc, loopNodes, head); } diff --git a/src/dataflow.cpp b/src/dataflow.cpp index 75c1fb9..269d3c3 100644 --- a/src/dataflow.cpp +++ b/src/dataflow.cpp @@ -143,7 +143,6 @@ void Function::elimCondCodes () //auto reversed_instructions = pBB->range() | reversed; for (useAt = pBB->rbegin(); useAt != pBB->rend(); useAt++) { - ICODE &useIcode(*useAt); llIcode useAtOp = llIcode(useAt->ll()->getOpcode()); use = useAt->ll()->flagDU.u; if ((useAt->type != LOW_LEVEL) || ( ! useAt->valid() ) || ( 0 == use )) @@ -159,7 +158,6 @@ void Function::elimCondCodes () continue; notSup = false; LLOperand *dest_ll = defIcode.ll()->get(DST); - LLOperand *src_ll = defIcode.ll()->get(SRC); if ((useAtOp >= iJB) && (useAtOp <= iJNS)) { iICODE befDefAt = (++riICODE(defAt)).base(); diff --git a/src/dcc.cpp b/src/dcc.cpp index d1e0654..7acdefd 100644 --- a/src/dcc.cpp +++ b/src/dcc.cpp @@ -4,26 +4,10 @@ * (C) Cristina Cifuentes ****************************************************************************/ +#include +#include #include #include -#include -#include "dcc.h" -#include "project.h" - -#include "CallGraph.h" -/* Global variables - extern to other modules */ -extern std::string asm1_name, asm2_name; /* Assembler output filenames */ -extern SYMTAB symtab; /* Global symbol table */ -extern STATS stats; /* cfg statistics */ -//PROG prog; /* programs fields */ -extern OPTION option; /* Command line options */ -//Function * pProcList; /* List of procedures, topologically sort */ -//Function * pLastProc; /* Pointer to last node in procedure list */ -//FunctionListType pProcList; -//CALL_GRAPH *callGraph; /* Call graph of the program */ - -static char *initargs(int argc, char *argv[]); -static void displayTotalStats(void); #include #include #include @@ -39,11 +23,24 @@ static void displayTotalStats(void); #include #include #include +#include + +#include "dcc.h" +#include "project.h" +#include "CallGraph.h" +#include "DccFrontend.h" + +/* Global variables - extern to other modules */ +extern QString asm1_name, asm2_name; /* Assembler output filenames */ +extern SYMTAB symtab; /* Global symbol table */ +extern STATS stats; /* cfg statistics */ +extern OPTION option; /* Command line options */ + +static char *initargs(int argc, char *argv[]); +static void displayTotalStats(void); /**************************************************************************** * main ***************************************************************************/ -#include -#include using namespace llvm; bool TVisitor(raw_ostream &OS, RecordKeeper &Records) { @@ -161,9 +158,9 @@ void setupOptions(QCoreApplication &app) { option.Stats = parser.isSet(boolOpts[4]); option.Interact = false; option.Calls = parser.isSet(boolOpts[2]); - option.filename = args.first().toStdString(); + option.filename = args.first(); if(parser.isSet(targetFileOption)) - asm1_name = asm2_name = parser.value(targetFileOption).toStdString(); + asm1_name = asm2_name = parser.value(targetFileOption); else if(option.asm1 || option.asm2) { asm1_name = option.filename+".a1"; asm2_name = option.filename+".a2"; @@ -181,7 +178,14 @@ int main(int argc, char **argv) * building the call graph and attaching appropriate bits of code for * each procedure. */ - DccFrontend fe(option.filename); + Project::get()->create(option.filename); + + DccFrontend fe(&app); + if(!Project::get()->load()) { + return -1; + } + if (option.verbose) + Project::get()->prog.displayLoadInfo(); if(false==fe.FrontEnd ()) return -1; if(option.asm1) @@ -198,7 +202,7 @@ int main(int argc, char **argv) * analysis, data flow etc. and outputs it to output file ready for * re-compilation. */ - BackEnd(!asm1_name.empty() ? asm1_name:option.filename, Project::get()->callGraph); + BackEnd(Project::get()->callGraph); Project::get()->callGraph->write(); diff --git a/src/dcc_interface.cpp b/src/dcc_interface.cpp new file mode 100644 index 0000000..7a050a2 --- /dev/null +++ b/src/dcc_interface.cpp @@ -0,0 +1,61 @@ +#include "dcc_interface.h" +#include "dcc.h" +#include "project.h" +struct DccImpl : public IDcc{ + + + // IDcc interface +public: + void BaseInit() + { + } + void Init(QObject *tgt) + { + } + ilFunction GetFirstFuncHandle() + { + } + ilFunction GetCurFuncHandle() + { + } + void analysis_Once() + { + } + void load(QString name) + { + option.filename = name; + Project::get()->create(name); + } + void prtout_asm(IXmlTarget *, int level) + { + } + void prtout_cpp(IXmlTarget *, int level) + { + } + size_t getFuncCount() + { + } + const lFunction &validFunctions() const + { + return Project::get()->functions(); + } + void SetCurFunc_by_Name(QString) + { + } + QDir installDir() { + return QDir("."); + } + QDir dataDir(QString kind) { // return directory containing decompilation helper data -> signatures/includes/etc. + QDir res(installDir()); + res.cd(kind); + return res; + } +}; + +IDcc* IDcc::get() { + static IDcc *v=0; + if(!v) + v = new DccImpl; + + return v; +} diff --git a/src/disassem.cpp b/src/disassem.cpp index 6ea0656..2788227 100644 --- a/src/disassem.cpp +++ b/src/disassem.cpp @@ -150,10 +150,10 @@ void Disassembler::disassem(Function * ppProc) if (pass != 3) { auto p = (pass == 1)? asm1_name: asm2_name; - m_fp.open(p,ios_base::app); + m_fp.open(p.toStdString(),ios_base::app); if (!m_fp.is_open()) { - fatalError(CANNOT_OPEN, p.c_str()); + fatalError(CANNOT_OPEN, p.toStdString().c_str()); } } /* Create temporary code array */ diff --git a/src/idioms.cpp b/src/idioms.cpp index e0e1f8a..90c3b56 100644 --- a/src/idioms.cpp +++ b/src/idioms.cpp @@ -3,7 +3,12 @@ * (C) Cristina Cifuentes ****************************************************************************/ +#include +#if( (LLVM_VERSION_MAJOR==3 ) && (LLVM_VERSION_MINOR>3) ) +#include +#else #include +#endif #include #include #include diff --git a/src/idioms/mov_idioms.cpp b/src/idioms/mov_idioms.cpp index c932a18..bda01b6 100644 --- a/src/idioms/mov_idioms.cpp +++ b/src/idioms/mov_idioms.cpp @@ -27,16 +27,16 @@ bool Idiom14::match(iICODE pIcode) return false; m_icodes[0]=pIcode++; m_icodes[1]=pIcode++; - LLInst * matched [] = {m_icodes[0]->ll(),m_icodes[1]->ll()}; + LLInst * matched [] {m_icodes[0]->ll(),m_icodes[1]->ll()}; /* Check for regL */ - m_regL = m_icodes[0]->ll()->m_dst.regi; - if (not m_icodes[0]->ll()->testFlags(I) && ((m_regL == rAX) || (m_regL ==rBX))) + m_regL = matched[0]->m_dst.regi; + if (not matched[0]->testFlags(I) && ((m_regL == rAX) || (m_regL ==rBX))) { /* Check for XOR regH, regH */ - if (m_icodes[1]->ll()->match(iXOR) && not m_icodes[1]->ll()->testFlags(I)) + if (matched[1]->match(iXOR) && not matched[1]->testFlags(I)) { - m_regH = m_icodes[1]->ll()->m_dst.regi; - if (m_regH == m_icodes[1]->ll()->src().getReg2()) + m_regH = matched[1]->m_dst.regi; + if (m_regH == matched[1]->src().getReg2()) { if ((m_regL == rAX) && (m_regH == rDX)) return true; @@ -49,14 +49,11 @@ bool Idiom14::match(iICODE pIcode) } int Idiom14::action() { - int idx; - AstIdent *lhs; - Expr *rhs; - idx = m_func->localId.newLongReg (TYPE_LONG_SIGN, LONGID_TYPE(m_regH,m_regL), m_icodes[0]); - lhs = AstIdent::LongIdx (idx); + int idx = m_func->localId.newLongReg (TYPE_LONG_SIGN, LONGID_TYPE(m_regH,m_regL), m_icodes[0]); + AstIdent *lhs = AstIdent::LongIdx (idx); m_icodes[0]->setRegDU( m_regH, eDEF); - rhs = AstIdent::id (*m_icodes[0]->ll(), SRC, m_func, m_icodes[0], *m_icodes[0], NONE); + Expr *rhs = AstIdent::id (*m_icodes[0]->ll(), SRC, m_func, m_icodes[0], *m_icodes[0], NONE); m_icodes[0]->setAsgn(lhs, rhs); m_icodes[1]->invalidate(); return 2; diff --git a/src/parser.cpp b/src/parser.cpp index 9dfaccf..ab2c909 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -20,70 +20,8 @@ static void setBits(int16_t type, uint32_t start, uint32_t len); static void process_MOV(LLInst &ll, STATE * pstate); static SYM * lookupAddr (LLOperand *pm, STATE * pstate, int size, uint16_t duFlag); void interactDis(Function * initProc, int ic); -static uint32_t SynthLab; +extern uint32_t SynthLab; -/* Parses the program, builds the call graph, and returns the list of - * procedures found */ -void DccFrontend::parse(Project &proj) -{ - PROG &prog(proj.prog); - STATE state; - - /* Set initial state */ - state.setState(rES, 0); /* PSP segment */ - state.setState(rDS, 0); - state.setState(rCS, prog.initCS); - state.setState(rSS, prog.initSS); - state.setState(rSP, prog.initSP); - state.IP = ((uint32_t)prog.initCS << 4) + prog.initIP; - SynthLab = SYNTHESIZED_MIN; - - // default-construct a Function object ! - /*auto func = */; - - /* Check for special settings of initial state, based on idioms of the - startup code */ - state.checkStartup(); - Function *start_proc; - /* Make a struct for the initial procedure */ - if (prog.offMain != -1) - { - start_proc = proj.createFunction(0,"main"); - start_proc->retVal.loc = REG_FRAME; - start_proc->retVal.type = TYPE_WORD_SIGN; - start_proc->retVal.id.regi = rAX; - /* We know where main() is. Start the flow of control from there */ - start_proc->procEntry = prog.offMain; - /* In medium and large models, the segment of main may (will?) not be - the same as the initial CS segment (of the startup code) */ - state.setState(rCS, prog.segMain); - state.IP = prog.offMain; - } - else - { - start_proc = proj.createFunction(0,"start"); - /* Create initial procedure at program start address */ - start_proc->procEntry = (uint32_t)state.IP; - } - - /* The state info is for the first procedure */ - start_proc->state = state; - - /* Set up call graph initial node */ - proj.callGraph = new CALL_GRAPH; - proj.callGraph->proc = start_proc; - - /* This proc needs to be called to set things up for LibCheck(), which - checks a proc to see if it is a know C (etc) library */ - SetupLibCheck(); - //BUG: proj and g_proj are 'live' at this point ! - - /* Recursively build entire procedure list */ - start_proc->FollowCtrl(proj.callGraph, &state); - - /* This proc needs to be called to clean things up from SetupLibCheck() */ - CleanupLibCheck(); -} /* Returns the size of the string pointed by sym and delimited by delim. * Size includes delimiter. */ diff --git a/src/project.cpp b/src/project.cpp index 23d298e..0cb0ff8 100644 --- a/src/project.cpp +++ b/src/project.cpp @@ -1,3 +1,5 @@ +#include +#include #include #include "dcc.h" #include "CallGraph.h" @@ -5,7 +7,7 @@ #include "Procedure.h" using namespace std; //Project g_proj; -string asm1_name, asm2_name; /* Assembler output filenames */ +QString asm1_name, asm2_name; /* Assembler output filenames */ SYMTAB symtab; /* Global symbol table */ STATS stats; /* cfg statistics */ //PROG prog; /* programs fields */ @@ -20,19 +22,26 @@ void Project::initialize() delete callGraph; callGraph = nullptr; } -void Project::create(const string &a) +void Project::create(const QString &a) { + initialize(); m_fname=a; - string::size_type ext_loc=a.find_last_of('.'); - string::size_type slash_loc=a.find_last_of('/',ext_loc); - if(slash_loc==string::npos) + auto ext_loc=a.lastIndexOf('.'); + auto slash_loc=a.lastIndexOf('/',ext_loc); + if(slash_loc==-1) slash_loc=0; else slash_loc++; - if(ext_loc!=string::npos) - m_project_name = a.substr(slash_loc,(ext_loc-slash_loc)); + if(ext_loc!=-1) { + m_project_name = a.mid(slash_loc,ext_loc-slash_loc); + } else - m_project_name = a.substr(slash_loc); + m_project_name = a.mid(slash_loc); + m_output_path = a.left(slash_loc); +} + +QString Project::output_name(const char *ext) { + return m_output_path+QDir::separator()+m_project_name+"."+ext; } bool Project::valid(ilFunction iter) {