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Replaced memory tags #defines with eAreaType enum

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Added replaceExpr, which replaces expression, and deletes the old one.
Moved subReg* family to Machine_X86, also moved there a few float op
decoding parts.
A few more usages of cCode global replaced with ostreams
Refactored compoundCond().
This commit is contained in:
Artur K 2012-03-13 22:10:07 +01:00
parent c2e5ac2694
commit a740690e04
24 changed files with 525 additions and 504 deletions
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2
include/BasicBlock.h
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@ -105,7 +105,7 @@ static BB * Create(int start, int ip, uint8_t nodeType, int numOutEdges, Functio
/// ///
const Function *getParent() const { return Parent; } const Function *getParent() const { return Parent; }
Function *getParent() { return Parent; } Function *getParent() { return Parent; }
void writeBB(int lev, Function *pProc, int *numLoc); void writeBB(std::ostream &ostr, int lev, Function *pProc, int *numLoc);
BB *rmJMP(int marker, BB *pBB); BB *rmJMP(int marker, BB *pBB);
void genDU1(); void genDU1();
private: private:

9
include/Procedure.h
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@ -151,7 +151,14 @@ public:
void controlFlowAnalysis(); void controlFlowAnalysis();
void newRegArg(iICODE picode, iICODE ticode); void newRegArg(iICODE picode, iICODE ticode);
void writeProcComments(std::ostream &ostr); void writeProcComments(std::ostream &ostr);
protected: bool Case_X_and_Y(BB* pbb, BB* thenBB, BB* elseBB);
bool Case_X_or_Y(BB* pbb, BB* thenBB, BB* elseBB);
bool Case_notX_or_Y(BB* pbb, BB* thenBB, BB* elseBB);
bool Case_notX_and_Y(BB* pbb, BB* thenBB, BB* elseBB);
void replaceInEdge(BB* where, BB* which, BB* with);
protected:
bool removeInEdge_Flag_and_ProcessLatch(BB *pbb, BB *a, BB *b);
// TODO: replace those with friend visitor ? // TODO: replace those with friend visitor ?
void propLongReg(int loc_ident_idx, const ID &pLocId); void propLongReg(int loc_ident_idx, const ID &pLocId);
void propLongStk(int i, const ID &pLocId); void propLongStk(int i, const ID &pLocId);

25
include/ast.h
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@ -44,29 +44,29 @@ protected:
} boolExpr; } boolExpr;
public: public:
condNodeType type; /* Conditional Expression Node Type */ condNodeType m_type; /* Conditional Expression Node Type */
union _exprNode { /* Different cond expr nodes */ union _exprNode { /* Different cond expr nodes */
COND_EXPR *unaryExp; /* for NEGATION,ADDRESSOF,DEREFERENCE*/ COND_EXPR *unaryExp; /* for NEGATION,ADDRESSOF,DEREFERENCE*/
IDENTTYPE ident; /* for IDENTIFIER */ IDENTTYPE ident; /* for IDENTIFIER */
} expr; } expr;
COND_EXPR *lhs() COND_EXPR *lhs()
{ {
assert(type==BOOLEAN_OP); assert(m_type==BOOLEAN_OP);
return boolExpr.lhs; return boolExpr.lhs;
} }
const COND_EXPR *lhs() const const COND_EXPR *lhs() const
{ {
assert(type==BOOLEAN_OP); assert(m_type==BOOLEAN_OP);
return boolExpr.lhs; return boolExpr.lhs;
} }
COND_EXPR *rhs() COND_EXPR *rhs()
{ {
assert(type==BOOLEAN_OP); assert(m_type==BOOLEAN_OP);
return boolExpr.rhs; return boolExpr.rhs;
} }
const COND_EXPR *rhs() const const COND_EXPR *rhs() const
{ {
assert(type==BOOLEAN_OP); assert(m_type==BOOLEAN_OP);
return boolExpr.rhs; return boolExpr.rhs;
} }
condOp op() const { return boolExpr.op;} condOp op() const { return boolExpr.op;}
@ -92,11 +92,11 @@ public:
void changeBoolOp(condOp newOp); void changeBoolOp(condOp newOp);
COND_EXPR(const COND_EXPR &other) COND_EXPR(const COND_EXPR &other)
{ {
type=other.type; m_type=other.m_type;
expr=other.expr; expr=other.expr;
boolExpr=other.boolExpr; boolExpr=other.boolExpr;
} }
COND_EXPR(condNodeType t=UNKNOWN_OP) : type(t) COND_EXPR(condNodeType t=UNKNOWN_OP) : m_type(t)
{ {
memset(&expr,0,sizeof(_exprNode)); memset(&expr,0,sizeof(_exprNode));
memset(&boolExpr,0,sizeof(boolExpr)); memset(&boolExpr,0,sizeof(boolExpr));
@ -108,6 +108,7 @@ public:
virtual bool xClear(iICODE f, iICODE t, iICODE lastBBinst, Function *pproc); virtual bool xClear(iICODE f, iICODE t, iICODE lastBBinst, Function *pproc);
virtual COND_EXPR *insertSubTreeReg(COND_EXPR *_expr, eReg regi, LOCAL_ID *locsym); virtual COND_EXPR *insertSubTreeReg(COND_EXPR *_expr, eReg regi, LOCAL_ID *locsym);
virtual COND_EXPR *insertSubTreeLongReg(COND_EXPR *_expr, int longIdx); virtual COND_EXPR *insertSubTreeLongReg(COND_EXPR *_expr, int longIdx);
virtual hlType expType(Function *pproc) const;
}; };
struct BinaryOperator : public COND_EXPR struct BinaryOperator : public COND_EXPR
{ {
@ -129,22 +130,22 @@ struct BinaryOperator : public COND_EXPR
COND_EXPR *lhs() COND_EXPR *lhs()
{ {
assert(type==BOOLEAN_OP); assert(m_type==BOOLEAN_OP);
return m_lhs; return m_lhs;
} }
const COND_EXPR *lhs() const const COND_EXPR *lhs() const
{ {
assert(type==BOOLEAN_OP); assert(m_type==BOOLEAN_OP);
return m_lhs; return m_lhs;
} }
COND_EXPR *rhs() COND_EXPR *rhs()
{ {
assert(type==BOOLEAN_OP); assert(m_type==BOOLEAN_OP);
return m_rhs; return m_rhs;
} }
const COND_EXPR *rhs() const const COND_EXPR *rhs() const
{ {
assert(type==BOOLEAN_OP); assert(m_type==BOOLEAN_OP);
return m_rhs; return m_rhs;
} }
condOp op() const { return m_op;} condOp op() const { return m_op;}
@ -161,7 +162,7 @@ struct UnaryOperator : public COND_EXPR
static UnaryOperator *Create(condNodeType t, COND_EXPR *sub_expr) static UnaryOperator *Create(condNodeType t, COND_EXPR *sub_expr)
{ {
UnaryOperator *newExp = new UnaryOperator(); UnaryOperator *newExp = new UnaryOperator();
newExp->type=t; newExp->m_type=t;
newExp->unaryExp = sub_expr; newExp->unaryExp = sub_expr;
return (newExp); return (newExp);
} }

18
include/bundle.h
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@ -8,14 +8,26 @@
#include <stdio.h> #include <stdio.h>
#include <vector> #include <vector>
#include <string> #include <string>
typedef std::vector<std::string> strTable; struct strTable : std::vector<std::string>
{
/* Returns the next available index into the table */
size_t nextIdx() {return size();}
public:
void addLabelBundle(int idx, int label);
};
struct bundle struct bundle
{ {
public: public:
void appendCode(const char *format, ...); void appendCode(const char *format, ...);
void appendCode(const std::string &s);
void appendDecl(const char *format, ...); void appendDecl(const char *format, ...);
void appendDecl(const std::string &); void appendDecl(const std::string &);
void init()
{
decl.clear();
code.clear();
}
strTable decl; /* Declarations */ strTable decl; /* Declarations */
strTable code; /* C code */ strTable code; /* C code */
}; };
@ -23,9 +35,7 @@ public:
#define lineSize 360 /* 3 lines in the mean time */ #define lineSize 360 /* 3 lines in the mean time */
void newBundle (bundle *procCode); //void newBundle (bundle *procCode);
int nextBundleIdx (strTable *strTab);
void addLabelBundle (strTable &strTab, int idx, int label);
void writeBundle (std::ostream &ios, bundle procCode); void writeBundle (std::ostream &ios, bundle procCode);
void freeBundle (bundle *procCode); void freeBundle (bundle *procCode);

21
include/dcc.h
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@ -39,8 +39,8 @@ public:
}; };
//#define NUM_PROCS_DELTA 5 /* delta # procs a proc invokes */ //#define NUM_PROCS_DELTA 5 /* delta # procs a proc invokes */
//extern std::list<Function> pProcList; //extern std::list<Function> pProcList;
extern FunctionListType pProcList; //extern FunctionListType pProcList;
extern CALL_GRAPH * callGraph; /* Pointer to the head of the call graph */ //extern CALL_GRAPH * callGraph; /* Pointer to the head of the call graph */
extern bundle cCode; /* Output C procedure's declaration and code */ extern bundle cCode; /* Output C procedure's declaration and code */
/**** Global variables ****/ /**** Global variables ****/
@ -89,10 +89,13 @@ extern std::bitset<32> maskDuReg[30]; /* masks off du bits for regs */
/* Registers used by icode instructions */ /* Registers used by icode instructions */
/* Memory map states */ /* Memory map states */
#define BM_UNKNOWN 0 /* Unscanned memory */ enum eAreaType
#define BM_DATA 1 /* Data */ {
#define BM_CODE 2 /* Code */ BM_UNKNOWN = 0, /* Unscanned memory */
#define BM_IMPURE 3 /* Used as Data and Code*/ BM_DATA = 1, /* Data */
BM_CODE = 2, /* Code */
BM_IMPURE = 3 /* Used as Data and Code*/
};
/* Intermediate instructions statistics */ /* Intermediate instructions statistics */
struct STATS struct STATS
@ -142,14 +145,12 @@ bool LibCheck(Function &p); /* chklib.c */
/* Exported functions from procs.c */ /* Exported functions from procs.c */
boolT insertCallGraph (CALL_GRAPH *, ilFunction, ilFunction); boolT insertCallGraph (CALL_GRAPH *, ilFunction, ilFunction);
void allocStkArgs (ICODE *, int);
void placeStkArg (ICODE *, COND_EXPR *, int);
void adjustActArgType (COND_EXPR *, hlType, Function *); void adjustActArgType (COND_EXPR *, hlType, Function *);
/* Exported functions from ast.c */ /* Exported functions from ast.c */
std::string walkCondExpr (const COND_EXPR *exp, Function * pProc, int *); std::string walkCondExpr (const COND_EXPR *exp, Function * pProc, int *);
int hlTypeSize (const COND_EXPR *, Function *); int hlTypeSize (const COND_EXPR *, Function *);
hlType expType (const COND_EXPR *, Function *); //hlType expType (const COND_EXPR *, Function *);
/* Exported functions from hlicode.c */ /* Exported functions from hlicode.c */
@ -164,6 +165,4 @@ boolT checkLongRegEq (LONGID_TYPE, iICODE, int, Function *, Assignment &asgn, iI
eReg otherLongRegi(eReg, int, LOCAL_ID *); eReg otherLongRegi(eReg, int, LOCAL_ID *);
extern eReg subRegH(eReg reg); //TODO: move these into machine_x86
extern eReg subRegL(eReg reg);
extern const char *indentStr(int level); extern const char *indentStr(int level);

6
include/icode.h
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@ -120,6 +120,12 @@ public:
assert(e); assert(e);
exp.v=e; exp.v=e;
} }
void replaceExpr(COND_EXPR *e)
{
assert(e);
delete exp.v;
exp.v=e;
}
COND_EXPR * expr() { return exp.v;} COND_EXPR * expr() { return exp.v;}
const COND_EXPR * const expr() const { return exp.v;} const COND_EXPR * const expr() const { return exp.v;}
void set(hlIcode i,COND_EXPR *e) void set(hlIcode i,COND_EXPR *e)

4
include/machine_x86.h
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@ -49,6 +49,7 @@ public:
Machine_X86(); Machine_X86();
static const std::string &regName(eReg r); static const std::string &regName(eReg r);
static const std::string &opcodeName(unsigned r); static const std::string &opcodeName(unsigned r);
static const std::string &floatOpName(unsigned r);
static bool physicalReg(eReg r); static bool physicalReg(eReg r);
/* Writes the registers that are set in the bitvector */ /* Writes the registers that are set in the bitvector */
//TODO: move this into Machine_X86 ? //TODO: move this into Machine_X86 ?
@ -61,6 +62,9 @@ public:
ostr << regName(eReg(j)); ostr << regName(eReg(j));
} }
} }
static eReg subRegH(eReg reg); //TODO: move these into machine_x86
static eReg subRegL(eReg reg);
static bool isMemOff(eReg r); static bool isMemOff(eReg r);
static bool isSubRegisterOf(eReg reg, eReg parent);
}; };

37
src/BasicBlock.cpp
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@ -157,6 +157,7 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode,
if (_loopType) if (_loopType)
{ {
latch = pProc->m_dfsLast[this->latchNode]; latch = pProc->m_dfsLast[this->latchNode];
std::ostringstream ostr;
switch (_loopType) switch (_loopType)
{ {
case WHILE_TYPE: case WHILE_TYPE:
@ -170,7 +171,7 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode,
if (numHlIcodes > 1) if (numHlIcodes > 1)
{ {
/* Write the code for this basic block */ /* Write the code for this basic block */
writeBB(indLevel, pProc, numLoc); writeBB(ostr,indLevel, pProc, numLoc);
repCond = true; repCond = true;
} }
@ -178,34 +179,36 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode,
* the THEN path of the header node */ * the THEN path of the header node */
if (edges[ELSE].BBptr->dfsLastNum == loopFollow) if (edges[ELSE].BBptr->dfsLastNum == loopFollow)
{ {
COND_EXPR *old_expr=picode->hl()->expr(); picode->hl()->replaceExpr(picode->hl()->expr()->inverse());
string e=walkCondExpr (old_expr, pProc, numLoc);
picode->hl()->expr(picode->hl()->expr()->inverse());
delete old_expr;
} }
{ {
string e=walkCondExpr (picode->hl()->expr(), pProc, numLoc); string e=walkCondExpr (picode->hl()->expr(), pProc, numLoc);
cCode.appendCode( "\n%swhile (%s) {\n", indentStr(indLevel),e.c_str()); ostr << "\n"<<indentStr(indLevel)<<"while ("<<e<<") {\n";
} }
picode->invalidate(); picode->invalidate();
break; break;
case REPEAT_TYPE: case REPEAT_TYPE:
cCode.appendCode( "\n%sdo {\n", indentStr(indLevel)); ostr << "\n"<<indentStr(indLevel)<<"do {\n";
picode = &latch->back(); picode = &latch->back();
picode->invalidate(); picode->invalidate();
break; break;
case ENDLESS_TYPE: case ENDLESS_TYPE:
cCode.appendCode( "\n%sfor (;;) {\n", indentStr(indLevel)); ostr << "\n"<<indentStr(indLevel)<<"for (;;) {\n";
} }
cCode.appendCode(ostr.str());
stats.numHLIcode += 1; stats.numHLIcode += 1;
indLevel++; indLevel++;
} }
/* Write the code for this basic block */ /* Write the code for this basic block */
if (repCond == false) if (repCond == false)
writeBB (indLevel, pProc, numLoc); {
std::ostringstream ostr;
writeBB(ostr,indLevel, pProc, numLoc);
cCode.appendCode(ostr.str());
}
/* Check for end of path */ /* Check for end of path */
_nodeType = nodeType; _nodeType = nodeType;
@ -237,11 +240,15 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode,
indLevel--; indLevel--;
if (_loopType == WHILE_TYPE) if (_loopType == WHILE_TYPE)
{ {
std::ostringstream ostr;
/* Check if there is need to repeat other statements involved /* Check if there is need to repeat other statements involved
* in while condition, then, emit the loop trailer */ * in while condition, then, emit the loop trailer */
if (repCond) if (repCond)
writeBB (indLevel+1, pProc, numLoc); {
cCode.appendCode( "%s} /* end of while */\n",indentStr(indLevel)); writeBB(ostr,indLevel+1, pProc, numLoc);
}
ostr <<indentStr(indLevel)<< "} /* end of while */\n";
cCode.appendCode(ostr.str());
} }
else if (_loopType == ENDLESS_TYPE) else if (_loopType == ENDLESS_TYPE)
cCode.appendCode( "%s} /* end of loop */\n",indentStr(indLevel)); cCode.appendCode( "%s} /* end of loop */\n",indentStr(indLevel));
@ -346,13 +353,11 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode,
* Args: pBB: pointer to the current basic block. * Args: pBB: pointer to the current basic block.
* Icode: pointer to the array of icodes for current procedure. * Icode: pointer to the array of icodes for current procedure.
* lev: indentation level - used for formatting. */ * lev: indentation level - used for formatting. */
void BB::writeBB(int lev, Function * pProc, int *numLoc) void BB::writeBB(std::ostream &ostr,int lev, Function * pProc, int *numLoc)
{ {
/* Save the index into the code table in case there is a later goto /* Save the index into the code table in case there is a later goto
* into this instruction (first instruction of the BB) */ * into this instruction (first instruction of the BB) */
front().ll()->codeIdx = nextBundleIdx (&cCode.code); front().ll()->codeIdx = cCode.code.nextIdx();
//hli[start].codeIdx = nextBundleIdx (&cCode.code);
//for (i = start, last = i + length; i < last; i++)
/* Generate code for each hlicode that is not a HLI_JCOND */ /* Generate code for each hlicode that is not a HLI_JCOND */
@ -363,7 +368,7 @@ void BB::writeBB(int lev, Function * pProc, int *numLoc)
std::string line = pHli.hl()->write1HlIcode(pProc, numLoc); std::string line = pHli.hl()->write1HlIcode(pProc, numLoc);
if (!line.empty()) if (!line.empty())
{ {
cCode.appendCode( "%s%s", indentStr(lev), line.c_str()); ostr<<indentStr(lev)<<line;
stats.numHLIcode++; stats.numHLIcode++;
} }
if (option.verbose) if (option.verbose)

58
src/ast.cpp
View File

@ -459,7 +459,7 @@ int hlTypeSize (const COND_EXPR *expr, Function * pproc)
if (expr == NULL) if (expr == NULL)
return (2); /* for TYPE_UNKNOWN */ return (2); /* for TYPE_UNKNOWN */
switch (expr->type) { switch (expr->m_type) {
case BOOLEAN_OP: case BOOLEAN_OP:
first = hlTypeSize (expr->lhs(), pproc); first = hlTypeSize (expr->lhs(), pproc);
second = hlTypeSize (expr->rhs(), pproc); second = hlTypeSize (expr->rhs(), pproc);
@ -507,21 +507,21 @@ int hlTypeSize (const COND_EXPR *expr, Function * pproc)
/* Returns the type of the expression */ /* Returns the type of the expression */
hlType expType (const COND_EXPR *expr, Function * pproc) hlType COND_EXPR::expType(Function * pproc) const
{ {
hlType first, second; hlType first, second;
if (expr == NULL) if (this == nullptr)
return (TYPE_UNKNOWN); return (TYPE_UNKNOWN);
switch (expr->type) switch (m_type)
{ {
case BOOLEAN_OP: case BOOLEAN_OP:
first = expType (expr->lhs(), pproc); first = lhs()->expType ( pproc );
second = expType (expr->rhs(), pproc); second = rhs()->expType ( pproc );
if (first != second) if (first != second)
{ {
if (hlTypeSize (expr->lhs(), pproc) > hlTypeSize (expr->rhs(), pproc)) if (hlTypeSize (lhs(), pproc) > hlTypeSize (rhs(), pproc))
return (first); return (first);
else else
return (second); return (second);
@ -532,34 +532,34 @@ hlType expType (const COND_EXPR *expr, Function * pproc)
case POST_INC: case POST_DEC: case POST_INC: case POST_DEC:
case PRE_INC: case PRE_DEC: case PRE_INC: case PRE_DEC:
case NEGATION: case NEGATION:
return (expType (expr->expr.unaryExp, pproc)); return (expr.unaryExp->expType (pproc));
case ADDRESSOF: return (TYPE_PTR); /***????****/ case ADDRESSOF: return (TYPE_PTR); /***????****/
case DEREFERENCE: return (TYPE_PTR); case DEREFERENCE: return (TYPE_PTR);
case IDENTIFIER: case IDENTIFIER:
switch (expr->expr.ident.idType) switch (expr.ident.idType)
{ {
case GLOB_VAR: case GLOB_VAR:
return g_proj.symbolType(expr->expr.ident.idNode.globIdx); return g_proj.symbolType(expr.ident.idNode.globIdx);
case REGISTER: case REGISTER:
if (expr->expr.ident.regiType == BYTE_REG) if (expr.ident.regiType == BYTE_REG)
return (TYPE_BYTE_SIGN); return (TYPE_BYTE_SIGN);
else else
return (TYPE_WORD_SIGN); return (TYPE_WORD_SIGN);
case LOCAL_VAR: case LOCAL_VAR:
return (pproc->localId.id_arr[expr->expr.ident.idNode.localIdx].type); return (pproc->localId.id_arr[expr.ident.idNode.localIdx].type);
case PARAM: case PARAM:
return (pproc->args[expr->expr.ident.idNode.paramIdx].type); return (pproc->args[expr.ident.idNode.paramIdx].type);
case GLOB_VAR_IDX: case GLOB_VAR_IDX:
return (pproc->localId.id_arr[expr->expr.ident.idNode.idxGlbIdx].type); return (pproc->localId.id_arr[expr.ident.idNode.idxGlbIdx].type);
case CONSTANT: case CONSTANT:
return (TYPE_CONST); return (TYPE_CONST);
case STRING: case STRING:
return (TYPE_STR); return (TYPE_STR);
case LONG_VAR: case LONG_VAR:
return (pproc->localId.id_arr[expr->expr.ident.idNode.longIdx].type); return (pproc->localId.id_arr[expr.ident.idNode.longIdx].type);
case FUNCTION: case FUNCTION:
return (expr->expr.ident.idNode.call.proc->retVal.type); return (expr.ident.idNode.call.proc->retVal.type);
case OTHER: case OTHER:
return (TYPE_UNKNOWN); return (TYPE_UNKNOWN);
} /* eos */ } /* eos */
@ -579,7 +579,7 @@ void HlTypeSupport::performLongRemoval (eReg regi, LOCAL_ID *locId, COND_EXPR *t
IDENTTYPE* ident; /* ptr to an identifier */ IDENTTYPE* ident; /* ptr to an identifier */
eReg otherRegi; /* high or low part of long register */ eReg otherRegi; /* high or low part of long register */
switch (tree->type) { switch (tree->m_type) {
case BOOLEAN_OP: case BOOLEAN_OP:
break; break;
case POST_INC: case POST_DEC: case POST_INC: case POST_DEC:
@ -631,7 +631,7 @@ string walkCondExpr (const COND_EXPR* expr, Function * pProc, int* numLoc)
return ""; return "";
needBracket = true; needBracket = true;
switch (expr->type) switch (expr->m_type)
{ {
case BOOLEAN_OP: case BOOLEAN_OP:
outStr << "("; outStr << "(";
@ -642,7 +642,7 @@ string walkCondExpr (const COND_EXPR* expr, Function * pProc, int* numLoc)
break; break;
case NEGATION: case NEGATION:
if (expr->expr.unaryExp->type == IDENTIFIER) if (expr->expr.unaryExp->m_type == IDENTIFIER)
{ {
needBracket = false; needBracket = false;
outStr << "!"; outStr << "!";
@ -655,7 +655,7 @@ string walkCondExpr (const COND_EXPR* expr, Function * pProc, int* numLoc)
break; break;
case ADDRESSOF: case ADDRESSOF:
if (expr->expr.unaryExp->type == IDENTIFIER) if (expr->expr.unaryExp->m_type == IDENTIFIER)
{ {
needBracket = false; needBracket = false;
outStr << "&"; outStr << "&";
@ -669,7 +669,7 @@ string walkCondExpr (const COND_EXPR* expr, Function * pProc, int* numLoc)
case DEREFERENCE: case DEREFERENCE:
outStr << "*"; outStr << "*";
if (expr->expr.unaryExp->type == IDENTIFIER) if (expr->expr.unaryExp->m_type == IDENTIFIER)
needBracket = false; needBracket = false;
else else
outStr << "("; outStr << "(";
@ -793,7 +793,7 @@ COND_EXPR *COND_EXPR::clone() const
{ {
COND_EXPR* newExp=0; /* Expression node copy */ COND_EXPR* newExp=0; /* Expression node copy */
switch (type) switch (m_type)
{ {
case BOOLEAN_OP: case BOOLEAN_OP:
newExp = new COND_EXPR(*this); newExp = new COND_EXPR(*this);
@ -836,19 +836,13 @@ bool COND_EXPR::insertSubTreeReg (COND_EXPR *&tree, COND_EXPR *_expr, eReg regi,
} }
return false; return false;
} }
bool isSubRegisterOf(eReg reg,eReg parent)
{
if ((parent < rAX) || (parent > rBX))
return false; // only AX -> BX are coverede by subregisters
return ((reg==subRegH(parent)) || (reg == subRegL(parent)));
}
COND_EXPR *COND_EXPR::insertSubTreeReg (COND_EXPR *_expr, eReg regi,LOCAL_ID *locsym) COND_EXPR *COND_EXPR::insertSubTreeReg (COND_EXPR *_expr, eReg regi,LOCAL_ID *locsym)
{ {
eReg treeReg; eReg treeReg;
COND_EXPR *temp; COND_EXPR *temp;
switch (type) { switch (m_type) {
case IDENTIFIER: case IDENTIFIER:
if (expr.ident.idType == REGISTER) if (expr.ident.idType == REGISTER)
{ {
@ -857,7 +851,7 @@ COND_EXPR *COND_EXPR::insertSubTreeReg (COND_EXPR *_expr, eReg regi,LOCAL_ID *lo
{ {
return _expr; return _expr;
} }
else if(isSubRegisterOf(treeReg,regi)) /* uint16_t/uint8_t reg */ else if(Machine_X86::isSubRegisterOf(treeReg,regi)) /* uint16_t/uint8_t reg */
{ {
return _expr; return _expr;
} }
@ -928,7 +922,7 @@ bool COND_EXPR::insertSubTreeLongReg(COND_EXPR *_expr, COND_EXPR **tree, int lon
COND_EXPR *COND_EXPR::insertSubTreeLongReg(COND_EXPR *_expr, int longIdx) COND_EXPR *COND_EXPR::insertSubTreeLongReg(COND_EXPR *_expr, int longIdx)
{ {
COND_EXPR *temp; COND_EXPR *temp;
switch (type) switch (m_type)
{ {
case IDENTIFIER: case IDENTIFIER:
if (expr.ident.idNode.longIdx == longIdx) if (expr.ident.idNode.longIdx == longIdx)
@ -987,7 +981,7 @@ COND_EXPR *BinaryOperator::insertSubTreeLongReg(COND_EXPR *_expr, int longIdx)
/* Recursively deallocates the abstract syntax tree rooted at *exp */ /* Recursively deallocates the abstract syntax tree rooted at *exp */
void COND_EXPR::release() void COND_EXPR::release()
{ {
switch (type) switch (m_type)
{ {
case BOOLEAN_OP: case BOOLEAN_OP:
lhs()->release(); lhs()->release();

6
src/backend.cpp
View File

@ -163,7 +163,7 @@ void Project::writeGlobSymTable()
static void writeHeader (std::ostream &_ios, char *fileName) static void writeHeader (std::ostream &_ios, char *fileName)
{ {
/* Write header information */ /* Write header information */
newBundle (&cCode); cCode.init();
cCode.appendDecl( "/*\n"); cCode.appendDecl( "/*\n");
cCode.appendDecl( " * Input file\t: %s\n", fileName); cCode.appendDecl( " * Input file\t: %s\n", fileName);
cCode.appendDecl( " * File type\t: %s\n", (prog.fCOM)?"COM":"EXE"); cCode.appendDecl( " * File type\t: %s\n", (prog.fCOM)?"COM":"EXE");
@ -205,7 +205,7 @@ void Function::codeGen (std::ostream &fs)
BB *pBB; /* Pointer to basic block */ BB *pBB; /* Pointer to basic block */
/* Write procedure/function header */ /* Write procedure/function header */
newBundle (&cCode); cCode.init();
if (flg & PROC_IS_FUNC) /* Function */ if (flg & PROC_IS_FUNC) /* Function */
ostr<< "\n"<<TypeContainer::typeName(retVal.type)<<" "<<name<<" ("; ostr<< "\n"<<TypeContainer::typeName(retVal.type)<<" "<<name<<" (";
else /* Procedure */ else /* Procedure */
@ -254,7 +254,7 @@ void Function::codeGen (std::ostream &fs)
} }
} }
} }
cCode.appendDecl(ostr.str()); fs<<ostr.str();
/* Write procedure's code */ /* Write procedure's code */
if (flg & PROC_ASM) /* generate assembler */ if (flg & PROC_ASM) /* generate assembler */
{ {

24
src/bundle.cpp
View File

@ -13,27 +13,17 @@
#define deltaProcLines 20 #define deltaProcLines 20
using namespace std;
/* Allocates memory for a new bundle and initializes it to zero. */ /* Allocates memory for a new bundle and initializes it to zero. */
void newBundle (bundle *)
{
}
/* Returns the next available index into the table */
int nextBundleIdx (strTable *strTab)
{
return (strTab->size());
}
/* Adds the given label to the start of the line strTab[idx]. The first /* Adds the given label to the start of the line strTab[idx]. The first
* tab is removed and replaced by this label */ * tab is removed and replaced by this label */
void addLabelBundle (strTable &strTab, int idx, int label) void strTable::addLabelBundle (int idx, int label)
{ {
char s[lineSize]; char s[16];
sprintf (s, "l%ld: %s", label, strTab[idx].c_str()+4); sprintf (s, "l%d: ", label);
strTab[idx] = s; at(idx) = string(s)+at(idx).substr(4);
} }
@ -77,6 +67,10 @@ void bundle::appendCode(const char *format,...)
code.push_back(buf); code.push_back(buf);
va_end (args); va_end (args);
} }
void bundle::appendCode(const std::string &s)
{
code.push_back(s);
}
void bundle::appendDecl(const char *format,...) void bundle::appendDecl(const char *format,...)
{ {

301
src/control.cpp
View File

@ -26,7 +26,7 @@ typedef std::list<int> nodeList; /* dfsLast index to the node */
* during the dfs traversal (ie. s has a smaller dfsFirst number) or s == p, * during the dfs traversal (ie. s has a smaller dfsFirst number) or s == p,
* then it is a backedge. * then it is a backedge.
* Also incrementes the number of backedges entries to the header node. */ * Also incrementes the number of backedges entries to the header node. */
static boolT isBackEdge (BB * p,BB * s) static bool isBackEdge (BB * p,BB * s)
{ {
if (p->dfsFirstNum >= s->dfsFirstNum) if (p->dfsFirstNum >= s->dfsFirstNum)
{ {
@ -89,7 +89,7 @@ static void insertList (nodeList &l, int n)
/* Returns whether or not the node n (dfsLast numbering of a basic block) /* Returns whether or not the node n (dfsLast numbering of a basic block)
* is on the list l. */ * is on the list l. */
static boolT inList (nodeList &l, int n) static bool inList (const nodeList &l, int n)
{ {
return std::find(l.begin(),l.end(),n)!=l.end(); return std::find(l.begin(),l.end(),n)!=l.end();
} }
@ -113,15 +113,12 @@ static boolT inInt(BB * n, queue &q)
* The follow node is the closest node to the loop. */ * The follow node is the closest node to the loop. */
static void findEndlessFollow (Function * pProc, nodeList &loopNodes, BB * head) static void findEndlessFollow (Function * pProc, nodeList &loopNodes, BB * head)
{ {
int succ;
head->loopFollow = MAX; head->loopFollow = MAX;
nodeList::iterator p = loopNodes.begin(); for( int loop_node : loopNodes)
for( ;p != loopNodes.end();++p)
{ {
for (size_t j = 0; j < pProc->m_dfsLast[*p]->edges.size(); j++) for (TYPEADR_TYPE &typeaddr: pProc->m_dfsLast[loop_node]->edges)
{ {
succ = pProc->m_dfsLast[*p]->edges[j].BBptr->dfsLastNum; int succ = typeaddr.BBptr->dfsLastNum;
if ((! inList(loopNodes, succ)) && (succ < head->loopFollow)) if ((! inList(loopNodes, succ)) && (succ < head->loopFollow))
head->loopFollow = succ; head->loopFollow = succ;
} }
@ -352,7 +349,8 @@ static bool successor (int s, int h, Function * pProc)
* the list l, head and tail (dfsLast index to first and exit node of the * the list l, head and tail (dfsLast index to first and exit node of the
* case). */ * case). */
static void tagNodesInCase (BB * pBB, nodeList &l, int head, int tail) static void tagNodesInCase (BB * pBB, nodeList &l, int head, int tail)
{ int current, /* index to current node */ {
int current, /* index to current node */
i; i;
pBB->traversed = DFS_CASE; pBB->traversed = DFS_CASE;
@ -361,9 +359,11 @@ static void tagNodesInCase (BB * pBB, nodeList &l, int head, int tail)
{ {
insertList (l, current); insertList (l, current);
pBB->caseHead = head; pBB->caseHead = head;
for (i = 0; i < pBB->edges.size(); i++) for(TYPEADR_TYPE &edge : pBB->edges)
if (pBB->edges[i].BBptr->traversed != DFS_CASE) {
tagNodesInCase (pBB->edges[i].BBptr, l, head, tail); if (edge.BBptr->traversed != DFS_CASE)
tagNodesInCase (edge.BBptr, l, head, tail);
}
} }
} }
@ -418,13 +418,11 @@ void Function::structCases()
static void flagNodes (nodeList &l, int f, Function * pProc) static void flagNodes (nodeList &l, int f, Function * pProc)
{ {
nodeList::iterator p; nodeList::iterator p;
for(int idx : l)
p = l.begin();
while (p!=l.end())
{ {
pProc->m_dfsLast[*p]->ifFollow = f; pProc->m_dfsLast[idx]->ifFollow = f;
p = l.erase(p);
} }
l.clear();
} }
@ -482,26 +480,127 @@ void Function::structIfs ()
freeList (domDesc); freeList (domDesc);
} }
} }
bool Function::removeInEdge_Flag_and_ProcessLatch(BB *pbb,BB *a,BB *b)
{
/* Remove in-edge e to t */
auto iter = std::find(b->inEdges.begin(),b->inEdges.end(),a);
assert(iter!=b->inEdges.end());
b->inEdges.erase(iter); /* looses 1 arc */
a->flg |= INVALID_BB;
if (pbb->flg & IS_LATCH_NODE)
this->m_dfsLast[a->dfsLastNum] = pbb;
else
return true; /* to repeat this analysis */
return false;
}
/* Checks for compound conditions of basic blocks that have only 1 high void Function::replaceInEdge(BB* where, BB* which,BB* with)
{
auto iter=std::find(where->inEdges.begin(),where->inEdges.end(),which);
assert(iter!=where->inEdges.end());
*iter=with;
}
bool Function::Case_notX_or_Y(BB* pbb, BB* thenBB, BB* elseBB)
{
HLTYPE &hl1(*pbb->back().hl());
HLTYPE &hl2(*thenBB->back().hl());
BB* obb = elseBB->edges[THEN].BBptr;
/* Construct compound DBL_OR expression */
hl1.replaceExpr(hl1.expr()->inverse());
hl1.expr(COND_EXPR::boolOp (hl1.expr(), hl2.expr(), DBL_OR));
/* Replace in-edge to obb from e to pbb */
replaceInEdge(obb,elseBB,pbb);
/* New THEN and ELSE out-edges of pbb */
pbb->edges[THEN].BBptr = obb;
pbb->edges[ELSE].BBptr = thenBB;
/* Remove in-edge e to t */
return removeInEdge_Flag_and_ProcessLatch(pbb,elseBB,thenBB);
}
bool Function::Case_X_and_Y(BB* pbb, BB* thenBB, BB* elseBB)
{
HLTYPE &hl1(*pbb->back().hl());
HLTYPE &hl2(*thenBB->back().hl());
BB* obb = elseBB->edges[ELSE].BBptr;
/* Construct compound DBL_AND expression */
hl1.expr(COND_EXPR::boolOp (hl1.expr(),hl2.expr(), DBL_AND));
/* Replace in-edge to obb from e to pbb */
replaceInEdge(obb,elseBB,pbb);
/* New ELSE out-edge of pbb */
pbb->edges[ELSE].BBptr = obb;
/* Remove in-edge e to t */
return removeInEdge_Flag_and_ProcessLatch(pbb,elseBB,thenBB);
}
bool Function::Case_notX_and_Y(BB* pbb, BB* thenBB, BB* elseBB)
{
HLTYPE &hl1(*pbb->back().hl());
HLTYPE &hl2(*thenBB->back().hl());
BB* obb = thenBB->edges[ELSE].BBptr;
/* Construct compound DBL_AND expression */
hl1.replaceExpr(hl1.expr()->inverse());
hl1.expr(COND_EXPR::boolOp (hl1.expr(), hl2.expr(), DBL_AND));
/* Replace in-edge to obb from t to pbb */
replaceInEdge(obb,thenBB,pbb);
/* New THEN and ELSE out-edges of pbb */
pbb->edges[THEN].BBptr = elseBB;
pbb->edges[ELSE].BBptr = obb;
/* Remove in-edge t to e */
return removeInEdge_Flag_and_ProcessLatch(pbb,thenBB,elseBB);
}
bool Function::Case_X_or_Y(BB* pbb, BB* thenBB, BB* elseBB)
{
HLTYPE &hl1(*pbb->back().hl());
HLTYPE &hl2(*thenBB->back().hl());
BB * obb = thenBB->edges[THEN].BBptr;
/* Construct compound DBL_OR expression */
hl1.expr(COND_EXPR::boolOp (hl1.expr(), hl2.expr(), DBL_OR));
/* Replace in-edge to obb from t to pbb */
auto iter=find(obb->inEdges.begin(),obb->inEdges.end(),thenBB);
if(iter!=obb->inEdges.end())
*iter = pbb;
/* New THEN out-edge of pbb */
pbb->edges[THEN].BBptr = obb;
/* Remove in-edge t to e */
return removeInEdge_Flag_and_ProcessLatch(pbb,thenBB,elseBB);
}
/** \brief Checks for compound conditions of basic blocks that have only 1 high
* level instruction. Whenever these blocks are found, they are merged * level instruction. Whenever these blocks are found, they are merged
* into one block with the appropriate condition */ * into one block with the appropriate condition */
void Function::compoundCond() void Function::compoundCond()
{ {
int i; //j, k, numOutEdges BB * pbb, * thenBB, * elseBB;
BB * pbb, * t, * e, * obb;//,* pred; bool change = true;
ICODE * picode, * ticode;
boolT change;
change = true;
while (change) while (change)
{ {
change = false; change = false;
/* Traverse nodes in postorder, this way, the header node of a /* Traverse nodes in postorder, this way, the header node of a
* compound condition is analysed first */ * compound condition is analysed first */
for (i = 0; i < this->numBBs; i++) for (int i = 0; i < this->numBBs; i++)
{ {
pbb = this->m_dfsLast[i]; pbb = this->m_dfsLast[i];
if (pbb->flg & INVALID_BB) if (pbb->flg & INVALID_BB)
@ -510,152 +609,44 @@ void Function::compoundCond()
if (pbb->nodeType != TWO_BRANCH) if (pbb->nodeType != TWO_BRANCH)
continue; continue;
t = pbb->edges[THEN].BBptr; thenBB = pbb->edges[THEN].BBptr;
e = pbb->edges[ELSE].BBptr; elseBB = pbb->edges[ELSE].BBptr;
change = true; //assume change
/* Check (X || Y) case */ /* Check (X || Y) case */
if ((t->nodeType == TWO_BRANCH) && (t->numHlIcodes == 1) && if ((thenBB->nodeType == TWO_BRANCH) && (thenBB->numHlIcodes == 1) &&
(t->inEdges.size() == 1) && (t->edges[ELSE].BBptr == e)) (thenBB->inEdges.size() == 1) && (thenBB->edges[ELSE].BBptr == elseBB))
{ {
obb = t->edges[THEN].BBptr; if(Case_X_or_Y(pbb, thenBB, elseBB))
--i;
/* Construct compound DBL_OR expression */
picode = &pbb->back();
ticode = &t->back();
picode->hl()->expr(COND_EXPR::boolOp (picode->hl()->expr(), ticode->hl()->expr(), DBL_OR));
/* Replace in-edge to obb from t to pbb */
{
auto iter=find(obb->inEdges.begin(),obb->inEdges.end(),t);
if(iter!=obb->inEdges.end())
*iter = pbb;
}
/* New THEN out-edge of pbb */
pbb->edges[THEN].BBptr = obb;
/* Remove in-edge t to e */
auto iter=std::find(e->inEdges.begin(),e->inEdges.end(),t);
assert(iter!=e->inEdges.end());
e->inEdges.erase(iter);
t->flg |= INVALID_BB;
if (pbb->flg & IS_LATCH_NODE)
this->m_dfsLast[t->dfsLastNum] = pbb;
else
i--; /* to repeat this analysis */
change = true;
} }
/* Check (!X && Y) case */ /* Check (!X && Y) case */
else if ((t->nodeType == TWO_BRANCH) && (t->numHlIcodes == 1) && else if ((thenBB->nodeType == TWO_BRANCH) && (thenBB->numHlIcodes == 1) &&
(t->inEdges.size() == 1) && (t->edges[THEN].BBptr == e)) (thenBB->inEdges.size() == 1) && (thenBB->edges[THEN].BBptr == elseBB))
{ {
obb = t->edges[ELSE].BBptr; if(Case_notX_and_Y(pbb, thenBB, elseBB))
--i;
/* Construct compound DBL_AND expression */
picode = &pbb->back();
ticode = &t->back();
COND_EXPR *oldexpr=picode->hl()->expr();
picode->hl()->expr(picode->hl()->expr()->inverse());
delete oldexpr;
picode->hl()->expr(COND_EXPR::boolOp (picode->hl()->expr(), ticode->hl()->expr(), DBL_AND));
/* Replace in-edge to obb from t to pbb */
auto iter=std::find(obb->inEdges.begin(),obb->inEdges.end(),t);
assert(iter!=obb->inEdges.end());
*iter=pbb;
/* New THEN and ELSE out-edges of pbb */
pbb->edges[THEN].BBptr = e;
pbb->edges[ELSE].BBptr = obb;
/* Remove in-edge t to e */
iter=std::find(e->inEdges.begin(),e->inEdges.end(),t);
assert(iter!=e->inEdges.end());
e->inEdges.erase(iter); /* looses 1 arc */
t->flg |= INVALID_BB;
if (pbb->flg & IS_LATCH_NODE)
this->m_dfsLast[t->dfsLastNum] = pbb;
else
i--; /* to repeat this analysis */
change = true;
} }
/* Check (X && Y) case */ /* Check (X && Y) case */
else if ((e->nodeType == TWO_BRANCH) && (e->numHlIcodes == 1) && else if ((elseBB->nodeType == TWO_BRANCH) && (elseBB->numHlIcodes == 1) &&
(e->inEdges.size()==1) && (e->edges[THEN].BBptr == t)) (elseBB->inEdges.size()==1) && (elseBB->edges[THEN].BBptr == thenBB))
{ {
obb = e->edges[ELSE].BBptr; if(Case_X_and_Y(pbb, thenBB, elseBB ))
--i;
/* Construct compound DBL_AND expression */
picode = &pbb->back();
ticode = &t->back();
picode->hl()->expr(COND_EXPR::boolOp (picode->hl()->expr(),ticode->hl()->expr(), DBL_AND));
/* Replace in-edge to obb from e to pbb */
auto iter = std::find(obb->inEdges.begin(),obb->inEdges.end(),e);
assert(iter!=obb->inEdges.end());
*iter=pbb;
/* New ELSE out-edge of pbb */
pbb->edges[ELSE].BBptr = obb;
/* Remove in-edge e to t */
iter = std::find(t->inEdges.begin(),t->inEdges.end(),e);
assert(iter!=t->inEdges.end());
t->inEdges.erase(iter);
e->flg |= INVALID_BB;
if (pbb->flg & IS_LATCH_NODE)
this->m_dfsLast[e->dfsLastNum] = pbb;
else
i--; /* to repeat this analysis */
change = true;
} }
/* Check (!X || Y) case */ /* Check (!X || Y) case */
else if ((e->nodeType == TWO_BRANCH) && (e->numHlIcodes == 1) && else if ((elseBB->nodeType == TWO_BRANCH) && (elseBB->numHlIcodes == 1) &&
(e->inEdges.size() == 1) && (e->edges[ELSE].BBptr == t)) (elseBB->inEdges.size() == 1) && (elseBB->edges[ELSE].BBptr == thenBB))
{ {
obb = e->edges[THEN].BBptr; if(Case_notX_or_Y(pbb, thenBB, elseBB ))
--i;
/* Construct compound DBL_OR expression */
picode = &pbb->back();
ticode = &t->back();
COND_EXPR *oldexp=picode->hl()->expr();
picode->hl()->expr(picode->hl()->expr()->inverse());
delete oldexp;
picode->hl()->expr(COND_EXPR::boolOp (picode->hl()->expr(), ticode->hl()->expr(), DBL_OR));
//picode->hl()->expr() = exp;
/* Replace in-edge to obb from e to pbb */
auto iter = std::find(obb->inEdges.begin(),obb->inEdges.end(),e);
assert(iter!=obb->inEdges.end());
*iter=pbb;
/* New THEN and ELSE out-edges of pbb */
pbb->edges[THEN].BBptr = obb;
pbb->edges[ELSE].BBptr = t;
/* Remove in-edge e to t */
iter = std::find(t->inEdges.begin(),t->inEdges.end(),e);
assert(iter!=t->inEdges.end());
t->inEdges.erase(iter);
e->flg |= INVALID_BB;
if (pbb->flg & IS_LATCH_NODE)
this->m_dfsLast[e->dfsLastNum] = pbb;
else
i--; /* to repeat this analysis */
change = true;
} }
else
change = false; // otherwise we changed nothing
} }
} }
} }

21
src/dataflow.cpp
View File

@ -355,7 +355,7 @@ void Function::liveRegAnalysis (std::bitset<32> &in_liveOut)
break; break;
default: default:
ticode.du1.numRegsDef = 0; ticode.du1.numRegsDef = 0;
fprintf(stderr,"Function::liveRegAnalysis : Unknown return type %d, assume 0\n",pcallee->retVal.type); //fprintf(stderr,"Function::liveRegAnalysis : Unknown return type %d, assume 0\n",pcallee->retVal.type);
} /*eos*/ } /*eos*/
/* Propagate def/use results to calling icode */ /* Propagate def/use results to calling icode */
@ -605,7 +605,7 @@ bool COND_EXPR::xClear (iICODE f, iICODE t, iICODE lastBBinst, Function * pproc)
boolT res; boolT res;
uint8_t regi; uint8_t regi;
switch (type) switch (m_type)
{ {
case IDENTIFIER: case IDENTIFIER:
if (expr.ident.idType == REGISTER) if (expr.ident.idType == REGISTER)
@ -691,7 +691,14 @@ static int processCArg (Function * pp, Function * pProc, ICODE * picode, int num
else /* user function */ else /* user function */
{ {
if (pp->args.numArgs > 0) if (pp->args.numArgs > 0)
pp->args.adjustForArgType (numArgs, expType (_exp, pProc)); {
if(_exp==NULL)
{
fprintf(stderr,"Would try to adjustForArgType with null _exp\n");
}
else
pp->args.adjustForArgType (numArgs, _exp->expType (pProc));
}
} }
res = picode->newStkArg (_exp, (llIcode)picode->ll()->getOpcode(), pProc); res = picode->newStkArg (_exp, (llIcode)picode->ll()->getOpcode(), pProc);
@ -776,7 +783,13 @@ void Function::processHliCall(COND_EXPR *_exp, iICODE picode)
else /* user function */ else /* user function */
{ {
if (pp->args.numArgs >0) if (pp->args.numArgs >0)
pp->args.adjustForArgType (numArgs,expType (_exp, this)); {
if(_exp==NULL)
{
fprintf(stderr,"Would try to adjustForArgType with null _exp\n");
}
pp->args.adjustForArgType (numArgs,_exp->expType (this));
}
res = picode->newStkArg (_exp,(llIcode)picode->ll()->getOpcode(), this); res = picode->newStkArg (_exp,(llIcode)picode->ll()->getOpcode(), this);
} }
if (res == false) if (res == false)

82
src/disassem.cpp
View File

@ -9,7 +9,6 @@
#include <iomanip> #include <iomanip>
#include <stdio.h> #include <stdio.h>
#include <string.h> #include <string.h>
#include <malloc.h> /* For free() */
#include "dcc.h" #include "dcc.h"
#include "symtab.h" #include "symtab.h"
@ -17,9 +16,7 @@
// Note: for the time being, there is no interactive disassembler // Note: for the time being, there is no interactive disassembler
// for unix // for unix
#ifndef __UNIX__
#include <conio.h> // getch() etc
#endif
using namespace std; using namespace std;
@ -30,37 +27,6 @@ using namespace std;
#define POS_OPR2 POS_OPR+WID_PTR /* Position of operand after "xword ptr" */ #define POS_OPR2 POS_OPR+WID_PTR /* Position of operand after "xword ptr" */
#define POS_CMT 54 /* Position of comment */ #define POS_CMT 54 /* Position of comment */
#define DELTA_ICODE 16 /* Number of icodes to realloc by each time */
/* The following opcodes are for mod != 3 */
static const char *szFlops1[] =
{
/* 0 1 2 3 4 5 6 7 */
"FADD", "FMUL", "FCOM", "FCOMP", "FSUB", "FSUBR", "FDIV", "FDIVR", /* 00 */
"FLD", "???", "FST", "???", "FLDENV","FLDCW", "FSTENV","FSTSW", /* 08 */
"FIADD", "FIMUL", "FICOM","FICOMP","FISUB", "FISUBR","FIDIV", "FIDIVR", /* 10 */
"FILD", "???", "FIST", "FISTP", "???", "???", "???", "FSTP", /* 18 */
"FADD", "FMUL", "FCOM", "FCOMP", "FSUB", "FSUBR", "FDIV", "FDIVR", /* 20 */
"FLD", "FLD", "FST", "FSTP", "FRESTOR","???", "FSAVE", "FSTSW", /* 28 */
"FIADD", "FIMUL", "FICOM","FICOMP","FISUB", "FISUBR","FIDIV", "FIDIVR", /* 30 */
"FILD", "???", "FIST", "FISTP", "FBLD", "???", "FBSTP", "FISTP" /* 38 */
};
/* The following opcodes are for mod == 3 */
static const char *szFlops2[] =
{
/* 0 1 2 3 4 5 6 7 */
"FADD", "FMUL", "FCOM", "FCOMP", "FSUB", "FSUBR", "FDIV", "FDIVR", /* 00 */
"FLD", "FXCH", "FNOP", "???", "", "", "", "", /* 08 */
"FIADD", "FIMUL", "FICOM","FICOMP","FISUB", "", "FIDIV", "FIDIVR", /* 10 */
"FILD", "???", "FIST", "FISTP", "???", "???", "???", "FSTP", /* 18 */
"FADD", "FMUL", "FCOM", "FCOMP", "FSUB", "FSUBR", "FDIV", "FDIVR", /* 20 */
"FFREE", "FSTP", "FST", "???", "FUCOM", "FUCOMP","???", "???", /* 28 */
"FADDP", "FMULP", "FICOM","", "FSUBRP","FISUBR","FDIVRP","FDIVP", /* 30 */
"FILD", "???", "FIST", "FISTP", "", "???", "FBSTP", "FISTP" /* 38 */
};
static const char *szFlops0C[] = static const char *szFlops0C[] =
{ {
"FCHS", "FABS", "???", "???", "FTST", "FXAM", "???", "???" "FCHS", "FABS", "???", "???", "FTST", "FXAM", "???", "???"
@ -102,21 +68,15 @@ static const char *szFlops3C[] =
}; };
//static const char *szIndex[8] = {"bx+si", "bx+di", "bp+si", "bp+di", "si", "di","bp","bx" };
//static const char *szBreg[8] = { "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" };
//static const char *szWreg[12] = { "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
// "es", "cs", "ss", "ds" };
static const char *szPtr[2] = { "word ptr ", "byte ptr " }; static const char *szPtr[2] = { "word ptr ", "byte ptr " };
//void dis1LineOp(int i, boolT fWin, char attr, uint16_t *len, Function * pProc);
static void formatRM(ostringstream &p, uint32_t flg, const LLOperand &pm); static void formatRM(ostringstream &p, uint32_t flg, const LLOperand &pm);
static ostringstream &strDst(ostringstream &os, uint32_t flg, LLOperand &pm); static ostringstream &strDst(ostringstream &os, uint32_t flg, LLOperand &pm);
static char *strHex(uint32_t d); static char *strHex(uint32_t d);
static int checkScanned(uint32_t pcCur); //static int checkScanned(uint32_t pcCur);
static void setProc(Function * proc); //static void setProc(Function * proc);
static void dispData(uint16_t dataSeg); //static void dispData(uint16_t dataSeg);
boolT callArg(uint16_t off, char *temp); /* Check for procedure name */ boolT callArg(uint16_t off, char *temp); /* Check for procedure name */
//static FILE *dis_g_fp; //static FILE *dis_g_fp;
@ -133,10 +93,9 @@ struct POSSTACK_ENTRY
int ic; /* An icode offset */ int ic; /* An icode offset */
Function * pProc; /* A pointer to a PROCEDURE structure */ Function * pProc; /* A pointer to a PROCEDURE structure */
} ; } ;
vector<POSSTACK_ENTRY> posStack; /* position stack */ static vector<POSSTACK_ENTRY> posStack; /* position stack */
uint8_t iPS; /* Index into the stack */ static uint8_t iPS; /* Index into the stack */
//static char cbuf[256]; /* Has to be 256 for wgetstr() to work */
// These are "curses equivalent" functions. (Used to use curses for all this, // These are "curses equivalent" functions. (Used to use curses for all this,
// but it was too much of a distribution hassle // but it was too much of a distribution hassle
@ -197,10 +156,9 @@ void Disassembler::disassem(Function * ppProc)
fatalError(CANNOT_OPEN, p); fatalError(CANNOT_OPEN, p);
} }
} }
pc=pProc->Icode;
/* Create temporary code array */ /* Create temporary code array */
// Mike: needs objectising! // Mike: needs objectising!
//pc = (ICODE *)memcpy(allocMem(cb), pProc->Icode.GetFirstIcode(), (size_t)cb); pc=pProc->Icode;
if (pass == 1) if (pass == 1)
{ {
@ -577,11 +535,11 @@ void Disassembler::dis1Line(LLInst &inst,int loc_ip, int pass)
/* output to .a1 or .a2 file */ /* output to .a1 or .a2 file */
if (not inst.testFlags(SYNTHETIC) ) if (not inst.testFlags(SYNTHETIC) )
{ {
sprintf(buf,"%03ld %06lX",loc_ip, inst.label); sprintf(buf,"%03d %06X",loc_ip, inst.label);
} }
else /* SYNTHETIC instruction */ else /* SYNTHETIC instruction */
{ {
sprintf(buf,"%03ld ",loc_ip); sprintf(buf,"%03d ",loc_ip);
result_stream<<";Synthetic inst"; result_stream<<";Synthetic inst";
} }
m_fp<<buf<< " " << result_stream.str() << "\n"; m_fp<<buf<< " " << result_stream.str() << "\n";
@ -600,9 +558,7 @@ static void formatRM(std::ostringstream &p, uint32_t flg, const LLOperand &pm)
if (pm.segOver) if (pm.segOver)
{ {
p <<Machine_X86::regName(pm.segOver)<<':'; p <<Machine_X86::regName(pm.segOver)<<':';
//strcat(strcpy(seg, szWreg[pm.segOver - rAX]), ":");
} }
//else *seg = '\0';
if (pm.regi == rUNDEF) if (pm.regi == rUNDEF)
{ {
@ -611,10 +567,6 @@ static void formatRM(std::ostringstream &p, uint32_t flg, const LLOperand &pm)
else if (pm.isReg()) else if (pm.isReg())
{ {
p<<Machine_X86::regName(pm.regi); p<<Machine_X86::regName(pm.regi);
// if(flg & B)
// p << szBreg[pm.regi - rAL];
// else
// p << szWreg[pm.regi - rAX];
} }
else if (pm.off) else if (pm.off)
@ -699,35 +651,35 @@ void LLInst::flops(std::ostringstream &out)
if ( not dst.isReg() ) if ( not dst.isReg() )
{ {
/* The mod/rm mod bits are not set to 11 (i.e. register). This is the normal floating point opcode */ /* The mod/rm mod bits are not set to 11 (i.e. register). This is the normal floating point opcode */
out<<szFlops1[op]<<' '; out<<Machine_X86::floatOpName(op)<<' ';
out <<setw(10); out <<setw(10);
if ((op == 0x29) || (op == 0x1F)) if ((op == 0x29) || (op == 0x1F))
{ {
strcpy(bf, "tbyte ptr "); out << "tbyte ptr ";
} }
else switch (op & 0x30) else switch (op & 0x30)
{ {
case 0x00: case 0x00:
case 0x10: case 0x10:
strcpy(bf, "dword ptr "); out << "dword ptr ";
break; break;
case 0x20: case 0x20:
strcpy(bf, "qword ptr "); out << "qword ptr ";
break; break;
case 0x30: case 0x30:
switch (op) switch (op)
{ {
case 0x3C: /* FBLD */ case 0x3C: /* FBLD */
case 0x3E: /* FBSTP */ case 0x3E: /* FBSTP */
strcpy(bf, "tbyte ptr "); out << "tbyte ptr ";
break; break;
case 0x3D: /* FILD 64 bit */ case 0x3D: /* FILD 64 bit */
case 0x3F: /* FISTP 64 bit */ case 0x3F: /* FISTP 64 bit */
strcpy(bf, "qword ptr "); out << "qword ptr ";
break; break;
default: default:
strcpy(bf, "uint16_t ptr "); out << "uint16_t ptr ";
break; break;
} }
} }
@ -769,7 +721,7 @@ void LLInst::flops(std::ostringstream &out)
out << szFlops3C[destRegIdx]; out << szFlops3C[destRegIdx];
break; break;
default: default:
out << szFlops2[op]; out << Machine_X86::floatOpName(0x40+op);
if ((op >= 0x20) && (op <= 0x27)) if ((op >= 0x20) && (op <= 0x27))
{ {
/* This is the ST(i), ST form. */ /* This is the ST(i), ST form. */

4
src/hlicode.cpp
View File

@ -452,7 +452,7 @@ COND_EXPR *COND_EXPR::inverse () const
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DBL_OR, DBL_AND}; DUMMY, DBL_OR, DBL_AND};
COND_EXPR *res=0; COND_EXPR *res=0;
if (type == BOOLEAN_OP) if (m_type == BOOLEAN_OP)
{ {
switch ( op() ) switch ( op() )
{ {
@ -476,7 +476,7 @@ COND_EXPR *COND_EXPR::inverse () const
} /* eos */ } /* eos */
} }
else if (type == NEGATION) //TODO: memleak here else if (m_type == NEGATION) //TODO: memleak here
{ {
return expr.unaryExp->clone(); return expr.unaryExp->clone();
} }

2
src/icode.cpp
View File

@ -75,7 +75,7 @@ void LLInst::emitGotoLabel (int indLevel)
/* Node has been traversed already, so backpatch this label into /* Node has been traversed already, so backpatch this label into
* the code */ * the code */
addLabelBundle (cCode.code, codeIdx, hllLabNum); cCode.code.addLabelBundle (codeIdx, hllLabNum);
} }
cCode.appendCode( "%sgoto L%ld;\n", indentStr(indLevel), hllLabNum); cCode.appendCode( "%sgoto L%ld;\n", indentStr(indLevel), hllLabNum);
stats.numHLIcode++; stats.numHLIcode++;

51
src/machine_x86.cpp
View File

@ -43,12 +43,48 @@ static const std::string szOps[] =
"STD", "STI", "STOS", "REP STOS", "SUB", "TEST", "WAIT", "XCHG", "STD", "STI", "STOS", "REP STOS", "SUB", "TEST", "WAIT", "XCHG",
"XLAT", "XOR", "INTO", "NOP", "REPNE", "REPE", "MOD" "XLAT", "XOR", "INTO", "NOP", "REPNE", "REPE", "MOD"
}; };
/* The following opcodes are for mod != 3 */
static std::string szFlops1[] =
{
/* 0 1 2 3 4 5 6 7 */
"FADD", "FMUL", "FCOM", "FCOMP", "FSUB", "FSUBR", "FDIV", "FDIVR", /* 00 */
"FLD", "???", "FST", "???", "FLDENV","FLDCW", "FSTENV","FSTSW", /* 08 */
"FIADD", "FIMUL", "FICOM","FICOMP","FISUB", "FISUBR","FIDIV", "FIDIVR", /* 10 */
"FILD", "???", "FIST", "FISTP", "???", "???", "???", "FSTP", /* 18 */
"FADD", "FMUL", "FCOM", "FCOMP", "FSUB", "FSUBR", "FDIV", "FDIVR", /* 20 */
"FLD", "FLD", "FST", "FSTP", "FRESTOR","???", "FSAVE", "FSTSW", /* 28 */
"FIADD", "FIMUL", "FICOM","FICOMP","FISUB", "FISUBR","FIDIV", "FIDIVR", /* 30 */
"FILD", "???", "FIST", "FISTP", "FBLD", "???", "FBSTP", "FISTP" /* 38 */
};
/* The following opcodes are for mod == 3 */
static std::string szFlops2[] =
{
/* 0 1 2 3 4 5 6 7 */
"FADD", "FMUL", "FCOM", "FCOMP", "FSUB", "FSUBR", "FDIV", "FDIVR", /* 00 */
"FLD", "FXCH", "FNOP", "???", "", "", "", "", /* 08 */
"FIADD", "FIMUL", "FICOM","FICOMP","FISUB", "", "FIDIV", "FIDIVR", /* 10 */
"FILD", "???", "FIST", "FISTP", "???", "???", "???", "FSTP", /* 18 */
"FADD", "FMUL", "FCOM", "FCOMP", "FSUB", "FSUBR", "FDIV", "FDIVR", /* 20 */
"FFREE", "FSTP", "FST", "???", "FUCOM", "FUCOMP","???", "???", /* 28 */
"FADDP", "FMULP", "FICOM","", "FSUBRP","FISUBR","FDIVRP","FDIVP", /* 30 */
"FILD", "???", "FIST", "FISTP", "", "???", "FBSTP", "FISTP" /* 38 */
};
const std::string &Machine_X86::opcodeName(unsigned r) const std::string &Machine_X86::opcodeName(unsigned r)
{ {
assert(r<(sizeof(szOps)/sizeof(std::string))); assert(r<(sizeof(szOps)/sizeof(std::string)));
return szOps[r]; return szOps[r];
} }
const std::string &Machine_X86::floatOpName(unsigned r)
{
if(r>=(sizeof(szFlops1)/sizeof(std::string)))
{
r-= (sizeof(szFlops1)/sizeof(std::string));
assert(r<(sizeof(szFlops2)/sizeof(std::string)));
return szFlops2[r];
}
return szFlops1[r];
}
bool Machine_X86::physicalReg(eReg r) bool Machine_X86::physicalReg(eReg r)
{ {
@ -58,3 +94,18 @@ bool Machine_X86::isMemOff(eReg r)
{ {
return r == 0 || r >= INDEX_BX_SI; return r == 0 || r >= INDEX_BX_SI;
} }
//TODO: Move these to Machine_X86
eReg Machine_X86::subRegH(eReg reg)
{
return eReg((int)reg + (int)rAH-(int)rAX);
}
eReg Machine_X86::subRegL(eReg reg)
{
return eReg((int)reg + (int)rAL-(int)rAX);
}
bool Machine_X86::isSubRegisterOf(eReg reg,eReg parent)
{
if ((parent < rAX) || (parent > rBX))
return false; // only AX -> BX are coverede by subregisters
return ((reg==subRegH(parent)) || (reg == subRegL(parent)));
}

9
src/parser.cpp
View File

@ -20,15 +20,6 @@ static void process_MOV(LLInst &ll, STATE * pstate);
static SYM * lookupAddr (LLOperand *pm, STATE * pstate, int size, uint16_t duFlag); static SYM * lookupAddr (LLOperand *pm, STATE * pstate, int size, uint16_t duFlag);
void interactDis(Function * initProc, int ic); void interactDis(Function * initProc, int ic);
static uint32_t SynthLab; static uint32_t SynthLab;
//TODO: Move these to Machine_X86
/*constexpr */eReg subRegH(eReg reg)
{
return eReg((int)reg + (int)rAH-(int)rAX);
}
/*constexpr */eReg subRegL(eReg reg)
{
return eReg((int)reg + (int)rAL-(int)rAX);
}
/* Parses the program, builds the call graph, and returns the list of /* Parses the program, builds the call graph, and returns the list of
* procedures found */ * procedures found */

6
src/procs.cpp
View File

@ -224,7 +224,7 @@ bool CallType::newStkArg(COND_EXPR *exp, llIcode opcode, Function * pproc)
* long references to another segment) */ * long references to another segment) */
if (exp) if (exp)
{ {
if ((exp->type == IDENTIFIER) && (exp->expr.ident.idType == REGISTER)) if ((exp->m_type == IDENTIFIER) && (exp->expr.ident.idType == REGISTER))
{ {
regi = pproc->localId.id_arr[exp->expr.ident.idNode.regiIdx].id.regi; regi = pproc->localId.id_arr[exp->expr.ident.idNode.regiIdx].id.regi;
if ((regi >= rES) && (regi <= rDS)) if ((regi >= rES) && (regi <= rDS))
@ -264,8 +264,8 @@ void adjustActArgType (COND_EXPR *exp, hlType forType, Function * pproc)
if (exp == NULL) if (exp == NULL)
return; return;
actType = expType (exp, pproc); actType = exp-> expType (pproc);
if (((actType == forType) || (exp->type != IDENTIFIER))) if (((actType == forType) || (exp->m_type != IDENTIFIER)))
return; return;
switch (forType) switch (forType)
{ {

2
src/scanner.cpp
View File

@ -437,7 +437,7 @@ static void setAddress(int i, boolT fdst, uint16_t seg, int16_t reg, uint16_t of
pm->off = (int16_t)off; pm->off = (int16_t)off;
if (reg && reg < INDEX_BX_SI && (stateTable[i].flg & B)) if (reg && reg < INDEX_BX_SI && (stateTable[i].flg & B))
{ {
pm->regi = subRegL(pm->regi); pm->regi = Machine_X86::subRegL(pm->regi);
} }
if (seg) /* So we can catch invalid use of segment overrides */ if (seg) /* So we can catch invalid use of segment overrides */

120
tests/prev_base/DHAMP.EXE.a1
View File

@ -107,17 +107,17 @@
095 0009BA A12006 MOV ax, [620h] 095 0009BA A12006 MOV ax, [620h]
096 0009BD 52 PUSH dx 096 0009BD 52 PUSH dx
097 0009BE 50 PUSH ax 097 0009BE 50 PUSH ax
098 0009BF CD378626FF ESC FILD [bp-0DAh] 098 0009BF CD378626FF ESC FILD dword ptr [bp-0DAh]
099 0009C4 CD3D INT 3Dh /* Unknown int */ 099 0009C4 CD3D INT 3Dh /* Unknown int */
100 0009C6 83C404 ADD sp, 4 100 0009C6 83C404 ADD sp, 4
101 0009C9 83EC08 SUB sp, 8 101 0009C9 83EC08 SUB sp, 8
102 0009CC CD399E22FF ESC FSTP [bp-0DEh] 102 0009CC CD399E22FF ESC FSTP qword ptr [bp-0DEh]
103 0009D1 CD3D INT 3Dh /* Unknown int */ 103 0009D1 CD3D INT 3Dh /* Unknown int */
104 0009D3 9A21028B00 CALL far ptr proc_7 104 0009D3 9A21028B00 CALL far ptr proc_7
105 0009D8 83C408 ADD sp, 8 105 0009D8 83C408 ADD sp, 8
106 0009DB CD391E2406 ESC FSTP [624h] 106 0009DB CD391E2406 ESC FSTP qword ptr [624h]
107 0009E0 CD3D INT 3Dh /* Unknown int */ 107 0009E0 CD3D INT 3Dh /* Unknown int */
108 0009E2 FF362A06 PUSH word ptr [62Ah] 108 0009E2 FF362A06 PUSH word ptr [62Ah]
@ -135,7 +135,7 @@
120 000A0B FF362406 PUSH word ptr [624h] 120 000A0B FF362406 PUSH word ptr [624h]
121 000A0F 9AE6028B00 CALL far ptr proc_9 121 000A0F 9AE6028B00 CALL far ptr proc_9
122 000A14 83C408 ADD sp, 8 122 000A14 83C408 ADD sp, 8
123 000A17 CD395EF8 ESC FSTP [bp-8] 123 000A17 CD395EF8 ESC FSTP qword ptr [bp-8]
124 000A1B CD3D INT 3Dh /* Unknown int */ 124 000A1B CD3D INT 3Dh /* Unknown int */
125 000A1D FF76FE PUSH word ptr [bp-2] 125 000A1D FF76FE PUSH word ptr [bp-2]
@ -398,9 +398,9 @@
000 000AD1 55 PUSH bp 000 000AD1 55 PUSH bp
001 000AD2 8BEC MOV bp, sp 001 000AD2 8BEC MOV bp, sp
002 000AD4 83EC10 SUB sp, 10h 002 000AD4 83EC10 SUB sp, 10h
003 000AD7 CD394606 ESC FLD [bp+6] 003 000AD7 CD394606 ESC FLD qword ptr [bp+6]
004 000ADB CD38362701 ESC FDIV [127h] 004 000ADB CD38362701 ESC FDIV qword ptr [127h]
005 000AE0 CD395EF8 ESC FSTP [bp-8] 005 000AE0 CD395EF8 ESC FSTP qword ptr [bp-8]
006 000AE4 CD3D INT 3Dh /* Unknown int */ 006 000AE4 CD3D INT 3Dh /* Unknown int */
007 000AE6 8B460C MOV ax, [bp+0Ch] 007 000AE6 8B460C MOV ax, [bp+0Ch]
@ -413,26 +413,26 @@
014 000AFB 8946F0 MOV [bp-10h], ax 014 000AFB 8946F0 MOV [bp-10h], ax
015 000AFE EB43 JMP L29 015 000AFE EB43 JMP L29
016 000B43 CD39062F01 L29: ESC FLD [12Fh] 016 000B43 CD39062F01 L29: ESC FLD qword ptr [12Fh]
017 000B48 CD384EF8 ESC FMUL [bp-8] 017 000B48 CD384EF8 ESC FMUL qword ptr [bp-8]
018 000B4C CD385EF0 ESC FCOMP [bp-10h] 018 000B4C CD385EF0 ESC FCOMP qword ptr [bp-10h]
019 000B50 CD393E2C06 ESC FSTSW [62Ch] 019 000B50 CD393E2C06 ESC FSTSW qword ptr [62Ch]
020 000B55 CD3D INT 3Dh /* Unknown int */ 020 000B55 CD3D INT 3Dh /* Unknown int */
021 000B57 8A262D06 MOV ah, [62Dh] 021 000B57 8A262D06 MOV ah, [62Dh]
022 000B5B 9E SAHF 022 000B5B 9E SAHF
023 000B5C 72A2 JB L30 023 000B5C 72A2 JB L30
024 000B5E CD3946F8 ESC FLD [bp-8] 024 000B5E CD3946F8 ESC FLD qword ptr [bp-8]
025 000B62 EB00 JMP L31 025 000B62 EB00 JMP L31
026 000B64 8BE5 L31: MOV sp, bp 026 000B64 8BE5 L31: MOV sp, bp
027 000B66 5D POP bp 027 000B66 5D POP bp
028 000B67 CB RETF 028 000B67 CB RETF
029 000B00 CD394606 L30: ESC FLD [bp+6] 029 000B00 CD394606 L30: ESC FLD qword ptr [bp+6]
030 000B04 CD3876F8 ESC FDIV [bp-8] 030 000B04 CD3876F8 ESC FDIV qword ptr [bp-8]
031 000B08 CD3866F8 ESC FSUB [bp-8] 031 000B08 CD3866F8 ESC FSUB qword ptr [bp-8]
032 000B0C CD395EF0 ESC FSTP [bp-10h] 032 000B0C CD395EF0 ESC FSTP qword ptr [bp-10h]
033 000B10 CD3D INT 3Dh /* Unknown int */ 033 000B10 CD3D INT 3Dh /* Unknown int */
034 000B12 FF76F6 PUSH word ptr [bp-0Ah] 034 000B12 FF76F6 PUSH word ptr [bp-0Ah]
@ -441,14 +441,14 @@
037 000B1B FF76F0 PUSH word ptr [bp-10h] 037 000B1B FF76F0 PUSH word ptr [bp-10h]
038 000B1E 9AB8028B00 CALL far ptr proc_8 038 000B1E 9AB8028B00 CALL far ptr proc_8
039 000B23 83C408 ADD sp, 8 039 000B23 83C408 ADD sp, 8
040 000B26 CD395EF0 ESC FSTP [bp-10h] 040 000B26 CD395EF0 ESC FSTP qword ptr [bp-10h]
041 000B2A CD3D INT 3Dh /* Unknown int */ 041 000B2A CD3D INT 3Dh /* Unknown int */
042 000B2C CD394606 ESC FLD [bp+6] 042 000B2C CD394606 ESC FLD qword ptr [bp+6]
043 000B30 CD3876F8 ESC FDIV [bp-8] 043 000B30 CD3876F8 ESC FDIV qword ptr [bp-8]
044 000B34 CD3846F8 ESC FADD [bp-8] 044 000B34 CD3846F8 ESC FADD qword ptr [bp-8]
045 000B38 CD38362701 ESC FDIV [127h] 045 000B38 CD38362701 ESC FDIV qword ptr [127h]
046 000B3D CD395EF8 ESC FSTP [bp-8] 046 000B3D CD395EF8 ESC FSTP qword ptr [bp-8]
047 000B41 CD3D INT 3Dh /* Unknown int */ 047 000B41 CD3D INT 3Dh /* Unknown int */
048 JMP L29 ;Synthetic inst 048 JMP L29 ;Synthetic inst
@ -458,16 +458,16 @@
proc_8 PROC FAR proc_8 PROC FAR
000 000B68 55 PUSH bp 000 000B68 55 PUSH bp
001 000B69 8BEC MOV bp, sp 001 000B69 8BEC MOV bp, sp
002 000B6B CD39062601 ESC FLD [126h] 002 000B6B CD39062601 ESC FLD qword ptr [126h]
003 000B70 CD394606 ESC FLD [bp+6] 003 000B70 CD394606 ESC FLD qword ptr [bp+6]
004 000B74 CD3AD9 ESC FCOMPP 004 000B74 CD3AD9 ESC FCOMPP
005 000B77 CD393E2C06 ESC FSTSW [62Ch] 005 000B77 CD393E2C06 ESC FSTSW qword ptr [62Ch]
006 000B7C CD3D INT 3Dh /* Unknown int */ 006 000B7C CD3D INT 3Dh /* Unknown int */
007 000B7E 8A262D06 MOV ah, [62Dh] 007 000B7E 8A262D06 MOV ah, [62Dh]
008 000B82 9E SAHF 008 000B82 9E SAHF
009 000B83 7309 JAE L32 009 000B83 7309 JAE L32
010 000B85 CD394606 ESC FLD [bp+6] 010 000B85 CD394606 ESC FLD qword ptr [bp+6]
011 000B89 CD35E0 ESC FCHS 011 000B89 CD35E0 ESC FCHS
012 000B8C EB04 JMP L33 012 000B8C EB04 JMP L33
@ -476,7 +476,7 @@
014 000B94 5D L34: POP bp 014 000B94 5D L34: POP bp
015 000B95 CB RETF 015 000B95 CB RETF
016 000B8E CD394606 L32: ESC FLD [bp+6] 016 000B8E CD394606 L32: ESC FLD qword ptr [bp+6]
017 JMP L33 ;Synthetic inst 017 JMP L33 ;Synthetic inst
proc_8 ENDP proc_8 ENDP
@ -495,49 +495,49 @@
009 000C30 7403 JE L36 009 000C30 7403 JE L36
010 000C32 E96EFF JMP L37 010 000C32 E96EFF JMP L37
011 000BA3 CD394606 L37: ESC FLD [bp+6] 011 000BA3 CD394606 L37: ESC FLD qword ptr [bp+6]
012 000BA7 CD384E06 ESC FMUL [bp+6] 012 000BA7 CD384E06 ESC FMUL qword ptr [bp+6]
013 000BAB CD384E06 ESC FMUL [bp+6] 013 000BAB CD384E06 ESC FMUL qword ptr [bp+6]
014 000BAF CD384E06 ESC FMUL [bp+6] 014 000BAF CD384E06 ESC FMUL qword ptr [bp+6]
015 000BB3 CD384E06 ESC FMUL [bp+6] 015 000BB3 CD384E06 ESC FMUL qword ptr [bp+6]
016 000BB7 CD384E06 ESC FMUL [bp+6] 016 000BB7 CD384E06 ESC FMUL qword ptr [bp+6]
017 000BBB CD384E06 ESC FMUL [bp+6] 017 000BBB CD384E06 ESC FMUL qword ptr [bp+6]
018 000BBF CD395EF8 ESC FSTP [bp-8] 018 000BBF CD395EF8 ESC FSTP qword ptr [bp-8]
019 000BC3 CD3D INT 3Dh /* Unknown int */ 019 000BC3 CD3D INT 3Dh /* Unknown int */
020 000BC5 CD3946F8 ESC FLD [bp-8] 020 000BC5 CD3946F8 ESC FLD qword ptr [bp-8]
021 000BC9 CD387606 ESC FDIV [bp+6] 021 000BC9 CD387606 ESC FDIV qword ptr [bp+6]
022 000BCD CD387606 ESC FDIV [bp+6] 022 000BCD CD387606 ESC FDIV qword ptr [bp+6]
023 000BD1 CD387606 ESC FDIV [bp+6] 023 000BD1 CD387606 ESC FDIV qword ptr [bp+6]
024 000BD5 CD387606 ESC FDIV [bp+6] 024 000BD5 CD387606 ESC FDIV qword ptr [bp+6]
025 000BD9 CD387606 ESC FDIV [bp+6] 025 000BD9 CD387606 ESC FDIV qword ptr [bp+6]
026 000BDD CD387606 ESC FDIV [bp+6] 026 000BDD CD387606 ESC FDIV qword ptr [bp+6]
027 000BE1 CD395EF8 ESC FSTP [bp-8] 027 000BE1 CD395EF8 ESC FSTP qword ptr [bp-8]
028 000BE5 CD3D INT 3Dh /* Unknown int */ 028 000BE5 CD3D INT 3Dh /* Unknown int */
029 000BE7 CD3946F8 ESC FLD [bp-8] 029 000BE7 CD3946F8 ESC FLD qword ptr [bp-8]
030 000BEB CD384606 ESC FADD [bp+6] 030 000BEB CD384606 ESC FADD qword ptr [bp+6]
031 000BEF CD384606 ESC FADD [bp+6] 031 000BEF CD384606 ESC FADD qword ptr [bp+6]
032 000BF3 CD384606 ESC FADD [bp+6] 032 000BF3 CD384606 ESC FADD qword ptr [bp+6]
033 000BF7 CD384606 ESC FADD [bp+6] 033 000BF7 CD384606 ESC FADD qword ptr [bp+6]
034 000BFB CD384606 ESC FADD [bp+6] 034 000BFB CD384606 ESC FADD qword ptr [bp+6]
035 000BFF CD384606 ESC FADD [bp+6] 035 000BFF CD384606 ESC FADD qword ptr [bp+6]
036 000C03 CD395EF8 ESC FSTP [bp-8] 036 000C03 CD395EF8 ESC FSTP qword ptr [bp-8]
037 000C07 CD3D INT 3Dh /* Unknown int */ 037 000C07 CD3D INT 3Dh /* Unknown int */
038 000C09 CD3946F8 ESC FLD [bp-8] 038 000C09 CD3946F8 ESC FLD qword ptr [bp-8]
039 000C0D CD386606 ESC FSUB [bp+6] 039 000C0D CD386606 ESC FSUB qword ptr [bp+6]
040 000C11 CD386606 ESC FSUB [bp+6] 040 000C11 CD386606 ESC FSUB qword ptr [bp+6]
041 000C15 CD386606 ESC FSUB [bp+6] 041 000C15 CD386606 ESC FSUB qword ptr [bp+6]
042 000C19 CD386606 ESC FSUB [bp+6] 042 000C19 CD386606 ESC FSUB qword ptr [bp+6]
043 000C1D CD386606 ESC FSUB [bp+6] 043 000C1D CD386606 ESC FSUB qword ptr [bp+6]
044 000C21 CD386606 ESC FSUB [bp+6] 044 000C21 CD386606 ESC FSUB qword ptr [bp+6]
045 000C25 CD395EF8 ESC FSTP [bp-8] 045 000C25 CD395EF8 ESC FSTP qword ptr [bp-8]
046 000C29 CD3D INT 3Dh /* Unknown int */ 046 000C29 CD3D INT 3Dh /* Unknown int */
047 JMP L35 ;Synthetic inst 047 JMP L35 ;Synthetic inst
048 000C35 CD3946F8 L36: ESC FLD [bp-8] 048 000C35 CD3946F8 L36: ESC FLD qword ptr [bp-8]
049 000C39 EB00 JMP L38 049 000C39 EB00 JMP L38
050 000C3B 5E L38: POP si 050 000C3B 5E L38: POP si

120
tests/prev_base/DHAMP.EXE.a2
View File

@ -94,49 +94,49 @@
008 000C2E 0BC0 OR ax, ax 008 000C2E 0BC0 OR ax, ax
009 000C30 7403 JE L9 009 000C30 7403 JE L9
011 000BA3 CD394606 L10: ESC FLD [bp+6] 011 000BA3 CD394606 L10: ESC FLD qword ptr [bp+6]
012 000BA7 CD384E06 ESC FMUL [bp+6] 012 000BA7 CD384E06 ESC FMUL qword ptr [bp+6]
013 000BAB CD384E06 ESC FMUL [bp+6] 013 000BAB CD384E06 ESC FMUL qword ptr [bp+6]
014 000BAF CD384E06 ESC FMUL [bp+6] 014 000BAF CD384E06 ESC FMUL qword ptr [bp+6]
015 000BB3 CD384E06 ESC FMUL [bp+6] 015 000BB3 CD384E06 ESC FMUL qword ptr [bp+6]
016 000BB7 CD384E06 ESC FMUL [bp+6] 016 000BB7 CD384E06 ESC FMUL qword ptr [bp+6]
017 000BBB CD384E06 ESC FMUL [bp+6] 017 000BBB CD384E06 ESC FMUL qword ptr [bp+6]
018 000BBF CD395EF8 ESC FSTP [bp-8] 018 000BBF CD395EF8 ESC FSTP qword ptr [bp-8]
019 000BC3 CD3D INT 3Dh /* Unknown int */ 019 000BC3 CD3D INT 3Dh /* Unknown int */
020 000BC5 CD3946F8 ESC FLD [bp-8] 020 000BC5 CD3946F8 ESC FLD qword ptr [bp-8]
021 000BC9 CD387606 ESC FDIV [bp+6] 021 000BC9 CD387606 ESC FDIV qword ptr [bp+6]
022 000BCD CD387606 ESC FDIV [bp+6] 022 000BCD CD387606 ESC FDIV qword ptr [bp+6]
023 000BD1 CD387606 ESC FDIV [bp+6] 023 000BD1 CD387606 ESC FDIV qword ptr [bp+6]
024 000BD5 CD387606 ESC FDIV [bp+6] 024 000BD5 CD387606 ESC FDIV qword ptr [bp+6]
025 000BD9 CD387606 ESC FDIV [bp+6] 025 000BD9 CD387606 ESC FDIV qword ptr [bp+6]
026 000BDD CD387606 ESC FDIV [bp+6] 026 000BDD CD387606 ESC FDIV qword ptr [bp+6]
027 000BE1 CD395EF8 ESC FSTP [bp-8] 027 000BE1 CD395EF8 ESC FSTP qword ptr [bp-8]
028 000BE5 CD3D INT 3Dh /* Unknown int */ 028 000BE5 CD3D INT 3Dh /* Unknown int */
029 000BE7 CD3946F8 ESC FLD [bp-8] 029 000BE7 CD3946F8 ESC FLD qword ptr [bp-8]
030 000BEB CD384606 ESC FADD [bp+6] 030 000BEB CD384606 ESC FADD qword ptr [bp+6]
031 000BEF CD384606 ESC FADD [bp+6] 031 000BEF CD384606 ESC FADD qword ptr [bp+6]
032 000BF3 CD384606 ESC FADD [bp+6] 032 000BF3 CD384606 ESC FADD qword ptr [bp+6]
033 000BF7 CD384606 ESC FADD [bp+6] 033 000BF7 CD384606 ESC FADD qword ptr [bp+6]
034 000BFB CD384606 ESC FADD [bp+6] 034 000BFB CD384606 ESC FADD qword ptr [bp+6]
035 000BFF CD384606 ESC FADD [bp+6] 035 000BFF CD384606 ESC FADD qword ptr [bp+6]
036 000C03 CD395EF8 ESC FSTP [bp-8] 036 000C03 CD395EF8 ESC FSTP qword ptr [bp-8]
037 000C07 CD3D INT 3Dh /* Unknown int */ 037 000C07 CD3D INT 3Dh /* Unknown int */
038 000C09 CD3946F8 ESC FLD [bp-8] 038 000C09 CD3946F8 ESC FLD qword ptr [bp-8]
039 000C0D CD386606 ESC FSUB [bp+6] 039 000C0D CD386606 ESC FSUB qword ptr [bp+6]
040 000C11 CD386606 ESC FSUB [bp+6] 040 000C11 CD386606 ESC FSUB qword ptr [bp+6]
041 000C15 CD386606 ESC FSUB [bp+6] 041 000C15 CD386606 ESC FSUB qword ptr [bp+6]
042 000C19 CD386606 ESC FSUB [bp+6] 042 000C19 CD386606 ESC FSUB qword ptr [bp+6]
043 000C1D CD386606 ESC FSUB [bp+6] 043 000C1D CD386606 ESC FSUB qword ptr [bp+6]
044 000C21 CD386606 ESC FSUB [bp+6] 044 000C21 CD386606 ESC FSUB qword ptr [bp+6]
045 000C25 CD395EF8 ESC FSTP [bp-8] 045 000C25 CD395EF8 ESC FSTP qword ptr [bp-8]
046 000C29 CD3D INT 3Dh /* Unknown int */ 046 000C29 CD3D INT 3Dh /* Unknown int */
047 JMP L8 ;Synthetic inst 047 JMP L8 ;Synthetic inst
048 000C35 CD3946F8 L9: ESC FLD [bp-8] 048 000C35 CD3946F8 L9: ESC FLD qword ptr [bp-8]
050 000C3B 5E POP si 050 000C3B 5E POP si
051 000C3C 8BE5 MOV sp, bp 051 000C3C 8BE5 MOV sp, bp
052 000C3E 5D POP bp 052 000C3E 5D POP bp
@ -147,22 +147,22 @@
proc_8 PROC FAR proc_8 PROC FAR
000 000B68 55 PUSH bp 000 000B68 55 PUSH bp
001 000B69 8BEC MOV bp, sp 001 000B69 8BEC MOV bp, sp
002 000B6B CD39062601 ESC FLD [126h] 002 000B6B CD39062601 ESC FLD qword ptr [126h]
003 000B70 CD394606 ESC FLD [bp+6] 003 000B70 CD394606 ESC FLD qword ptr [bp+6]
004 000B74 CD3AD9 ESC FCOMPP 004 000B74 CD3AD9 ESC FCOMPP
005 000B77 CD393E2C06 ESC FSTSW [62Ch] 005 000B77 CD393E2C06 ESC FSTSW qword ptr [62Ch]
006 000B7C CD3D INT 3Dh /* Unknown int */ 006 000B7C CD3D INT 3Dh /* Unknown int */
007 000B7E 8A262D06 MOV ah, [62Dh] 007 000B7E 8A262D06 MOV ah, [62Dh]
008 000B82 9E SAHF 008 000B82 9E SAHF
009 000B83 7309 JAE L11 009 000B83 7309 JAE L11
010 000B85 CD394606 ESC FLD [bp+6] 010 000B85 CD394606 ESC FLD qword ptr [bp+6]
011 000B89 CD35E0 ESC FCHS 011 000B89 CD35E0 ESC FCHS
014 000B94 5D L12: POP bp 014 000B94 5D L12: POP bp
015 000B95 CB RETF 015 000B95 CB RETF
016 000B8E CD394606 L11: ESC FLD [bp+6] 016 000B8E CD394606 L11: ESC FLD qword ptr [bp+6]
017 JMP L12 ;Synthetic inst 017 JMP L12 ;Synthetic inst
proc_8 ENDP proc_8 ENDP
@ -171,9 +171,9 @@
000 000AD1 55 PUSH bp 000 000AD1 55 PUSH bp
001 000AD2 8BEC MOV bp, sp 001 000AD2 8BEC MOV bp, sp
002 000AD4 83EC10 SUB sp, 10h 002 000AD4 83EC10 SUB sp, 10h
003 000AD7 CD394606 ESC FLD [bp+6] 003 000AD7 CD394606 ESC FLD qword ptr [bp+6]
004 000ADB CD38362701 ESC FDIV [127h] 004 000ADB CD38362701 ESC FDIV qword ptr [127h]
005 000AE0 CD395EF8 ESC FSTP [bp-8] 005 000AE0 CD395EF8 ESC FSTP qword ptr [bp-8]
006 000AE4 CD3D INT 3Dh /* Unknown int */ 006 000AE4 CD3D INT 3Dh /* Unknown int */
007 000AE6 8B460C MOV ax, [bp+0Ch] 007 000AE6 8B460C MOV ax, [bp+0Ch]
@ -185,24 +185,24 @@
013 000AF8 8B4606 MOV ax, [bp+6] 013 000AF8 8B4606 MOV ax, [bp+6]
014 000AFB 8946F0 MOV [bp-10h], ax 014 000AFB 8946F0 MOV [bp-10h], ax
016 000B43 CD39062F01 L13: ESC FLD [12Fh] 016 000B43 CD39062F01 L13: ESC FLD qword ptr [12Fh]
017 000B48 CD384EF8 ESC FMUL [bp-8] 017 000B48 CD384EF8 ESC FMUL qword ptr [bp-8]
018 000B4C CD385EF0 ESC FCOMP [bp-10h] 018 000B4C CD385EF0 ESC FCOMP qword ptr [bp-10h]
019 000B50 CD393E2C06 ESC FSTSW [62Ch] 019 000B50 CD393E2C06 ESC FSTSW qword ptr [62Ch]
020 000B55 CD3D INT 3Dh /* Unknown int */ 020 000B55 CD3D INT 3Dh /* Unknown int */
021 000B57 8A262D06 MOV ah, [62Dh] 021 000B57 8A262D06 MOV ah, [62Dh]
022 000B5B 9E SAHF 022 000B5B 9E SAHF
023 000B5C 72A2 JB L14 023 000B5C 72A2 JB L14
024 000B5E CD3946F8 ESC FLD [bp-8] 024 000B5E CD3946F8 ESC FLD qword ptr [bp-8]
026 000B64 8BE5 MOV sp, bp 026 000B64 8BE5 MOV sp, bp
027 000B66 5D POP bp 027 000B66 5D POP bp
028 000B67 CB RETF 028 000B67 CB RETF
029 000B00 CD394606 L14: ESC FLD [bp+6] 029 000B00 CD394606 L14: ESC FLD qword ptr [bp+6]
030 000B04 CD3876F8 ESC FDIV [bp-8] 030 000B04 CD3876F8 ESC FDIV qword ptr [bp-8]
031 000B08 CD3866F8 ESC FSUB [bp-8] 031 000B08 CD3866F8 ESC FSUB qword ptr [bp-8]
032 000B0C CD395EF0 ESC FSTP [bp-10h] 032 000B0C CD395EF0 ESC FSTP qword ptr [bp-10h]
033 000B10 CD3D INT 3Dh /* Unknown int */ 033 000B10 CD3D INT 3Dh /* Unknown int */
034 000B12 FF76F6 PUSH word ptr [bp-0Ah] 034 000B12 FF76F6 PUSH word ptr [bp-0Ah]
@ -211,14 +211,14 @@
037 000B1B FF76F0 PUSH word ptr [bp-10h] 037 000B1B FF76F0 PUSH word ptr [bp-10h]
038 000B1E 9AB8028B00 CALL far ptr proc_8 038 000B1E 9AB8028B00 CALL far ptr proc_8
039 000B23 83C408 ADD sp, 8 039 000B23 83C408 ADD sp, 8
040 000B26 CD395EF0 ESC FSTP [bp-10h] 040 000B26 CD395EF0 ESC FSTP qword ptr [bp-10h]
041 000B2A CD3D INT 3Dh /* Unknown int */ 041 000B2A CD3D INT 3Dh /* Unknown int */
042 000B2C CD394606 ESC FLD [bp+6] 042 000B2C CD394606 ESC FLD qword ptr [bp+6]
043 000B30 CD3876F8 ESC FDIV [bp-8] 043 000B30 CD3876F8 ESC FDIV qword ptr [bp-8]
044 000B34 CD3846F8 ESC FADD [bp-8] 044 000B34 CD3846F8 ESC FADD qword ptr [bp-8]
045 000B38 CD38362701 ESC FDIV [127h] 045 000B38 CD38362701 ESC FDIV qword ptr [127h]
046 000B3D CD395EF8 ESC FSTP [bp-8] 046 000B3D CD395EF8 ESC FSTP qword ptr [bp-8]
047 000B41 CD3D INT 3Dh /* Unknown int */ 047 000B41 CD3D INT 3Dh /* Unknown int */
048 JMP L13 ;Synthetic inst 048 JMP L13 ;Synthetic inst
@ -533,17 +533,17 @@
095 0009BA A12006 MOV ax, [620h] 095 0009BA A12006 MOV ax, [620h]
096 0009BD 52 PUSH dx 096 0009BD 52 PUSH dx
097 0009BE 50 PUSH ax 097 0009BE 50 PUSH ax
098 0009BF CD378626FF ESC FILD [bp-0DAh] 098 0009BF CD378626FF ESC FILD dword ptr [bp-0DAh]
099 0009C4 CD3D INT 3Dh /* Unknown int */ 099 0009C4 CD3D INT 3Dh /* Unknown int */
100 0009C6 83C404 ADD sp, 4 100 0009C6 83C404 ADD sp, 4
101 0009C9 83EC08 SUB sp, 8 101 0009C9 83EC08 SUB sp, 8
102 0009CC CD399E22FF ESC FSTP [bp-0DEh] 102 0009CC CD399E22FF ESC FSTP qword ptr [bp-0DEh]
103 0009D1 CD3D INT 3Dh /* Unknown int */ 103 0009D1 CD3D INT 3Dh /* Unknown int */
104 0009D3 9A21028B00 CALL far ptr proc_7 104 0009D3 9A21028B00 CALL far ptr proc_7
105 0009D8 83C408 ADD sp, 8 105 0009D8 83C408 ADD sp, 8
106 0009DB CD391E2406 ESC FSTP [624h] 106 0009DB CD391E2406 ESC FSTP qword ptr [624h]
107 0009E0 CD3D INT 3Dh /* Unknown int */ 107 0009E0 CD3D INT 3Dh /* Unknown int */
108 0009E2 FF362A06 PUSH word ptr [62Ah] 108 0009E2 FF362A06 PUSH word ptr [62Ah]
@ -561,7 +561,7 @@
120 000A0B FF362406 PUSH word ptr [624h] 120 000A0B FF362406 PUSH word ptr [624h]
121 000A0F 9AE6028B00 CALL far ptr proc_9 121 000A0F 9AE6028B00 CALL far ptr proc_9
122 000A14 83C408 ADD sp, 8 122 000A14 83C408 ADD sp, 8
123 000A17 CD395EF8 ESC FSTP [bp-8] 123 000A17 CD395EF8 ESC FSTP qword ptr [bp-8]
124 000A1B CD3D INT 3Dh /* Unknown int */ 124 000A1B CD3D INT 3Dh /* Unknown int */
125 000A1D FF76FE PUSH word ptr [bp-2] 125 000A1D FF76FE PUSH word ptr [bp-2]

46
tests/prev_base/DHAMP.b
View File

@ -159,22 +159,22 @@ void proc_8 (int arg0)
{ {
PUSH bp PUSH bp
MOV bp, sp MOV bp, sp
ESC FLD [126h] ESC FLD qword ptr [126h]
ESC FLD [bp+6] ESC FLD qword ptr [bp+6]
ESC FCOMPP ESC FCOMPP
ESC FSTSW [62Ch] ESC FSTSW qword ptr [62Ch]
INT 3Dh /* Unknown int */ INT 3Dh /* Unknown int */
MOV ah, [62Dh] MOV ah, [62Dh]
SAHF SAHF
JAE L1 JAE L1
ESC FLD [bp+6] ESC FLD qword ptr [bp+6]
ESC FCHS ESC FCHS
L2: POP bp L2: POP bp
RETF RETF
L1: ESC FLD [bp+6] L1: ESC FLD qword ptr [bp+6]
JMP L2 ;Synthetic inst JMP L2 ;Synthetic inst
} }
@ -191,9 +191,9 @@ void proc_8 (int arg0)
PUSH bp PUSH bp
MOV bp, sp MOV bp, sp
SUB sp, 10h SUB sp, 10h
ESC FLD [bp+6] ESC FLD qword ptr [bp+6]
ESC FDIV [127h] ESC FDIV qword ptr [127h]
ESC FSTP [bp-8] ESC FSTP qword ptr [bp-8]
INT 3Dh /* Unknown int */ INT 3Dh /* Unknown int */
MOV ax, [bp+0Ch] MOV ax, [bp+0Ch]
@ -205,24 +205,24 @@ void proc_8 (int arg0)
MOV ax, [bp+6] MOV ax, [bp+6]
MOV [bp-10h], ax MOV [bp-10h], ax
L1: ESC FLD [12Fh] L1: ESC FLD qword ptr [12Fh]
ESC FMUL [bp-8] ESC FMUL qword ptr [bp-8]
ESC FCOMP [bp-10h] ESC FCOMP qword ptr [bp-10h]
ESC FSTSW [62Ch] ESC FSTSW qword ptr [62Ch]
INT 3Dh /* Unknown int */ INT 3Dh /* Unknown int */
MOV ah, [62Dh] MOV ah, [62Dh]
SAHF SAHF
JB L2 JB L2
ESC FLD [bp-8] ESC FLD qword ptr [bp-8]
MOV sp, bp MOV sp, bp
POP bp POP bp
RETF RETF
L2: ESC FLD [bp+6] L2: ESC FLD qword ptr [bp+6]
ESC FDIV [bp-8] ESC FDIV qword ptr [bp-8]
ESC FSUB [bp-8] ESC FSUB qword ptr [bp-8]
ESC FSTP [bp-10h] ESC FSTP qword ptr [bp-10h]
INT 3Dh /* Unknown int */ INT 3Dh /* Unknown int */
PUSH word ptr [bp-0Ah] PUSH word ptr [bp-0Ah]
@ -231,14 +231,14 @@ void proc_8 (int arg0)
PUSH word ptr [bp-10h] PUSH word ptr [bp-10h]
CALL far ptr proc_8 CALL far ptr proc_8
ADD sp, 8 ADD sp, 8
ESC FSTP [bp-10h] ESC FSTP qword ptr [bp-10h]
INT 3Dh /* Unknown int */ INT 3Dh /* Unknown int */
ESC FLD [bp+6] ESC FLD qword ptr [bp+6]
ESC FDIV [bp-8] ESC FDIV qword ptr [bp-8]
ESC FADD [bp-8] ESC FADD qword ptr [bp-8]
ESC FDIV [127h] ESC FDIV qword ptr [127h]
ESC FSTP [bp-8] ESC FSTP qword ptr [bp-8]
INT 3Dh /* Unknown int */ INT 3Dh /* Unknown int */
JMP L1 ;Synthetic inst JMP L1 ;Synthetic inst

11
valgrind_tester
View File

@ -7,16 +7,19 @@ def path_local(from)
from.gsub('/','\\\\') from.gsub('/','\\\\')
end end
TESTS_DIR="./tests" TESTS_DIR="./tests"
def perform_test(exepath,filepath,outname) def perform_test(exepath,filepath,outname,args)
output_path=path_local(TESTS_DIR+"/outputs/"+outname) output_path=path_local(TESTS_DIR+"/outputs/"+outname)
error_path=path_local(TESTS_DIR+"/errors/"+outname) error_path=path_local(TESTS_DIR+"/errors/"+outname)
exepath=path_local(exepath) exepath=path_local(exepath)
output_path=path_local(output_path) output_path=path_local(output_path)
filepath=path_local(filepath) filepath=path_local(filepath)
printf("calling:" + "#{exepath} -a1 -o#{output_path}.a1 #{filepath}\n") joined_args = args.join(' ')
printf("calling:" + "#{exepath} #{joined_args} -o#{output_path}.a1 #{filepath}\n")
valgrind_mode="valgrind --track-origins=yes " valgrind_mode="valgrind --track-origins=yes "
#valgrind --tool=callgrind --dump-instr=yes --collect-jumps=yes #valgrind --tool=callgrind --dump-instr=yes --collect-jumps=yes
result = `#{valgrind_mode} #{exepath} -a2V -o#{output_path}.a2 #{filepath} 2>#{error_path}.val` result = `#{valgrind_mode} #{exepath} #{joined_args} -a1 -o#{output_path}.b #{filepath} 2>#{error_path}.val`
result = `#{valgrind_mode} #{exepath} #{joined_args} -a2 -o#{output_path}.b #{filepath} 2>>#{error_path}.val`
result = `#{valgrind_mode} #{exepath} #{joined_args} -o#{output_path}.b #{filepath} 2>>#{error_path}.val`
puts result puts result
p $? p $?
end end
@ -28,7 +31,7 @@ if(ARGV.size()==0)
end end
Dir.open(TESTS_DIR+"/inputs").each() {|f| Dir.open(TESTS_DIR+"/inputs").each() {|f|
next if f=="." or f==".." next if f=="." or f==".."
perform_test(".//"+ARGV[0],TESTS_DIR+"/inputs/"+f,f) perform_test(".//"+ARGV[0],TESTS_DIR+"/inputs/"+f,f,ARGV[1..-1])
} }
Dir.open(TESTS_DIR+"/inputs").each() {|f| Dir.open(TESTS_DIR+"/inputs").each() {|f|
next if f=="." or f==".." next if f=="." or f==".."