37 lines
657 B
Verilog
37 lines
657 B
Verilog
module ram8_8(
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input [7:0] dia,
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output [7:0] doa,
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input wea,
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input ena,
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input clka,
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input [10:0] addra,
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input [7:0] dib,
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output [7:0] dob,
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input web,
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input enb,
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input clkb,
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input [10:0] addrb
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);
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genvar i;
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generate
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for (i = 0; i < 4; i=i+1) begin : ramx
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RAMB16_S2_S2 ramx(
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.DIA(dia[2 * i + 1: 2 * i]),
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.WEA(wea),
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.ENA(ena),
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.CLKA(clka),
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.ADDRA(addra),
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.DOA(doa[2 * i + 1: 2 * i]),
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.DIB(dib[2 * i + 1: 2 * i]),
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.WEB(web),
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.ENB(enb),
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.CLKB(clkb),
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.ADDRB(addrb),
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.DOB(dob[2 * i + 1: 2 * i])
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);
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end
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endgenerate
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endmodule
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