gameduino/fpga/testtop.v
2013-10-28 13:19:25 +00:00

21 lines
336 B
Verilog

module top(
input SCK, // arduino 13
input MOSI, // arduino 11
inout MISO, // arduino 12
input SSEL, // arduino 9
output flashMOSI,
input flashMISO,
output flashSCK,
output flashSSEL
);
assign flashMOSI = MOSI;
assign MISO = flashMISO;
assign flashSCK = SCK;
assign flashSSEL = SSEL;
endmodule // top