188 lines
4.3 KiB
Verilog
188 lines
4.3 KiB
Verilog
module j1(
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input sys_clk_i, input sys_rst_i, input [15:0] io_din,
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output io_rd, output io_wr, output [15:0] io_addr, output [15:0] io_dout);
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wire [15:0] insn;
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wire [15:0] immediate = { 1'b0, insn[14:0] };
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wire [15:0] ramrd;
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reg [4:0] dsp; // Data stack pointer
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reg [4:0] _dsp;
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reg [15:0] st0; // Return stack pointer
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reg [15:0] _st0;
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wire _dstkW; // D stack write
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reg [12:0] pc;
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reg [12:0] _pc;
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reg [4:0] rsp;
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reg [4:0] _rsp;
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reg _rstkW; // R stack write
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reg [15:0] _rstkD;
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wire _ramWE; // RAM write enable
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wire [15:0] pc_plus_1;
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assign pc_plus_1 = pc + 1;
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// The D and R stacks
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reg [15:0] dstack[0:31];
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reg [15:0] rstack[0:31];
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always @(posedge sys_clk_i)
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begin
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if (_dstkW)
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dstack[_dsp] = st0;
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if (_rstkW)
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rstack[_rsp] = _rstkD;
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end
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wire [15:0] st1 = dstack[dsp];
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wire [15:0] rst0 = rstack[rsp];
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// st0sel is the ALU operation. For branch and call the operation
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// is T, for 0branch it is N. For ALU ops it is loaded from the instruction
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// field.
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reg [3:0] st0sel;
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always @*
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begin
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case (insn[14:13])
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2'b00: st0sel = 0; // ubranch
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2'b10: st0sel = 0; // call
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2'b01: st0sel = 1; // 0branch
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2'b11: st0sel = insn[11:8]; // ALU
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default: st0sel = 4'bxxxx;
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endcase
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end
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`define RAMS 3
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genvar i;
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`define w (16 >> `RAMS)
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`define w1 (`w - 1)
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generate
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for (i = 0; i < (1 << `RAMS); i=i+1) begin : ram
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// RAMB16_S18_S18
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RAMB16_S2_S2
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ram(
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.DIA(0),
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// .DIPA(0),
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.DOA(insn[`w*i+`w1:`w*i]),
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.WEA(0),
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.ENA(1),
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.CLKA(sys_clk_i),
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.ADDRA({_pc}),
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.DIB(st1[`w*i+`w1:`w*i]),
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// .DIPB(2'b0),
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.WEB(_ramWE & (_st0[15:14] == 0)),
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.ENB(|_st0[15:14] == 0),
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.CLKB(sys_clk_i),
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.ADDRB(_st0[15:1]),
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.DOB(ramrd[`w*i+`w1:`w*i]));
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end
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endgenerate
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// Compute the new value of T.
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always @*
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begin
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if (insn[15])
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_st0 = immediate;
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else
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case (st0sel)
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4'b0000: _st0 = st0;
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4'b0001: _st0 = st1;
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4'b0010: _st0 = st0 + st1;
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4'b0011: _st0 = st0 & st1;
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4'b0100: _st0 = st0 | st1;
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4'b0101: _st0 = st0 ^ st1;
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4'b0110: _st0 = ~st0;
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4'b0111: _st0 = {16{(st1 == st0)}};
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4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}};
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4'b1001: _st0 = st1 >> st0[3:0];
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4'b1010: _st0 = st0 - 1;
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4'b1011: _st0 = rst0;
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4'b1100: _st0 = |st0[15:14] ? io_din : ramrd;
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4'b1101: _st0 = st1 << st0[3:0];
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4'b1110: _st0 = {rsp, 3'b000, dsp};
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4'b1111: _st0 = {16{(st1 < st0)}};
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default: _st0 = 16'hxxxx;
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endcase
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end
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wire is_alu = (insn[15:13] == 3'b011);
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wire is_lit = (insn[15]);
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assign io_rd = (is_alu & (insn[11:8] == 4'hc));
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assign io_wr = _ramWE;
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assign io_addr = st0;
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assign io_dout = st1;
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assign _ramWE = is_alu & insn[5];
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assign _dstkW = is_lit | (is_alu & insn[7]);
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wire [1:0] dd = insn[1:0]; // D stack delta
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wire [1:0] rd = insn[3:2]; // R stack delta
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always @*
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begin
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if (is_lit) begin // literal
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_dsp = dsp + 1;
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_rsp = rsp;
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_rstkW = 0;
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_rstkD = _pc;
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end else if (is_alu) begin
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_dsp = dsp + {dd[1], dd[1], dd[1], dd};
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_rsp = rsp + {rd[1], rd[1], rd[1], rd};
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_rstkW = insn[6];
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_rstkD = st0;
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end else begin // jump/call
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// predicated jump is like DROP
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if (insn[15:13] == 3'b001) begin
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_dsp = dsp - 1;
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end else begin
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_dsp = dsp;
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end
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if (insn[15:13] == 3'b010) begin // call
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_rsp = rsp + 1;
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_rstkW = 1;
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_rstkD = {pc_plus_1[14:0], 1'b0};
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end else begin
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_rsp = rsp;
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_rstkW = 0;
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_rstkD = _pc;
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end
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end
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end
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always @*
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begin
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if (sys_rst_i)
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_pc = pc;
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else
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if ((insn[15:13] == 3'b000) |
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((insn[15:13] == 3'b001) & (|st0 == 0)) |
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(insn[15:13] == 3'b010))
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_pc = insn[12:0];
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else if (is_alu & insn[12])
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_pc = rst0[15:1];
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else
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_pc = pc_plus_1;
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end
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always @(posedge sys_clk_i)
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begin
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if (sys_rst_i) begin
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pc <= 0;
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dsp <= 0;
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st0 <= 0;
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rsp <= 0;
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end else begin
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dsp <= _dsp;
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pc <= _pc;
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st0 <= _st0;
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rsp <= _rsp;
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end
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end
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endmodule // j1
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