41 lines
1.1 KiB
Verilog
41 lines
1.1 KiB
Verilog
module ck_div(
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input ck_in,
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output ck_out,
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input sys_rst_i
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//output locked;
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);
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parameter DIV_BY = 1;
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parameter MULT_BY = 1;
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wire ck_fb;
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//DCM #(
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// .CLKDV_DIVIDE(DIV_BY),
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// .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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// .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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// .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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//) DCM_inst (
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// .CLK0(ck_fb),
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// .CLKDV(ck_out),
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// .CLKFB(ck_fb), // DCM clock feedback
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// .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
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// .RST(0)
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//);
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DCM #(
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.CLKFX_MULTIPLY(MULT_BY),
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.CLKFX_DIVIDE(DIV_BY),
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.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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) DCM_inst (
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.CLK0(ck_fb),
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.CLKFX(ck_out),
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.CLKFB(ck_fb), // DCM clock feedback
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.CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
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.RST(0)
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);
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//BUFG BUFG_inst(.I(ck_int), .O(ck_out));
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endmodule |