34 lines
635 B
Verilog
34 lines
635 B
Verilog
module fifo ( clk, datain, wr, dataout, rd, fullness);
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parameter WIDTH = 1;
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input clk;
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input [WIDTH-1:0] datain;
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input wr;
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output [WIDTH-1:0] dataout;
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input rd;
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output reg [4:0] fullness;
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always @(posedge clk)
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begin
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fullness <= (fullness + wr - rd);
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end
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wire [3:0] readaddr = (fullness - 1);
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genvar i;
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generate
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for (i = 0; i < WIDTH; i=i+1) begin : srl16
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SRL16E fifo16(
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.CLK(clk),
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.CE(wr),
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.D(datain[i]),
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.A0(readaddr[0]),
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.A1(readaddr[1]),
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.A2(readaddr[2]),
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.A3(readaddr[3]),
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.Q(dataout[i]));
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end
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endgenerate
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endmodule
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