10 lines
188 B
Makefile
10 lines
188 B
Makefile
project = j1
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vendor = xilinx
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family = spartan3s
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part = xc3s1000-4ft256
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top_module = top
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vfiles = ../verilog/top.v ../verilog/j1.v ../verilog/ck_div.v ../verilog/uart.v
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include xilinx.mk
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