175 lines
5.6 KiB
Makefile
175 lines
5.6 KiB
Makefile
# The top level module should define the variables below then include
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# this file. The files listed should be in the same directory as the
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# Makefile.
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#
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# variable description
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# ---------- -------------
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# project project name (top level module should match this name)
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# top_module top level module of the project
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# libdir path to library directory
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# libs library modules used
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# vfiles all local .v files
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# xilinx_cores all local .xco files
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# vendor vendor of FPGA (xilinx, altera, etc.)
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# family FPGA device family (spartan3e)
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# part FPGA part name (xc4vfx12-10-sf363)
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# flashsize size of flash for mcs file (16384)
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# optfile (optional) xst extra opttions file to put in .scr
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# map_opts (optional) options to give to map
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# par_opts (optional) options to give to par
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# intstyle (optional) intstyle option to all tools
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#
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# files description
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# ---------- ------------
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# $(project).ucf ucf file
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#
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# Library modules should have a modules.mk in their root directory,
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# namely $(libdir)/<libname>/module.mk, that simply adds to the vfiles
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# and xilinx_cores variable.
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#
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# all the .xco files listed in xilinx_cores will be generated with core, with
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# the resulting .v and .ngc files placed back in the same directory as
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# the .xco file.
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#
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# TODO: .xco files are device dependant, should use a template based system
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coregen_work_dir ?= ./coregen-tmp
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map_opts ?= -timing -ol high -detail -pr b -register_duplication -w
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par_opts ?= -ol high
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isedir ?= /opt/Xilinx/11.1/ISE
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xil_env ?= . $(isedir)/settings32.sh
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flashsize ?= 8192
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libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
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mkfiles = Makefile $(libmks) xilinx.mk
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include $(libmks)
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corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc))
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local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc)))
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vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v))
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junk += $(local_corengcs)
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.PHONY: default xilinx_cores clean twr etwr
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default: $(project).bit $(project).mcs
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xilinx_cores: $(corengcs)
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twr: $(project).twr
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etwr: $(project)_err.twr
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define cp_template
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$(2): $(1)
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cp $(1) $(2)
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endef
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$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc)))))
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%.ngc %.v: %.xco
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@echo "=== rebuilding $@"
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if [ -d $(coregen_work_dir) ]; then \
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rm -rf $(coregen_work_dir)/*; \
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else \
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mkdir -p $(coregen_work_dir); \
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fi
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cd $(coregen_work_dir); \
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$(xil_env); \
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coregen -b $$OLDPWD/$<; \
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cd -
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xcodir=`dirname $<`; \
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basename=`basename $< .xco`; \
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if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \
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echo "'$@' wasn't created."; \
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exit 1; \
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else \
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cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \
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fi
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junk += $(coregen_work_dir)
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date = $(shell date +%F-%H-%M)
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# some common junk
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junk += *.xrpt
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programming_files: $(project).bit $(project).mcs
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mkdir -p $@/$(date)
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mkdir -p $@/latest
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for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done
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$(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - $(project).scr > $@/$(date)/$(project).scr
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$(project).mcs: $(project).bit
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$(xil_env); \
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promgen -w -s $(flashsize) -p mcs -o $@ -u 0 $^
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junk += $(project).mcs $(project).cfi $(project).prm
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$(project).bit: $(project)_par.ncd
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$(xil_env); \
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bitgen $(intstyle) -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit
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junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm
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$(project)_par.ncd: $(project).ncd
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$(xil_env); \
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if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \
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:; \
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else \
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$(MAKE) etwr; \
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fi
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junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
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junk += $(project)_par_pad.csv $(project)_par_pad.txt
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junk += $(project)_par.grf $(project)_par.ptwx
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junk += $(project)_par.unroutes $(project)_par.xpi
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$(project).ncd: $(project).ngd
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if [ -r $(project)_par.ncd ]; then \
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cp $(project)_par.ncd smartguide.ncd; \
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smartguide="-smartguide smartguide.ncd"; \
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else \
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smartguide=""; \
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fi; \
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$(xil_env); \
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map $(intstyle) $(map_opts) $$smartguide $<
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junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
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junk += smartguide.ncd $(project).psr
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junk += $(project)_summary.xml $(project)_usage.xml
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$(project).ngd: $(project).ngc $(project).ucf $(project).bmm
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$(xil_env); ngdbuild $(intstyle) $(project).ngc -bm $(project).bmm
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junk += $(project).ngd $(project).bld
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$(project).ngc: $(vfiles) $(local_corengcs) $(project).scr $(project).prj
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$(xil_env); xst $(intstyle) -ifn $(project).scr
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junk += xlnx_auto* $(top_module).lso $(project).srp
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junk += netlist.lst xst $(project).ngc
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$(project).prj: $(vfiles) $(mkfiles)
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for src in $(vfiles); do echo "verilog work $$src" >> $(project).tmpprj; done
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sort -u $(project).tmpprj > $(project).prj
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rm -f $(project).tmpprj
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junk += $(project).prj
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optfile += $(wildcard $(project).opt)
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top_module ?= $(project)
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$(project).scr: $(optfile) $(mkfiles) ./xilinx.opt
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echo "run" > $@
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echo "-p $(part)" >> $@
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echo "-top $(top_module)" >> $@
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echo "-ifn $(project).prj" >> $@
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echo "-ofn $(project).ngc" >> $@
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cat ./xilinx.opt $(optfile) >> $@
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junk += $(project).scr
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$(project).post_map.twr: $(project).ncd
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$(xil_env); trce -e 10 $< $(project).pcf -o $@
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junk += $(project).post_map.twr $(project).post_map.twx smartpreview.twr
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$(project).twr: $(project)_par.ncd
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$(xil_env); trce $< $(project).pcf -o $(project).twr
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junk += $(project).twr $(project).twx smartpreview.twr
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$(project)_err.twr: $(project)_par.ncd
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$(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr
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junk += $(project)_err.twr $(project)_err.twx
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.gitignore: $(mkfiles)
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echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore
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clean::
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rm -rf $(junk)
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