initial commit

This commit is contained in:
Gregory Estrade
2013-11-13 22:47:08 +01:00
commit b27bee02c8
10 changed files with 1176 additions and 0 deletions

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# Auto detect text files and perform LF normalization
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*.dbproj merge=union
# Standard to msysgit
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*.DOC diff=astextplain
*.docx diff=astextplain
*.DOCX diff=astextplain
*.dot diff=astextplain
*.DOT diff=astextplain
*.pdf diff=astextplain
*.PDF diff=astextplain
*.rtf diff=astextplain
*.RTF diff=astextplain

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#################
## Eclipse
#################
*.pydevproject
.project
.metadata
bin/
tmp/
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*.bak
*.swp
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.settings/
.loadpath
# External tool builders
.externalToolBuilders/
# Locally stored "Eclipse launch configurations"
*.launch
# CDT-specific
.cproject
# PDT-specific
.buildpath
#################
## Visual Studio
#################
## Ignore Visual Studio temporary files, build results, and
## files generated by popular Visual Studio add-ons.
# User-specific files
*.suo
*.user
*.sln.docstates
# Build results
[Dd]ebug/
[Rr]elease/
x64/
build/
[Bb]in/
[Oo]bj/
# MSTest test Results
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[Bb]uild[Ll]og.*
*_i.c
*_p.c
*.ilk
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# ReSharper is a .NET coding add-in
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DocProject/Help/*.hhp
DocProject/Help/Html2
DocProject/Help/html
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publish/
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#############
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Thumbs.db
ehthumbs.db
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# Recycle Bin used on file shares
$RECYCLE.BIN/
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.DS_Store
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#############
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build/
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parts/
var/
sdist/
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CM_VGA.brd Normal file

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CM_VGA.sch Normal file

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8
README Normal file
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Guimauve 2ooo - VGA output for Apple //c computers.
Here are the schematics and VHDL code for this adapter.
The board itself is awfully designed.
I'm releasing it for people that were interested in purchasing the board, as I don't plan to assemble new ones.
Feel free to contact me if you have some questions to ask about it.

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[Eagle]
Version="05 04 00"
Platform="Windows"
Serial="62191E841E-LSR-WLM-1EL"
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb_encoder is
port(
CLK14M : in std_logic;
CREF : in std_logic;
nSEROUT : in std_logic;
nSYNC : in std_logic;
TEXT : in std_logic;
GR : in std_logic;
RED : out std_logic_vector(1 downto 0);
GREEN : out std_logic_vector(1 downto 0);
BLUE : out std_logic_vector(1 downto 0);
nSYNCOUT : out std_logic
);
end rgb_encoder;
architecture rtl of rgb_encoder is
signal R : std_logic_vector(1 downto 0) := "00";
signal G : std_logic_vector(1 downto 0) := "00";
signal B : std_logic_vector(1 downto 0) := "00";
signal COLCLK : std_logic_vector(3 downto 0) := "1111";
signal COLPAT : std_logic_vector(3 downto 0) := "1111";
begin
RED <= R;
GREEN <= G;
BLUE <= B;
nSYNCOUT <= nSYNC;
process(CLK14M, nSEROUT, CREF, GR)
variable COLPAT2 : std_logic_vector(3 downto 0);
begin
if falling_edge(CLK14M) then
COLCLK <= COLCLK(2 downto 0) & CREF;
COLPAT <= COLPAT(2 downto 0) & nSEROUT;
if GR = '1' then
if COLCLK = "0011" or COLCLK = "1100" then
if COLCLK = "0011" then
COLPAT2 := COLPAT;
else
COLPAT2 := COLPAT(1 downto 0) & COLPAT(3 downto 2);
end if;
case COLPAT2 is
when "1011" => -- 1 - 0x90 17 40
R <= "10";
G <= "00";
B <= "01";
when "1101" => -- 2 - 0x40 2c a5
R <= "01";
G <= "00";
B <= "10";
when "1001" => -- 3 - 0xd0 43 e5
R <= "11";
G <= "01";
B <= "11";
when "1110" => -- 4 - 0x00 69 40
R <= "00";
G <= "01";
B <= "01";
when "1010" => -- 5 - 0x80 80 80
R <= "10";
G <= "10";
B <= "10";
when "1100" => -- 6 - 0x2f 95 e5
R <= "00";
G <= "10";
B <= "11";
when "1000" => -- 7 - 0xbf ab ff
R <= "11";
G <= "10";
B <= "11";
when "0111" => -- 8 - 0x40 54 00
R <= "01";
G <= "01";
B <= "00";
when "0011" => -- 9 - 0xd0 6a 1a
R <= "11";
G <= "01";
B <= "00";
when "0101" => -- 10 - 0x80 80 80
R <= "01";
G <= "01";
B <= "01";
when "0001" => -- 11 - 0xff 96 bf
R <= "11";
G <= "10";
B <= "11";
when "0110" => -- 12 - 0x2f bc 1a
R <= "00";
G <= "11";
B <= "00";
when "0010" => -- 13 - 0xbf d3 5a
R <= "11";
G <= "11";
B <= "01";
when "0100" => -- 14 - 0x6f e8 bf
R <= "01";
G <= "11";
B <= "11";
when "0000" => -- 15 - 0xff ff ff
R <= "11";
G <= "11";
B <= "11";
when others => -- 0 - 0x00 00 00
R <= "00";
G <= "00";
B <= "00";
end case;
end if;
else
if COLPAT(3) = '1' then
R <= "00";
G <= "00";
B <= "00";
else
R <= "11";
G <= "11";
B <= "11";
end if;
end if;
end if;
end process;
end rtl;

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NET "CLK14M" LOC = "C10" | CLOCK_DEDICATED_ROUTE = FALSE | IOSTANDARD = LVCMOS33;
NET "CREF" LOC = "T3" | IOSTANDARD = LVCMOS33;
NET "nPRAS" LOC = "E10" | IOSTANDARD = LVCMOS33;
NET "nLDPS" LOC = "N11" | IOSTANDARD = LVCMOS33;
NET "VIDD7" LOC = "C11" | IOSTANDARD = LVCMOS33;
NET "nSEROUT" LOC = "P10" | IOSTANDARD = LVCMOS33;
NET "nWNDW" LOC = "D11" | IOSTANDARD = LVCMOS33;
NET "nSYNC" LOC = "R10" | IOSTANDARD = LVCMOS33;
NET "TEXT" LOC = "C12" | IOSTANDARD = LVCMOS33;
NET "SEGB" LOC = "T7" | IOSTANDARD = LVCMOS33;
NET "GR" LOC = "D12" | IOSTANDARD = LVCMOS33;
NET "nSYNCOUT" LOC = "E6" | IOSTANDARD = LVCMOS33;
NET "RED<0>" LOC = "D5" | IOSTANDARD = LVCMOS33;
NET "RED<1>" LOC = "C5" | IOSTANDARD = LVCMOS33;
NET "GREEN<0>" LOC = "D6" | IOSTANDARD = LVCMOS33;
NET "GREEN<1>" LOC = "C6" | IOSTANDARD = LVCMOS33;
NET "BLUE<0>" LOC = "E7" | IOSTANDARD = LVCMOS33;
NET "BLUE<1>" LOC = "C7" | IOSTANDARD = LVCMOS33;
NET "VGA_R" LOC = "R12" | IOSTANDARD = LVCMOS33;
NET "VGA_G" LOC = "T12" | IOSTANDARD = LVCMOS33;
NET "VGA_B" LOC = "R11" | IOSTANDARD = LVCMOS33;
NET "VGA_HS" LOC = "R9" | IOSTANDARD = LVCMOS33;
NET "VGA_VS" LOC = "T10" | IOSTANDARD = LVCMOS33;
#NET "VGA_HS" LOC = "D8" | IOSTANDARD = LVCMOS33;
#NET "VGA_VS" LOC = "C9" | IOSTANDARD = LVCMOS33;

72
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
port(
CLK14M : in std_logic;
CREF : in std_logic;
nPRAS : in std_logic;
nLDPS : in std_logic;
VIDD7 : in std_logic;
nSEROUT : in std_logic;
nWNDW : in std_logic;
nSYNC : in std_logic;
TEXT : in std_logic;
SEGB : in std_logic;
GR : in std_logic;
RED : out std_logic_vector(1 downto 0);
GREEN : out std_logic_vector(1 downto 0);
BLUE : out std_logic_vector(1 downto 0);
nSYNCOUT : out std_logic;
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_R : out std_logic;
VGA_G : out std_logic;
VGA_B : out std_logic
);
end top;
architecture rtl of top is
begin
RGB : entity work.rgb_encoder
port map(
CLK14M => CLK14M,
CREF => CREF,
nSEROUT => nSEROUT,
nSYNC => nSYNC,
TEXT => TEXT,
GR => GR,
RED => RED,
GREEN => GREEN,
BLUE => BLUE,
nSYNCOUT => nSYNCOUT
);
VGA : entity work.vga_controller
port map(
CLK_14M => CLK14M,
nVIDEO => nSEROUT,
COLOR_LINE => GR,
CBL => nWNDW,
nLDPS => nLDPS,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B
);
end rtl;

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-------------------------------------------------------------------------------
--
-- A VGA line-doubler for an Apple ][
--
-- Stephen A. Edwards, sedwards.cs.columbia.edu
--
-- The Apple ][ uses a 14.31818 MHz master clock. It outputs a new
-- horizontal line every 65 * 14 + 2 = 912 14M cycles. The extra two
-- are from the "extended cycle" used to keep the 3.579545 MHz
-- colorburst signal in sync. Of these, 40 * 14 = 560 are active video.
--
-- In graphics mode, the Apple effectively generates 140 four-bit pixels
-- output serially (i.e., with 3.579545 MHz pixel clock). In text mode,
-- it generates 280 one-bit pixels (i.e., with a 7.15909 MHz pixel clock).
--
-- We capture 140 four-bit nibbles for each line and interpret them in
-- one of the two modes. In graphics mode, each is displayed as a
-- single pixel of one of 16 colors. In text mode, each is displayed
-- as two black or white pixels.
--
-- The VGA display is nominally 640 X 480, but we use a 14.31818 MHz
-- dot clock. To stay in sync with the Apple, we generate a new line
-- every 912 / 2 = 456 14M cycles= 31.8 us, a 31.4 kHz horizontal
-- refresh rate. Of these, 280 will be active video.
--
-- One set of suggested VGA timings:
--
-- ______________________ ________
-- ________| VIDEO |________| VIDEO
-- |-C-|----------D-----------|-E-|
-- __ ______________________________ ___________
-- |_| |_|
-- |B|
-- |---------------A----------------|
--
-- A = 31.77 us Scanline time
-- B = 3.77 us Horizontal sync time
-- C = 1.89 us Back porch
-- D = 25.17 us Active video
-- E = 0.94 us Front porch
--
-- We use A = 456 / 14.31818 MHz = 31.84 us
-- B = 54 / 14.31818 MHz = 3.77 us
-- C = 106 / 14.31818 MHz = 7.40 us
-- D = 280 / 14.31818 MHz = 19.56 us
-- E = 16 / 14.31818 MHz = 1.12 us
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_controller is
port (
CLK_14M : in std_logic; -- 14.31818 MHz master clock
nVIDEO : in std_logic;
COLOR_LINE : in std_logic;
CBL : in std_logic;
SRAM_nWE : out std_logic;
SRAM_nOE : out std_logic;
SRAM_nCE : out std_logic;
SRAM_addr : out unsigned(8 downto 0);
SRAM_data : inout unsigned(3 downto 0);
VGA_HS : out std_logic; -- Active low
VGA_VS : out std_logic; -- Active low
VGA_R : out std_logic_vector(1 downto 0);
VGA_G : out std_logic_vector(1 downto 0);
VGA_B : out std_logic_vector(1 downto 0);
MODE : in std_logic
);
end vga_controller;
architecture rtl of vga_controller is
--GE
signal HBL : std_logic := '0';
signal VBL : std_logic := '0';
signal SRAM_rd_data : unsigned(5 downto 0);
signal SRAM_wr_data : unsigned(3 downto 0);
signal SRAM_nWEi : std_logic;
signal SRAM_nOEi : std_logic;
signal SRAM_nCEi : std_logic;
signal RCOL : std_logic_vector(1 downto 0) := "00";
signal GCOL : std_logic_vector(1 downto 0) := "00";
signal BCOL : std_logic_vector(1 downto 0) := "00";
signal R : std_logic_vector(1 downto 0);
signal G : std_logic_vector(1 downto 0);
signal B : std_logic_vector(1 downto 0);
signal PIXPAT : unsigned(3 downto 0);
signal RAMPIXPAT : unsigned(5 downto 0);
signal COLPAT : unsigned(3 downto 0);
signal TEXT : std_logic;
signal ram_write_addr : unsigned(8 downto 0);
signal ram_we : std_logic;
signal ram_read_addr : unsigned(8 downto 0);
signal hcount : unsigned(9 downto 0);
signal hcount2 : unsigned(9 downto 0);
--GE signal vcount : unsigned(5 downto 0);
signal vcount : unsigned(6 downto 0);
signal even_line : std_logic := '0';
signal hactive : std_logic;
constant VGA_SCANLINE : integer := 456; -- Must be 456 (set by the Apple)
constant VGA_HSYNC : integer := 54;
constant VGA_BACK_PORCH : integer := 66;
constant VGA_ACTIVE : integer := 282; -- Must be 280 (set by the Apple)
constant VGA_FRONT_PORCH : integer := 54;
-- VGA_HSYNC + VGA_BACK_PORCH + VGA_ACTIVE + VGA_FRONT_PORCH = VGA_SCANLINE
--GE (org) constant VBL_TO_VSYNC : integer := 33;
--GE constant VBL_TO_VSYNC : integer := 80;
constant VBL_TO_VSYNC : integer := 55;
constant VGA_VSYNC_LINES : integer := 3;
signal VGA_VS_I, VGA_HS_I : std_logic;
signal video_active : std_logic;
signal vbl_delayed : std_logic;
signal color_line_delayed_1, color_line_delayed_2 : std_logic;
--GE 10/02/2009
signal cbl_last : std_logic;
signal cbl_count : unsigned(9 downto 0);
begin
--GE 10/02/2009
blank_sep2 : process(CLK_14M, CBL, cbl_last, cbl_count)
begin
if falling_edge(CLK_14M) then
cbl_count <= cbl_count + 1;
cbl_last <= CBL;
if (cbl_last = '0' and CBL = '1') then
cbl_count <= "1000100101"; -- 549
end if;
if (cbl_count = 911) then
cbl_count <= (others => '0');
VBL <= CBL;
color_line_delayed_2 <= color_line_delayed_1;
color_line_delayed_1 <= COLOR_LINE;
vbl_delayed <= VBL;
if VBL = '1' then
even_line <= '0';
vcount <= vcount + 1;
else
vcount <= (others => '0');
even_line <= not even_line;
end if;
end if;
if (cbl_count >= 549) and (cbl_count <= 899) then
HBL <= '1';
else
HBL <= '0';
end if;
end if;
end process;
hcount <= cbl_count;
hsync_gen : process (CLK_14M)
begin
if falling_edge(CLK_14M) then
if hcount = VGA_ACTIVE + VGA_FRONT_PORCH or
hcount = VGA_SCANLINE + VGA_ACTIVE + VGA_FRONT_PORCH then
VGA_HS_I <= '0';
elsif hcount = VGA_ACTIVE + VGA_FRONT_PORCH + VGA_HSYNC or
hcount = VGA_SCANLINE + VGA_ACTIVE + VGA_FRONT_PORCH + VGA_HSYNC then
VGA_HS_I <= '1';
end if;
if hcount = VGA_SCANLINE - 1 or
hcount = VGA_SCANLINE + VGA_SCANLINE - 1 then
hactive <= '1';
elsif hcount = VGA_ACTIVE or
hcount = VGA_ACTIVE + VGA_SCANLINE then
hactive <= '0';
end if;
end if;
end process hsync_gen;
VGA_HS <= VGA_HS_I;
vsync_gen : process (CLK_14M)
begin
if falling_edge(CLK_14M) then
if vcount = VBL_TO_VSYNC then
VGA_VS_I <= '0';
elsif vcount = VBL_TO_VSYNC + VGA_VSYNC_LINES then
VGA_VS_I <= '1';
end if;
end if;
end process vsync_gen;
VGA_VS <= VGA_VS_I;
-- Shift in the incoming bits to reconstruct four-bit groups
input_shift_register : process (CLK_14M)
begin
if falling_edge(CLK_14M) then
PIXPAT <= PIXPAT(2 downto 0) & nVIDEO;
end if;
end process input_shift_register;
hcount2 <= hcount - VGA_SCANLINE;
ram_read_addr <=
even_line & hcount(8 downto 1) when hcount < VGA_SCANLINE else
even_line & hcount2(8 downto 1);
ram_write_addr <= (not even_line) & hcount(9 downto 2);
ram_we <= '1' when hcount(1 downto 0) = "00" else '0';
video_active <= hactive and not vbl_delayed;
-- RGB values from Linards Ticmanis,
-- http://newsgroups.derkeiler.com/Archive/Comp/comp.sys.apple2/2005-09/msg00534.html
colorgen: process(COLPAT)
begin
case COLPAT is
when "1110" => -- 1 - 0x90 17 40
RCOL <= "10";
GCOL <= "00";
BCOL <= "01";
when "0111" => -- 2 - 0x40 2c a5
RCOL <= "01";
GCOL <= "00";
BCOL <= "10";
when "0110" => -- 3 - 0xd0 43 e5
RCOL <= "11";
GCOL <= "01";
BCOL <= "11";
when "1011" => -- 4 - 0x00 69 40
RCOL <= "00";
GCOL <= "01";
BCOL <= "01";
when "1010" => -- 5 - 0x80 80 80
RCOL <= "10";
GCOL <= "10";
BCOL <= "10";
when "0011" => -- 6 - 0x2f 95 e5
RCOL <= "00";
GCOL <= "10";
BCOL <= "11";
when "0010" => -- 7 - 0xbf ab ff
RCOL <= "11";
GCOL <= "10";
BCOL <= "11";
when "1101" => -- 8 - 0x40 54 00
RCOL <= "01";
GCOL <= "01";
BCOL <= "00";
when "1100" => -- 9 - 0xd0 6a 1a
RCOL <= "11";
GCOL <= "01";
BCOL <= "00";
when "0101" => -- 10 - 0x80 80 80
RCOL <= "01";
GCOL <= "01";
BCOL <= "01";
when "0100" => -- 11 - 0xff 96 bf
RCOL <= "11";
GCOL <= "10";
BCOL <= "11";
when "1001" => -- 12 - 0x2f bc 1a
RCOL <= "00";
GCOL <= "11";
BCOL <= "00";
when "1000" => -- 13 - 0xbf d3 5a
RCOL <= "11";
GCOL <= "11";
BCOL <= "01";
when "0001" => -- 14 - 0x6f e8 bf
RCOL <= "01";
GCOL <= "11";
BCOL <= "11";
when "0000" => -- 15 - 0xff ff ff
RCOL <= "11";
GCOL <= "11";
BCOL <= "11";
when others => -- 0 - 0x00 00 00
RCOL <= "00";
GCOL <= "00";
BCOL <= "00";
end case;
end process;
TEXT <= '1' when hcount(0) = '0' and CLK_14M = '0' and RAMPIXPAT(3) = '0'
else '1' when hcount(0) = '0' and CLK_14M = '1' and RAMPIXPAT(2) = '0'
else '1' when hcount(0) = '1' and CLK_14M = '0' and RAMPIXPAT(1) = '0'
else '1' when hcount(0) = '1' and CLK_14M = '1' and RAMPIXPAT(0) = '0'
else '0';
COLPAT <= RAMPIXPAT(3 downto 0) when hcount(0) = '1'
else RAMPIXPAT(3 downto 2) & RAMPIXPAT(5 downto 4);
--GE
SRAM_addr <= ram_read_addr when hcount(0) = '1' else ram_write_addr;
SRAM_nWEi <= not ram_we;
SRAM_nOEi <= '0' when hcount(0) = '1' else '1';
SRAM_nCEi <= CLK_14M;
process(CLK_14M)
begin
if rising_edge(CLK_14M) and SRAM_nOEi = '0' then
SRAM_rd_data <= SRAM_rd_data(1 downto 0) & SRAM_data;
end if;
end process;
process(CLK_14M)
begin
if falling_edge(CLK_14M) then
RAMPIXPAT <= SRAM_rd_data;
end if;
end process;
SRAM_wr_data <= PIXPAT;
SRAM_data <= SRAM_wr_data when SRAM_nCEi = '0' and SRAM_nWEi = '0' else "ZZZZ";
SRAM_nCE <= SRAM_nCEi;
SRAM_nOE <= SRAM_nOEi;
SRAM_nWE <= SRAM_nWEi;
R <= RCOL when video_active = '1' and color_line_delayed_2 = '1'
else TEXT & TEXT when video_active = '1' and color_line_delayed_2 = '0'
else "00";
G <= GCOL when video_active = '1' and color_line_delayed_2 = '1'
else TEXT & TEXT when video_active = '1' and color_line_delayed_2 = '0'
else "00";
B <= BCOL when video_active = '1' and color_line_delayed_2 = '1'
else TEXT & TEXT when video_active = '1' and color_line_delayed_2 = '0'
else "00";
VGA_R <= R when MODE = '1' else "00";
VGA_G <= G when MODE = '1' else TEXT & TEXT when video_active = '1' else "00";
VGA_B <= B when MODE = '1' else "00";
end rtl;