Fix building
Most patches are temporary and there just to let the code to build. It will not work in the current state. Also now force the use of paged memory. It was not working properly because of the way the old GPU code is working.
This commit is contained in:
120
source/memory.c
120
source/memory.c
@@ -63,6 +63,8 @@ extern nec_Regs I;
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void dump_memory()
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{
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// TODO: Need complete rewrite
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#if 0
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int i;
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FILE *fp;
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printf("Dumping memory....\n");
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@@ -103,118 +105,9 @@ void dump_memory()
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/* IP */
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fwrite(&I.ip, 1, 2, fp);
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fclose(fp);
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#endif
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}
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#ifndef USE_PAGED_MEMORY_ACCESS
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void mem_writemem20(uint32_t addr, uint8_t value)
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{
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uint32_t offset = addr & 0xffff;
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uint32_t bank = addr >> 16;
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if (!bank)
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{
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// 0 - RAM - 16 KB (WS) / 64 KB (WSC) internal RAM
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ws_gpu_write_byte(offset, value);
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ws_audio_write_byte(offset, value);
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}
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else if (bank == 1)
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{
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// 1 - SRAM (cart)
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ws_staticRam[offset & sramAddressMask] = value;
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}
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// other banks are read-only
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}
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uint8_t mem_readmem20(uint32_t addr)
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{
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uint32_t offset = addr & 0xffff;
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uint32_t bank = addr >> 16;
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//uint16_t romBank;
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uint8_t hwReg;
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uint32_t temp;
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uint8_t ret;
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wssystem_t currentSystem = ws_get_system();
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switch (bank)
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{
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case 0:
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/*
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* So the original WonderSwan, and Color/Crystal in B&W mode have 16KB of IRAM Mapped.
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* Color/Crystal in color mode have 64 KB IRAM mapped.
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*/
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if (ws_gpu_operatingInColor)
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{
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return (internalRam[offset]);
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}
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else if (offset < 0x4000)
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{
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return (internalRam[offset]);
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}
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return (0x90);
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case 1: // 1 - SRAM (cart)
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return ws_staticRam[offset & sramAddressMask];
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case 2:
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// Bank 2
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hwReg = ws_ioRam[0xC2];
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temp = hwReg << 16;
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temp += offset;
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temp &= (romSize - 1);
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return ws_rom[temp];
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case 3:
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// Bank 3
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hwReg = ws_ioRam[0xC3];
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temp = hwReg << 16;
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temp += offset;
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temp &= (romSize - 1);
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return ws_rom[temp];
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case 0xF:
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hwReg = ws_ioRam[0xA0];
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if (!(hwReg & 1))
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{
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if (currentSystem == WS_SYSTEM_COLOR && ws_haveColorIRom)
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{
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if (addr >= 0xFE000)
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{
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ret = internalColorIRom[addr & ~0xFE000];
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return ret;
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}
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}
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else if (currentSystem == WS_SYSTEM_CRYSTAL && ws_haveColorIRom)
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{
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if (addr >= 0xFE000)
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{
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ret = internalCrystalIRom[addr & ~0xFE000];
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return ret;
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}
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}
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else if (currentSystem == WS_SYSTEM_MONO && ws_haveBWIRom)
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{
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if (addr >= 0xFF000)
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{
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ret = internalBWIRom[addr & ~0xFF000];
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return ret;
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}
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}
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}
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// fall through
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default:
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hwReg = ws_ioRam[0xC0];
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temp = hwReg << 20;
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temp += addr & 0xFFFFF;
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temp &= (romSize - 1);
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return ws_rom[temp];
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}
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return (0x90);
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}
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#else
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/* 256 page of 12 bits */
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uint8_t *pagedMemory[0x100];
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@@ -330,7 +223,6 @@ void mem_dump_info()
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i, pagedMemory[i], i+1, pagedMemory[i+1], i+2, pagedMemory[i+2], i+3, pagedMemory[i+3]);
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}
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}
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#endif
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char *load_file(char *filename)
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{
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@@ -468,16 +360,11 @@ void ws_memory_init(uint8_t *rom, uint32_t wsRomSize)
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romAddressMask = romSize - 1;
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#ifdef USE_PAGED_MEMORY_ACCESS
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for(int i = 0; i < 0x100; i++)
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{
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pagedMemory[i] = NULL;
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}
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/* We start in B&W mode */
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set_iram_access(IRAM_LIMITED_ACCESS);
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/* Cart SRAM */
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if (sramSize > 0)
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{
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@@ -494,7 +381,6 @@ void ws_memory_init(uint8_t *rom, uint32_t wsRomSize)
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mem_dump_info();
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set_irom_overlay();
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#endif
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}
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void ws_memory_reset(void)
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