1252 lines
27 KiB
C
1252 lines
27 KiB
C
/*******************************************************************************
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* NewOswan
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* io.c: I/O ports implementaton
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* Based on the original Oswan-unix
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* Copyright (c) 2014-2021 986-Studio. All rights reserved.
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*
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******************************************************************************/
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//////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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//
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//
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//////////////////////////////////////////////////////////////////////////////
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <fcntl.h>
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#include <time.h>
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#include <unistd.h> /* UNIX standard function definitions */
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#include <errno.h> /* Error number definitions */
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#include <termios.h> /* POSIX terminal control definitions */
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#include <sys/mman.h>
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#include "log.h"
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#include "rom.h"
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#include "./nec/nec.h"
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#include "./nec/necintrf.h"
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#include "gpu.h"
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#include "audio.h"
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#include "memory.h"
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#include "ws.h"
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#include <stdbool.h>
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//#define IO_DUMP
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//define EEPROM_DEBUG
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extern uint8_t *externalEeprom;
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extern uint32_t romAddressMask;
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extern uint16_t *internalEeprom;
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extern nec_Regs I;
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extern uint64_t nec_monotonicCycles;
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extern uint32_t sramSize;
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enum
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{
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EEPROM_SUBCOMMAND = 0, /* 00 00 */
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EEPROM_WRITE, /* 01 xx */
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EEPROM_READ, /* 10 xx */
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EEPROM_ERASE, /* 11 xx */
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EEPROM_WRITEDISABLE, /* 00 00 */
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EEPROM_WRITEALL, /* 00 01 */
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EEPROM_ERASEALL, /* 00 10 */
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EEPROM_WRITEENABLE /* 00 11 */
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};
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char *eii_CommandName[] = {
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"SUB", "WRI", "RED", "ERA", "WRD", "WRA", "ERL", "WRE",
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};
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uint8_t iee_WriteEnable = false;
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uint16_t iee_SelAddress = 0;
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uint16_t iee_Databuffer = 0;
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uint8_t iee_Mode = EEPROM_READ;
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uint8_t cee_WriteEnable = true;
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uint16_t cee_SelAddress = 0;
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uint16_t cee_Databuffer = 0;
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uint8_t cee_Mode = EEPROM_READ;
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uint8_t *ws_ioRam = NULL;
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uint8_t ws_key_start;
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uint8_t ws_key_x4;
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uint8_t ws_key_x2;
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uint8_t ws_key_x1;
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uint8_t ws_key_x3;
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uint8_t ws_key_y4;
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uint8_t ws_key_y2;
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uint8_t ws_key_y1;
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uint8_t ws_key_y3;
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uint8_t ws_key_button_a;
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uint8_t ws_key_button_b;
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uint8_t ws_key_flipped;
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int rtcDataRegisterReadCount = 0;
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FILE *ioLogFp = NULL;
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////////////////////////////////////////////////////////////////////////////////
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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void ws_io_reset(void)
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{
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ws_key_start = 0;
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ws_key_x4 = 0;
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ws_key_x2 = 0;
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ws_key_x1 = 0;
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ws_key_x3 = 0;
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ws_key_y4 = 0;
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ws_key_y2 = 0;
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ws_key_y1 = 0;
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ws_key_y3 = 0;
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ws_key_button_a = 0;
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ws_key_button_b = 0;
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int i;
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for (i = 0 ; i < 0x100 ; i++)
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{
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/*
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* 0x90 should probably be a better value as for some reason
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* the Swan seems to like to returh 0x90 for not connected memory/IO
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* Keep 0x00 for now until the whole IO "default" value is solved.
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*/
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ws_ioRam[i] = 0x00;
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}
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ws_ioRam[0xC0] = 0xFF;
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ws_ioRam[0xC1] = 0xFF;
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ws_ioRam[0xC2] = 0xFF;
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ws_ioRam[0xC3] = 0xFF;
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rtcDataRegisterReadCount = 0;
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}
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////////////////////////////////////////////////////////////////////////////////
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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void ws_io_init(void)
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{
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if (ws_ioRam == NULL)
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{
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ws_ioRam = (uint8_t *)malloc(0x100);
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}
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ws_io_reset();
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ws_key_flipped = 0;
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#ifdef IO_DUMP
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ioLogFp = fopen("iodump.csv", "wt");
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#endif
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}
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////////////////////////////////////////////////////////////////////////////////
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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void ws_io_flipControls(void)
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{
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ws_key_flipped = !ws_key_flipped;
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}
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////////////////////////////////////////////////////////////////////////////////
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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void ws_io_done(void)
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{
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if (ws_ioRam == NULL)
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{
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free(ws_ioRam);
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}
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#ifdef IO_DUMP
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fclose(ioLogFp);
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#endif
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}
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/* Serial port */
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#define BDR_9600 (0)
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#define BDR_38400 (1)
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#define SERIAL_PORT "/dev/tty.USA19H141P1.1"
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int serialfd = -1;
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int serial_have_data = 0;
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unsigned char serial_data = 0;
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int serial_speed = BDR_9600;
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void open_serial()
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{
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if (serialfd < 0)
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{
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serialfd = open(SERIAL_PORT, O_RDWR | O_NOCTTY | O_NDELAY);
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//set_baudrate(serial_speed);
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serial_have_data = 0;
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}
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}
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void set_baudrate(int speed)
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{
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struct termios options;
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if (serialfd < 0)
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{
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return;
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}
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tcgetattr(serialfd, &options);
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options.c_cflag &= ~PARENB;
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options.c_cflag &= ~CSTOPB;
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options.c_cflag &= ~CSIZE;
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options.c_cflag |= CS8;
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if (speed == BDR_9600)
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{
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cfsetispeed(&options, B9600);
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}
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else
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{
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cfsetospeed(&options, B38400);
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}
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#if 0
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options.c_cflag &= ~CNEW_RTSCTS;
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#else
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options.c_cflag &= ~CRTSCTS;
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#endif
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options.c_cflag |= (CLOCAL | CREAD);
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options.c_lflag &= ~(ICANON | ECHO | ECHOE | ISIG);
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options.c_oflag &= ~OPOST;
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tcsetattr(serialfd, TCSANOW, &options);
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/* Make sure read is not blocking */
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fcntl(serialfd, F_SETFL, FNDELAY);
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}
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void close_serial()
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{
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close(serialfd);
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serialfd = -1;
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}
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void check_serial_data()
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{
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unsigned char buf[10];
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int f;
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if (serialfd < 0)
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{
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return;
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}
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if (serial_have_data == 0)
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{
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f = read(serialfd, buf, 1);
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if (f > 0)
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{
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Log(TLOG_DEBUG, "serial", "Have data from serial [%d]!", f);
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fflush(stdout);
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serial_have_data = 0x01;
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serial_data = buf[0];
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}
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}
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if (serial_have_data > 0)
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{
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/* Gen an int if enabled */
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if (ws_ioRam[0xB2] & 0x04)
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{
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ws_ioRam[0xb6] &= ~0x04;
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Log(TLOG_DEBUG, "serial", "SERIAL INNNNNTTTT!!!!!!!");
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nec_int((ws_ioRam[0xb0] + 3) * 4);
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}
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}
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}
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unsigned char read_serial()
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{
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unsigned char buf[10];
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int f;
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if (serialfd < 0)
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{
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return 0xFF;
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}
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if (serial_have_data > 0)
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{
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serial_have_data = 0;
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return serial_data;
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}
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f = read(serialfd, buf, 1);
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if (f == 1)
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{
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return buf[0];
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}
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return 0x42;
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}
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void write_serial(unsigned char value)
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{
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if (serialfd < 0)
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{
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return;
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}
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write(serialfd, &value, 1);
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}
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////////////////////////////////////////////////////////////////////////////////
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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uint8_t cpu_readport(uint8_t port)
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{
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int w1, w2;
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uint8_t retVal = 0;
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/*
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if (port > 0x100)
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{
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port &= 0xFF;
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if (port > 0x100)
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{
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return 0x00;
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}
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}
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*/
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switch (port)
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{
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case 0x4e:
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case 0x4f:
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case 0x50:
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case 0x51:
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case 0x80:
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case 0x81:
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case 0x82:
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case 0x83:
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case 0x84:
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case 0x85:
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case 0x86:
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case 0x87:
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case 0x88:
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case 0x89:
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case 0x8a:
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case 0x8b:
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case 0x8c:
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case 0x8d:
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case 0x8e:
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case 0x8f:
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case 0x90:
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case 0x91:
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case 0x92:
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case 0x93:
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case 0x94:
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retVal = ws_audio_port_read(port);
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break;
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case 0xb5:
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w1 = ws_ioRam[0xb5];
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if (w1 & 0x40)
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{
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w2 = 0x00;
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w2 = (ws_key_start << 1) | (ws_key_button_a << 2) | (ws_key_button_b << 3);
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retVal = (uint8_t)((w1 & 0xf0) | w2);
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break;
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}
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if (w1 & 0x20)
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{
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w2 = 0x00;
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w2 = (ws_key_x1 << 0) | (ws_key_x2 << 1) | (ws_key_x3 << 2) | (ws_key_x4 << 3);
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retVal = (uint8_t)((w1 & 0xf0) | w2);
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break;
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}
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if (w1 & 0x10)
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{
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w2 = 0x00;
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w2 = (ws_key_y1 << 0) | (ws_key_y2 << 1) | (ws_key_y3 << 2) | (ws_key_y4 << 3);
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retVal = (uint8_t)((w1 & 0xf0) | w2);
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}
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break;
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case 0xbe: // internal eeprom status/command register
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// ack eeprom write
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if (ws_ioRam[0xbe] & 0x20)
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{
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retVal = ws_ioRam[0xbe] | 2;
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break;
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}
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// ack eeprom read
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if (ws_ioRam[0xbe] & 0x10)
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{
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retVal = ws_ioRam[0xbe] | 1;
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break;
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}
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// else ack both
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retVal = ws_ioRam[0xbe] | 3;
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break;
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case 0x62:
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switch (ws_get_system())
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{
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case WS_SYSTEM_AUTODETECT:
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case WS_SYSTEM_MONO:
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case WS_SYSTEM_COLOR:
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retVal = 0x00;
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break;
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case WS_SYSTEM_CRYSTAL:
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retVal = 0x80;
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break;
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}
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break;
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case 0xba: // eeprom even byte read
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retVal = iee_Databuffer & 0x00FF;
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break;
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case 0xbb: // eeprom odd byte read
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retVal = (iee_Databuffer & 0xFF00) >> 8;
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break;
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case 0xc0 : // ???
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retVal = ((ws_ioRam[0xc0] & 0xf) | 0x20);
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goto exit;
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case 0xC8:
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// ack eeprom write
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if (ws_ioRam[0xbe] & 0x20)
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{
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retVal = ws_ioRam[0xbe] | 2;
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break;
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}
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// ack eeprom read
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if (ws_ioRam[0xbe] & 0x10)
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{
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retVal = ws_ioRam[0xbe] | 1;
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break;
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}
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// else ack both
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retVal = ws_ioRam[0xbe] | 3;
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break;
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case 0xC4: // eeprom even byte read
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return cee_Databuffer & 0x00FF;
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case 0xC5: // eeprom odd byte read
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return (cee_Databuffer & 0xFF00) >> 8;
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case 0xca : // RTC Command and status register
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// set ack to always 1
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retVal = (ws_ioRam[0xca] | 0x80);
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goto exit;
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|
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case 0xcb : // RTC data register
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if (ws_ioRam[0xca] == 0x15) // get time command
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{
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struct tm *newtime;
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time_t long_time;
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time(&long_time);
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newtime = localtime(&long_time);
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|
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#define BCD(value) ((value/10)<<4)|(value%10)
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|
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switch (rtcDataRegisterReadCount)
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{
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case 0:
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rtcDataRegisterReadCount++;
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retVal = BCD(newtime->tm_year - 100);
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goto exit;
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case 1:
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rtcDataRegisterReadCount++;
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retVal = BCD(newtime->tm_mon);
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goto exit;
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case 2:
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rtcDataRegisterReadCount++;
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retVal = BCD(newtime->tm_mday);
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goto exit;
|
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case 3:
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rtcDataRegisterReadCount++;
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retVal = BCD(newtime->tm_wday);
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goto exit;
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case 4:
|
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rtcDataRegisterReadCount++;
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retVal = BCD(newtime->tm_hour);
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goto exit;
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case 5:
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rtcDataRegisterReadCount++;
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retVal = BCD(newtime->tm_min);
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goto exit;
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|
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case 6:
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rtcDataRegisterReadCount = 0;
|
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retVal = BCD(newtime->tm_sec);
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goto exit;
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}
|
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|
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return 0;
|
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}
|
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else
|
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{
|
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// set ack
|
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retVal = (ws_ioRam[0xcb] | 0x80);
|
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goto exit;
|
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}
|
|
|
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case 0xD0:
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retVal = 0;
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goto exit;
|
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|
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/* Serial port link.. */
|
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case 0xB1:
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retVal = read_serial();
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Log(TLOG_DEBUG, "serial", "Read %02X", retVal);
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goto exit;
|
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|
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case 0xB3:
|
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check_serial_data();
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|
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if (ws_ioRam[0xB3] & 0x80)
|
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{
|
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retVal = (ws_ioRam[0xB3] & ~1) | serial_have_data | 0x04;
|
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}
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else
|
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{
|
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retVal = 0x00;
|
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}
|
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|
|
Log(TLOG_DEBUG, "serial", "<<<<RS232STA: %02X [%c%c%cxx%c%c%c]", retVal, (retVal & 0x80) ? 'E' : 'd',
|
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(retVal & 0x40) ? '3' : '9', (retVal & 0x20) ? 'R' : 'n', (retVal & 0x04) ? 'E' : 'f',
|
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(retVal & 0x02) ? 'V' : 'n', (retVal & 0x01) ? 'D' : 'e');
|
|
goto exit;
|
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|
|
case 0xCC:
|
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case 0xCD:
|
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retVal = 0;
|
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break;
|
|
|
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default:
|
|
retVal = ws_ioRam[port];
|
|
if (port > 0xD0)
|
|
{
|
|
Log(TLOG_DEBUG, "io", "ReadIO %02X <= %02X", port, retVal);
|
|
}
|
|
break;
|
|
|
|
case 0xA0:
|
|
case 0xAA:
|
|
case 0xAB:
|
|
case 0xAC:
|
|
case 0xAD:
|
|
retVal = ws_gpu_port_read(port);
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
if (port >= 0xC4)
|
|
{
|
|
Log(TLOG_DEBUG, "io", "ReadMBCIO(%02X) <= %02X", port, retVal);
|
|
}
|
|
|
|
|
|
exit:
|
|
if (ioLogFp)
|
|
{
|
|
fprintf(ioLogFp, "%ld, R, %02X, %02X\n", nec_monotonicCycles, port, retVal);
|
|
}
|
|
return retVal;
|
|
}
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
//
|
|
//
|
|
//
|
|
//
|
|
//
|
|
//
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
void cpu_writeport(uint32_t port, uint8_t value)
|
|
{
|
|
int unknown_io_port = 0;
|
|
|
|
if (ioLogFp)
|
|
{
|
|
fprintf(ioLogFp, "%ld, W, %02X, %02X\n", nec_monotonicCycles, port, value);
|
|
}
|
|
|
|
if (port > 0x100)
|
|
{
|
|
port &= 0xFF;
|
|
if (port > 0x100)
|
|
{
|
|
return;
|
|
}
|
|
}
|
|
|
|
if ((port == 0xA0) && (ws_ioRam[port] & 0x01) && (~value & 0x01))
|
|
{
|
|
value |= 0x01;
|
|
}
|
|
|
|
ws_ioRam[port] = value;
|
|
|
|
switch (port)
|
|
{
|
|
/* GPU IOs */
|
|
case 0x00:
|
|
Log(TLOG_DEBUG, "GPU", "Screen enabled: W2:%c W2M:%c, SW:%c, S:%c, S2:%c, S1:%c",
|
|
(value & 0x20)?'Y':'N',
|
|
(value & 0x10)?'I':'O',
|
|
(value & 0x08)?'Y':'N',
|
|
(value & 0x04)?'Y':'N',
|
|
(value & 0x02)?'Y':'N',
|
|
(value & 0x01)?'Y':'N');
|
|
break;
|
|
|
|
case 0x04:
|
|
if (ws_gpu_operatingInColor)
|
|
{
|
|
Log(TLOG_DEBUG, "GPU", "Sprite base: %04X", (value & 0x1F) << 9);
|
|
}
|
|
else
|
|
{
|
|
Log(TLOG_DEBUG, "GPU", "Sprite base: %04X", (value & 0x3F) << 9);
|
|
}
|
|
break;
|
|
case 0x07:
|
|
if (ws_gpu_operatingInColor)
|
|
{
|
|
Log(TLOG_DEBUG, "GPU", "Sprite Screen1 base: %04X", (value & 0x7) << 11);
|
|
Log(TLOG_DEBUG, "GPU", "Sprite Screen2 base: %04X", (value & 0x70) << (11-4));
|
|
}
|
|
else
|
|
{
|
|
Log(TLOG_DEBUG, "GPU", "Sprite Screen1 base: %04X", (value & 0xF) << 11);
|
|
Log(TLOG_DEBUG, "GPU", "Sprite Screen2 base: %04X", (value & 0xF0) << (11-4));
|
|
}
|
|
break;
|
|
case 0x10:
|
|
//Log(TLOG_DEBUG, "GPU", "Sprite Screen1 X scroll: %d", value);
|
|
break;
|
|
case 0x11:
|
|
//Log(TLOG_DEBUG, "GPU", "Sprite Screen1 T scroll: %d", value);
|
|
break;
|
|
case 0x12:
|
|
//Log(TLOG_DEBUG, "GPU", "Sprite Screen2 X scroll: %d", value);
|
|
break;
|
|
case 0x13:
|
|
//Log(TLOG_DEBUG, "GPU", "Sprite Screen2 Y scroll: %d", value);
|
|
break;
|
|
|
|
case 0x01:
|
|
case 0x02:
|
|
case 0x03:
|
|
case 0x05:
|
|
case 0x06:
|
|
case 0x08:
|
|
case 0x09:
|
|
case 0x0A:
|
|
case 0x0B:
|
|
case 0x0C:
|
|
case 0x0D:
|
|
case 0x0E:
|
|
case 0x0F:
|
|
case 0x14:
|
|
break;
|
|
|
|
case 0x15:
|
|
Log(TLOG_DEBUG, "io", "Icons %c %c %c %c %c %c %c %c", (value >> 7) & 1 ? '?' : ' ', (value >> 6) & 1 ? '?' : ' ',
|
|
(value >> 5) & 1 ? '3' : ' ', (value >> 4) & 1 ? '2' : ' ', (value >> 3) & 1 ? '1' : ' ',
|
|
(value >> 2) & 1 ? 'H' : ' ', (value >> 1) & 1 ? 'V' : ' ', (value >> 0) & 1 ? 'S' : ' ');
|
|
break;
|
|
|
|
/* Palettes ? */
|
|
case 0x1C:
|
|
case 0x25:
|
|
case 0x2F:
|
|
case 0x38:
|
|
case 0x1D:
|
|
case 0x26:
|
|
case 0x30:
|
|
case 0x39:
|
|
case 0x1E:
|
|
case 0x27:
|
|
case 0x31:
|
|
case 0x3A:
|
|
case 0x1F:
|
|
case 0x28:
|
|
case 0x32:
|
|
case 0x3B:
|
|
case 0x20:
|
|
case 0x29:
|
|
case 0x33:
|
|
case 0x3C:
|
|
case 0x21:
|
|
case 0x2A:
|
|
case 0x34:
|
|
case 0x3E:
|
|
case 0x22:
|
|
case 0x2B:
|
|
case 0x35:
|
|
case 0x3F:
|
|
case 0x23:
|
|
case 0x2C:
|
|
case 0x36:
|
|
case 0x24:
|
|
case 0x2E:
|
|
case 0x37:
|
|
break;
|
|
|
|
/* DMAs */
|
|
case 0x40:
|
|
case 0x41:
|
|
case 0x42:
|
|
case 0x43:
|
|
case 0x44:
|
|
case 0x45:
|
|
case 0x46:
|
|
case 0x47:
|
|
break;
|
|
|
|
case 0x48: // DMA
|
|
|
|
// bit 7 set to start dma transfer
|
|
if (value & 0x80)
|
|
{
|
|
int dma_start = (((uint32_t)ws_ioRam[0x41]) << 8) | (((uint32_t)ws_ioRam[0x40])) |
|
|
(((uint32_t)ws_ioRam[0x42]) << 16);
|
|
int dma_end = (((uint32_t)ws_ioRam[0x45]) << 8) | (((uint32_t)ws_ioRam[0x44])) |
|
|
(((uint32_t)ws_ioRam[0x43]) << 16);
|
|
int dma_size = (((uint32_t)ws_ioRam[0x47]) << 8) | (((uint32_t)ws_ioRam[0x46]));
|
|
|
|
for (int ix = 0 ; ix < dma_size ; ix++)
|
|
{
|
|
cpu_writemem20(dma_end++, cpu_readmem20(dma_start++));
|
|
}
|
|
|
|
ws_ioRam[0x47] = 0;
|
|
ws_ioRam[0x46] = 0;
|
|
ws_ioRam[0x41] = (uint8_t)(dma_start >> 8);
|
|
ws_ioRam[0x40] = (uint8_t)(dma_start & 0xff);
|
|
ws_ioRam[0x45] = (uint8_t)(dma_end >> 8);
|
|
ws_ioRam[0x44] = (uint8_t)(dma_end & 0xff);
|
|
ws_ioRam[0x48] = 0;
|
|
}
|
|
|
|
break;
|
|
|
|
/* Audio */
|
|
case 0x4a:
|
|
case 0x4b:
|
|
case 0x4c:
|
|
case 0x4d:
|
|
case 0x4e:
|
|
case 0x4f:
|
|
ws_audio_port_write(port, value);
|
|
break;
|
|
|
|
/* DMA Start! */
|
|
case 0x52:
|
|
break;
|
|
|
|
/* GPU (again) */
|
|
case 0x60:
|
|
break;
|
|
|
|
/* System */
|
|
case 0x62:
|
|
Log(TLOG_DEBUG, "io", "HeyHo!");
|
|
break;
|
|
|
|
/* Audio */
|
|
case 0x80:
|
|
case 0x81:
|
|
case 0x82:
|
|
case 0x83:
|
|
case 0x84:
|
|
case 0x85:
|
|
case 0x86:
|
|
case 0x87:
|
|
case 0x88:
|
|
case 0x89:
|
|
case 0x8a:
|
|
case 0x8b:
|
|
case 0x8c:
|
|
case 0x8d:
|
|
case 0x8e:
|
|
case 0x8f:
|
|
case 0x90:
|
|
case 0x91:
|
|
case 0x92:
|
|
case 0x93:
|
|
case 0x94:
|
|
case 0x95:
|
|
case 0x96:
|
|
case 0x97:
|
|
case 0x98:
|
|
case 0x99:
|
|
case 0x9A:
|
|
case 0x9B:
|
|
case 0x9C:
|
|
case 0x9D:
|
|
case 0x9E:
|
|
ws_audio_port_write(port, value);
|
|
break;
|
|
|
|
/* Hardware */
|
|
case 0xA0:
|
|
|
|
/* Force cart handshake to be set */
|
|
ws_ioRam[port] |= 0x80;
|
|
|
|
#ifdef USE_PAGED_MEMORY_ACCESS
|
|
if (value & 0x01)
|
|
{
|
|
Log(TLOG_WARNING, "A0", "Oh yeah %02X BABY", value);
|
|
uint32_t romSize;
|
|
uint8_t *rom = getRom(&romSize);
|
|
set_memory_bank(0xF, ws_get_page_ptr(rom, romSize, (ws_ioRam[0xC0] & 0x0F << 4) + 0x0F));
|
|
}
|
|
break;
|
|
#endif
|
|
/* Timers */
|
|
case 0xA2:
|
|
case 0xA4:
|
|
case 0xA5:
|
|
case 0xA6:
|
|
case 0xA7:
|
|
case 0xA8:
|
|
case 0xA9:
|
|
case 0xAA:
|
|
case 0xAB:
|
|
break;
|
|
|
|
|
|
/* Intc */
|
|
case 0xB0:
|
|
case 0xB2:
|
|
case 0xB4:
|
|
case 0xB6:
|
|
break;
|
|
|
|
/* Serial */
|
|
case 0xB1:
|
|
write_serial(value);
|
|
break;
|
|
|
|
case 0xB3:
|
|
Log(TLOG_DEBUG, "serial", ">>>>RS232STA: %02X [%c%c%cxx%c%c%c]", value, (value & 0x80) ? 'E' : 'd', (value & 0x40) ? '3' : '9',
|
|
(value & 0x20) ? 'R' : 'n', (value & 0x04) ? 'E' : 'f', (value & 0x02) ? 'V' : 'n',
|
|
(value & 0x01) ? 'D' : 'e');
|
|
|
|
/* Serial status: 7 = Enable, 6 = baudrate, 5 = Overrun reset
|
|
2 = Send Buffer empty
|
|
1 = Overrun
|
|
0 = Data Received
|
|
*/
|
|
serial_speed = ((value & 040) == 0x00) ? BDR_9600 : BDR_38400;
|
|
|
|
if ((value & 0x80) == 0x80)
|
|
{
|
|
open_serial();
|
|
set_baudrate(serial_speed);
|
|
check_serial_data();
|
|
}
|
|
|
|
break;
|
|
|
|
/* buttons */
|
|
case 0xB5:
|
|
break;
|
|
|
|
/* Internal EEPROM */
|
|
case 0xba: /* DATA Low */
|
|
iee_Databuffer = iee_Databuffer & 0xFF00;
|
|
iee_Databuffer = iee_Databuffer | (value);
|
|
break;
|
|
|
|
case 0xbb: /* Data High */
|
|
iee_Databuffer = iee_Databuffer & 0x00FF;
|
|
iee_Databuffer = iee_Databuffer | (value << 8);
|
|
break;
|
|
|
|
case 0xBC: /* Address Low */
|
|
case 0xBD: /* Address High */
|
|
break;
|
|
|
|
case 0xBE: /* Command / Status */
|
|
{
|
|
uint16_t address, command, subcmd;
|
|
|
|
iee_SelAddress = (ws_ioRam[0xBD] << 8) | ws_ioRam[0xBC];
|
|
|
|
if (ws_gpu_operatingInColor)
|
|
{
|
|
/*
|
|
13 00
|
|
S CCaa AAAA AAAA
|
|
0001 0011 0000 0000
|
|
|
|
*/
|
|
/* S CC aaAAAAAAAA */
|
|
command = (iee_SelAddress >> 10) & 0x3;
|
|
address = iee_SelAddress & 0x3FF;
|
|
subcmd = (iee_SelAddress >> 8) & 0x03;
|
|
}
|
|
else
|
|
{
|
|
/* S CC aaAAAA */
|
|
command = (iee_SelAddress >> 6) & 0x3;
|
|
address = iee_SelAddress & 0x3F;
|
|
subcmd = (iee_SelAddress >> 4) & 0x03;
|
|
}
|
|
|
|
|
|
if (command == EEPROM_SUBCOMMAND)
|
|
{
|
|
command = EEPROM_WRITEDISABLE + subcmd;
|
|
}
|
|
#ifdef EEPROM_DEBUG
|
|
printf("IEEP: RA:%04X RD:%04X A:%03X C:%s", iee_SelAddress, iee_Databuffer, address, eii_CommandName[command]);
|
|
#endif
|
|
if (value & 0x40)
|
|
{
|
|
/* Sub command */
|
|
#ifdef EEPROM_DEBUG
|
|
printf(" - Sub");
|
|
#endif
|
|
if (command == EEPROM_WRITEENABLE)
|
|
{
|
|
#ifdef EEPROM_DEBUG
|
|
printf(" Write Enable\n");
|
|
#endif
|
|
iee_WriteEnable = true;
|
|
}
|
|
else if (command == EEPROM_WRITEDISABLE)
|
|
{
|
|
#ifdef EEPROM_DEBUG
|
|
printf(" Write Disable\n");
|
|
#endif
|
|
iee_WriteEnable = false;
|
|
}
|
|
else if (command == EEPROM_ERASEALL)
|
|
{
|
|
#ifdef EEPROM_DEBUG
|
|
printf(" Erase All\n");
|
|
#endif
|
|
if (ws_gpu_operatingInColor)
|
|
{
|
|
memset(internalEeprom, 0, COLOR_IEEPROM_SIZE);
|
|
}
|
|
else
|
|
{
|
|
memset(internalEeprom, 0, BW_IEEPROM_SIZE);
|
|
}
|
|
}
|
|
#ifdef EEPROM_DEBUG
|
|
else
|
|
{
|
|
printf(" Write All?\n");
|
|
}
|
|
#endif
|
|
}
|
|
else if (value & 0x20)
|
|
{
|
|
/* Write */
|
|
#ifdef EEPROM_DEBUG
|
|
printf(" - Write?");
|
|
#endif
|
|
if (iee_WriteEnable)
|
|
{
|
|
#ifdef EEPROM_DEBUG
|
|
printf(" Yes : %04X\n", iee_Databuffer);
|
|
#endif
|
|
internalEeprom[address] = iee_Databuffer;
|
|
}
|
|
#ifdef EEPROM_DEBUG
|
|
else
|
|
{
|
|
printf(" No\n");
|
|
}
|
|
#endif
|
|
}
|
|
else if (value & 0x10)
|
|
{
|
|
/* Read */
|
|
#ifdef EEPROM_DEBUG
|
|
printf(" - Read");
|
|
#endif
|
|
iee_Databuffer = internalEeprom[address];
|
|
#ifdef EEPROM_DEBUG
|
|
printf(" Data : %04X\n", iee_Databuffer);
|
|
#endif
|
|
}
|
|
#ifdef EEPROM_DEBUG
|
|
else
|
|
{
|
|
printf(" Unknown value: %02X\n", value);
|
|
}
|
|
#endif
|
|
fflush(stdout);
|
|
}
|
|
break;
|
|
|
|
|
|
/* MBC */
|
|
#ifndef USE_PAGED_MEMORY_ACCESS
|
|
case 0xC0:
|
|
case 0xC1:
|
|
case 0xC2:
|
|
case 0xC3:
|
|
break;
|
|
#else
|
|
case 0xC0:
|
|
{
|
|
/* page 4 to F */
|
|
uint32_t romSize;
|
|
uint8_t *rom = getRom(&romSize);
|
|
for (int i = 0x04 ; i < 0x10 ; i++)
|
|
{
|
|
set_memory_bank(i, ws_get_page_ptr(rom, romSize, (value << 4) + i));
|
|
}
|
|
|
|
if (!(ws_ioRam[0xA0] & 0x01))
|
|
{
|
|
set_irom_overlay();
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0xC1:
|
|
/* Sram bank */
|
|
if (sramSize > 0)
|
|
{
|
|
uint32_t sramSize;
|
|
uint8_t *sram = getSram(&sramSize);
|
|
set_memory_bank(0x1, ws_get_page_ptr(sram, sramSize, value));
|
|
}
|
|
break;
|
|
|
|
case 0xC2:
|
|
{
|
|
/* page 4 to F */
|
|
uint32_t romSize;
|
|
uint8_t *rom = getRom(&romSize);
|
|
/* Page 2 */
|
|
set_memory_bank(0x2, ws_get_page_ptr(rom, romSize, value));
|
|
break;
|
|
}
|
|
|
|
case 0xC3:
|
|
{
|
|
/* page 4 to F */
|
|
uint32_t romSize;
|
|
uint8_t *rom = getRom(&romSize);
|
|
/* Page 3 */
|
|
set_memory_bank(0x3, ws_get_page_ptr(rom, romSize, value));
|
|
break;
|
|
}
|
|
|
|
#endif
|
|
|
|
/* Cart EEPROM */
|
|
case 0xC4: /* Data High */
|
|
cee_Databuffer = cee_Databuffer & 0xFF00;
|
|
cee_Databuffer = cee_Databuffer | (value);
|
|
break;
|
|
|
|
case 0xC5: /* Data High */
|
|
cee_Databuffer = cee_Databuffer & 0x00FF;
|
|
cee_Databuffer = cee_Databuffer | (value << 8);
|
|
break;
|
|
|
|
case 0xC6: /* Address Low */
|
|
case 0xC7: /* Address High */
|
|
break;
|
|
|
|
case 0xC8: /* Command / Status */
|
|
{
|
|
uint16_t address, command, subcmd; /*, start;*/
|
|
|
|
cee_SelAddress = (ws_ioRam[0xBD] << 8) | ws_ioRam[0xBC];
|
|
|
|
/* S CC aaAAAA */
|
|
command = (cee_SelAddress >> 6) & 0x3;
|
|
address = cee_SelAddress & 0x3F;
|
|
subcmd = (cee_SelAddress >> 4) & 0x03;
|
|
|
|
|
|
if (command == EEPROM_SUBCOMMAND)
|
|
{
|
|
command = EEPROM_WRITEDISABLE + subcmd;
|
|
}
|
|
|
|
printf("CEEP: RA:%04X RD:%04X A:%03X C:%s", cee_SelAddress, cee_Databuffer, address, eii_CommandName[command]);
|
|
|
|
if (value & 0x40)
|
|
{
|
|
/* Sub command */
|
|
printf(" - Sub");
|
|
if (command == EEPROM_WRITEENABLE)
|
|
{
|
|
printf(" Write Enable\n");
|
|
cee_WriteEnable = true;
|
|
}
|
|
else if (command == EEPROM_WRITEDISABLE)
|
|
{
|
|
printf(" Write Disable\n");
|
|
cee_WriteEnable = false;
|
|
}
|
|
else if (command == EEPROM_ERASEALL)
|
|
{
|
|
printf(" Erase All\n");
|
|
/* Nothing here at the moment */
|
|
}
|
|
else
|
|
{
|
|
printf(" Write All?\n");
|
|
}
|
|
}
|
|
else if (value & 0x20)
|
|
{
|
|
/* Write */
|
|
printf(" - Write?");
|
|
if (cee_WriteEnable)
|
|
{
|
|
printf(" Yes : %04X\n", cee_Databuffer);
|
|
externalEeprom[address] = cee_Databuffer;
|
|
}
|
|
else
|
|
{
|
|
printf(" No\n");
|
|
}
|
|
}
|
|
else if (value & 0x10)
|
|
{
|
|
/* Read */
|
|
printf(" - Read");
|
|
cee_Databuffer = externalEeprom[address];
|
|
printf(" Data : %04X\n", cee_Databuffer);
|
|
}
|
|
else
|
|
{
|
|
printf(" Unknown value: %02X@", value);
|
|
}
|
|
fflush(stdout);
|
|
}
|
|
break;
|
|
|
|
case 0xca:
|
|
if (value == 0x15)
|
|
{
|
|
rtcDataRegisterReadCount = 0;
|
|
}
|
|
|
|
break;
|
|
break;
|
|
|
|
case 0xCB:
|
|
break;
|
|
|
|
case 0xF0:
|
|
break;
|
|
|
|
case 0xF1:
|
|
printf("%d\n", (signed short)((value << 8) | ws_ioRam[0xF0]));
|
|
break;
|
|
|
|
case 0xF2:
|
|
printf("%c", value);
|
|
fflush(stdout);
|
|
break;
|
|
|
|
case 0xB7:
|
|
break; /* Somwthing to write there, but what? */
|
|
|
|
default:
|
|
unknown_io_port = 1;
|
|
}
|
|
|
|
if ((ws_gpu_port_write(port, value) == 1) && (unknown_io_port == 1))
|
|
{
|
|
Log(TLOG_DEBUG, "io", "WriteIO(%02X, %02X) [%04X:%04Xh];", port, value, I.sregs[CS], I.ip);
|
|
}
|
|
|
|
if (port >= 0xC4)
|
|
{
|
|
Log(TLOG_DEBUG, "io", "WriteMBCIO(%02X, %02X);", port, value);
|
|
}
|
|
}
|