@macro op_branch(name, condition)
  void {class}::op_{name}() {
    if({condition} == false) {
{lc}  rd.l = op_readpc();
    } else {
      rd.l = op_readpc();
      aa.w = regs.pc.d + (int8_t)rd.l;
      op_io_cond6(aa.w);
{lc}  op_io();
      regs.pc.w = aa.w;
    }
  }
@endmacro

@macro op_bra()
  void {class}::op_bra() {
    rd.l = op_readpc();
    aa.w = regs.pc.d + (int8_t)rd.l;
    op_io_cond6(aa.w);
{lc}op_io();
    regs.pc.w = aa.w;
  }
@endmacro

@macro op_brl()
  void {class}::op_brl() {
    rd.l = op_readpc();
    rd.h = op_readpc();
{lc}op_io();
    regs.pc.w = regs.pc.d + (int16_t)rd.w;
  }
@endmacro

@macro op_jmp_addr()
  void {class}::op_jmp_addr() {
    rd.l = op_readpc();
{lc}rd.h = op_readpc();
    regs.pc.w = rd.w;
  }
@endmacro

@macro op_jmp_long()
  void {class}::op_jmp_long() {
    rd.l = op_readpc();
    rd.h = op_readpc();
{lc}rd.b = op_readpc();
    regs.pc.d = rd.d & 0xffffff;
  }
@endmacro

@macro op_jmp_iaddr()
  void {class}::op_jmp_iaddr() {
    aa.l = op_readpc();
    aa.h = op_readpc();
    rd.l = op_readaddr(aa.w + 0);
{lc}rd.h = op_readaddr(aa.w + 1);
    regs.pc.w = rd.w;
  }
@endmacro

@macro op_jmp_iaddrx()
  void {class}::op_jmp_iaddrx() {
    aa.l = op_readpc();
    aa.h = op_readpc();
    op_io();
    rd.l = op_readpbr(aa.w + regs.x.w + 0);
{lc}rd.h = op_readpbr(aa.w + regs.x.w + 1);
    regs.pc.w = rd.w;
  }
@endmacro

@macro op_jmp_iladdr()
  void {class}::op_jmp_iladdr() {
    aa.l = op_readpc();
    aa.h = op_readpc();
    rd.l = op_readaddr(aa.w + 0);
    rd.h = op_readaddr(aa.w + 1);
{lc}rd.b = op_readaddr(aa.w + 2);
    regs.pc.d = rd.d & 0xffffff;
  }
@endmacro

@macro op_jsr_addr()
  void {class}::op_jsr_addr() {
    aa.l = op_readpc();
    aa.h = op_readpc();
    op_io();
    regs.pc.w--;
    op_writestack(regs.pc.h);
{lc}op_writestack(regs.pc.l);
    regs.pc.w = aa.w;
  }
@endmacro

@macro op_jsr_long()
  void {class}::op_jsr_long_e() {
    aa.l = op_readpc();
    aa.h = op_readpc();
    op_writestackn(regs.pc.b);
    op_io();
    aa.b = op_readpc();
    regs.pc.w--;
    op_writestackn(regs.pc.h);
{lc}op_writestackn(regs.pc.l);
    regs.pc.d = aa.d & 0xffffff;
    regs.s.h = 0x01;
  }

  void {class}::op_jsr_long_n() {
    aa.l = op_readpc();
    aa.h = op_readpc();
    op_writestackn(regs.pc.b);
    op_io();
    aa.b = op_readpc();
    regs.pc.w--;
    op_writestackn(regs.pc.h);
{lc}op_writestackn(regs.pc.l);
    regs.pc.d = aa.d & 0xffffff;
  }
@endmacro

@macro op_jsr_iaddrx()
  void {class}::op_jsr_iaddrx_e() {
    aa.l = op_readpc();
    op_writestackn(regs.pc.h);
    op_writestackn(regs.pc.l);
    aa.h = op_readpc();
    op_io();
    rd.l = op_readpbr(aa.w + regs.x.w + 0);
{lc}rd.h = op_readpbr(aa.w + regs.x.w + 1);
    regs.pc.w = rd.w;
    regs.s.h = 0x01;
  }

  void {class}::op_jsr_iaddrx_n() {
    aa.l = op_readpc();
    op_writestackn(regs.pc.h);
    op_writestackn(regs.pc.l);
    aa.h = op_readpc();
    op_io();
    rd.l = op_readpbr(aa.w + regs.x.w + 0);
{lc}rd.h = op_readpbr(aa.w + regs.x.w + 1);
    regs.pc.w = rd.w;
  }
@endmacro

@macro op_rti()
  void {class}::op_rti_e() {
    op_io();
    op_io();
    regs.p = op_readstack() | 0x30;
    rd.l = op_readstack();
{lc}rd.h = op_readstack();
    regs.pc.w = rd.w;
  }

  void {class}::op_rti_n() {
    op_io();
    op_io();
    regs.p = op_readstack();
    if(regs.p.x) {
      regs.x.h = 0x00;
      regs.y.h = 0x00;
    }
    rd.l = op_readstack();
    rd.h = op_readstack();
{lc}rd.b = op_readstack();
    regs.pc.d = rd.d & 0xffffff;
    update_table();
  }
@endmacro

@macro op_rts()
  void {class}::op_rts() {
    op_io();
    op_io();
    rd.l = op_readstack();
    rd.h = op_readstack();
{lc}op_io();
    regs.pc.w = ++rd.w;
  }
@endmacro

@macro op_rtl()
  void {class}::op_rtl_e() {
    op_io();
    op_io();
    rd.l = op_readstackn();
    rd.h = op_readstackn();
{lc}rd.b = op_readstackn();
    regs.pc.b = rd.b;
    regs.pc.w = ++rd.w;
    regs.s.h = 0x01;
  }

  void {class}::op_rtl_n() {
    op_io();
    op_io();
    rd.l = op_readstackn();
    rd.h = op_readstackn();
{lc}rd.b = op_readstackn();
    regs.pc.b = rd.b;
    regs.pc.w = ++rd.w;
  }
@endmacro
